Comments on: Verilog: Declaring each port (or argument) once https://billauer.se/blog/2009/07/verilog-standard-short-port-declaration-output-reg-autoarg/ Anything I found worthy to write down. Thu, 26 Mar 2026 13:15:15 +0000 hourly 1 http://wordpress.org/?v=3.1.2 By: Michael https://billauer.se/blog/2009/07/verilog-standard-short-port-declaration-output-reg-autoarg/comment-page-1/#comment-1596 Michael Thu, 12 May 2022 12:23:02 +0000 https://billauer.se/blog/?p=324#comment-1596 When using the concise format, it is impossible to pass structs between modules When using the concise format, it is impossible to pass structs between modules

]]> By: Evgeni https://billauer.se/blog/2009/07/verilog-standard-short-port-declaration-output-reg-autoarg/comment-page-1/#comment-886 Evgeni Fri, 09 Aug 2013 17:57:37 +0000 https://billauer.se/blog/?p=324#comment-886 One use of duplicated port declaration I've seen was in netlisting tool that converted transistor-level schematics into Verilog netlist. This was part of a fully custom chip design flow. The tool was generating code like this: module example( my_signal1[0], my_signal2[1:0], {my_signal1[1], my_signal2[2]} ); input [1:0] my_signal1; input [2:0] my_signal2; Don't know the reason why it did it that way. But it took advantage of the fact that Verilog allows flexible grouping of the module IO signals. Thanks, Evgeni One use of duplicated port declaration I’ve seen was in netlisting tool that converted transistor-level schematics into Verilog netlist. This was part of a fully custom chip design flow.

The tool was generating code like this:

module example( my_signal1[0], my_signal2[1:0],
{my_signal1[1], my_signal2[2]} );
input [1:0] my_signal1;
input [2:0] my_signal2;

Don’t know the reason why it did it that way. But it took advantage of the fact that Verilog allows flexible grouping of the module IO signals.

Thanks,
Evgeni

]]> By: Tim https://billauer.se/blog/2009/07/verilog-standard-short-port-declaration-output-reg-autoarg/comment-page-1/#comment-861 Tim Fri, 12 Apr 2013 14:21:07 +0000 https://billauer.se/blog/?p=324#comment-861 This is priceless! Having switched from VHDL to Verilog, I was always annoyed with these double port declarations. This easily cuts out a hundred lines of useless code. This is priceless! Having switched from VHDL to Verilog, I was always annoyed with these double port declarations. This easily cuts out a hundred lines of useless code.

]]> By: eli https://billauer.se/blog/2009/07/verilog-standard-short-port-declaration-output-reg-autoarg/comment-page-1/#comment-414 eli Tue, 06 Apr 2010 19:45:05 +0000 https://billauer.se/blog/?p=324#comment-414 I suppose there was some inside sabotage by VHDL guys. I suppose there was some inside sabotage by VHDL guys.

]]> By: Andy https://billauer.se/blog/2009/07/verilog-standard-short-port-declaration-output-reg-autoarg/comment-page-1/#comment-413 Andy Tue, 06 Apr 2010 19:39:12 +0000 https://billauer.se/blog/?p=324#comment-413 I agree this format is much more concise and easier to read. I wonder what the reasoning was in Verilog 95 for requiring the dual input/output declaration? I agree this format is much more concise and easier to read. I wonder what the reasoning was in Verilog 95 for requiring the dual input/output declaration?

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