Comments on: PCI express from a Xilinx/Altera FPGA to a Linux machine: Making it easy

By: eli

eli — Wed, 25 Apr 2012 06:58:37 +0000

Questions & Comments Since the comment section of similar posts tend to turn into a Q & A session, I’ve taken that to a separate place. So if you’d like to discuss something with me, please post questions and comments here instead. No registration is required. This comment section is closed.

By: eli

eli — Thu, 22 Mar 2012 15:09:43 +0000

If we’ll take the SPI as an example, the FPGA logic will need to serialize/deserialize the data and then connect it with a standard FIFO. This is not completely trivial if you’re not experienced with FPGA design, but this logic has to be there this way or another.

As for the Linux side, there is no work at all. Xillybus gives you the data directly through a device file interface.

By: Diego

Diego — Thu, 22 Mar 2012 13:43:05 +0000

Hi there!

First of all, I’m not a FPGA guy. I’m a linux device drivers developer.

I’m working in a project which has some communication (i2c,spi and MDIO) will be performed by the FPGA. The CPU will access these buses via PCI Express.
What has to be done in FPGA and PICe linux device driver to allow kernel to see the communication interfaces?

By: eli

eli — Wed, 29 Feb 2012 09:28:47 +0000

Regarding where the data can be “found” when you don’t use Xillybus: The data isn’t stored anywhere. It arrives as packets which you need to handle one by one with a state machine you develop. On the PC side, yes, you need to develop or adopt some kind of driver.

As for the throughput: All data transfers are initiated by the FPGA (“Initiator”). There is no exact meaning to packet size and transfer size when working with Xillybus, because the system presents a stream interface. So basically, I just ran a program that reads or writes to a file descriptor as fast as possible (typically a few GBs), and divided the amount of data with the time elapsed.

By: Smith

Smith — Wed, 29 Feb 2012 06:42:35 +0000

Thanks Eli for the response on Xillybus throughput. Below are my definition on Initiator & Target.

Initiator (or Master): FPGA has DMA type functionality and can transfer the data from FPGA to Host without requiring Memory Read packets from the Host.

Target: This is more like Slave where the Host initiates all write/read transactions and FPGA just responds to Memory Writes and Memory read packets.

What packet size and transfer size did you use for throughput calculations?

By: harini

harini — Wed, 29 Feb 2012 06:29:56 +0000

i am new to fpga and pcie so without using xillybus cant we know the exact location of where the data is stored in fpga by pcie and also when pcie is connected to the linux should we have a kernal module to transfer the data from pc????

By: eli

eli — Tue, 28 Feb 2012 09:45:58 +0000

In the FPGA, you’ll fetch the data from a standard FIFO. This is explained in Xillybus’ site.

By: harini

harini — Tue, 28 Feb 2012 07:36:20 +0000

hi,i am working on a project where i need to send the data from the pc to fpga(virtex6) through pcie on linux.and i need to know where the data is storing on the fpga so that i can retrive it and again process it and send it to mac layer.

By: eli

eli — Mon, 27 Feb 2012 15:34:02 +0000

I’m not 100% sure I understood your question, so I’ll try the best I can.

Throughput: The upstream (from FPGA) direction offers 200 MB/s. Downstream gives slightly lower than 100 MB/s for a single stream, but two independent streams can run in parallel and reach a total of nearly 200 MB/s.
All this holds for a 1x connection as offered by Spartan-6T. Virtex-6 goes higher.

Flow control: FPGA logic interfaces with a FIFO’s empty or full lines. The rest of the flow control is handled by Xillybus’ logic and drivers transparently, much by sensing the FIFO’s control signals on the other side.

By: Smith

Smith — Mon, 27 Feb 2012 15:15:28 +0000

Does Xillybus IP has both PCIe Initiator & Target functionality in FPGA? What is the achieved PCIe throughput in Spartan-6 with Linux/Windows driver assuming the user interface does not apply any back pressure/flow control?

I am looking at an application which needs 100MB/sec in each direction.

Thanks