Comments on: Synthesizing a black-box binary IP core with XST

By: eli

eli — Mon, 17 Jun 2013 20:28:18 +0000

Again — it was ISE 9.2.

Anyhow, the option is available in ISE under the XST’s process’ properties > Xilinx Specific Options.

Don’t know exactly where it’s to be found on 13.1.

By: tom jones

tom jones — Mon, 17 Jun 2013 20:24:53 +0000

Sorry – I should RTFM.

Also, the option is still available as of 13.1 but not called out in the GUI – just add “-iobuf no” to add’l command-line options.

By: tom jones

tom jones — Mon, 17 Jun 2013 20:19:48 +0000

What version of ISE did you use? I remember unchecking the “Add I/O Buffers” before for trial routes with fresh RTL but I can’t seem to find it on 13.1.

By: eli

eli — Fri, 22 Mar 2013 01:59:56 +0000

It was ISE 9.2, as mentioned in the post.

By: Alex

Alex — Fri, 22 Mar 2013 01:56:34 +0000

That is brilliant. Thank you for posting this info. May I ask which version of ISE did you use?

By: Mohanavel

Mohanavel — Wed, 27 Jul 2011 05:39:03 +0000

Hi…
currently im trying to use ngc file in project navigater, i have done removing of I/O buffer in stynthesis option, copied ngc file into project directory and add as a black_box, but still im not getting behavioral simulation output. plz can u help me…?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

—- Uncomment the following library declaration if instantiating
—- any Xilinx primitives in this code.
–library UNISIM;
–use UNISIM.VComponents.all;

entity AND_Gate_BB is
port(
T_clk : in std_logic;
T_a,T_b,T_c : in std_logic;
T_x,T_y,T_z : out std_logic
);
end AND_Gate_BB;

architecture Behavioral of AND_Gate_BB is

component AND_Gate
port(
clk : in std_logic;
a,b,c : in std_logic;
x,y,z : out std_logic
);
end component;

attribute syn_black_box : boolean;
attribute syn_black_box of AND_Gate: component is true;

begin

BB: AND_Gate
port map(
clk => T_clk,
a => T_a,
b => T_b,
c => T_c,
x => T_x,
y => T_y,
z => T_z
);
end Behavioral;