Comments on: Embedded PC talking with an FPGA: Make it simple https://billauer.se/blog/2011/07/pc-104-embedded-pc-fpga-usb-ethernet/ Anything I found worthy to write down. Thu, 26 Mar 2026 13:15:15 +0000 hourly 1 http://wordpress.org/?v=3.1.2 By: eli https://billauer.se/blog/2011/07/pc-104-embedded-pc-fpga-usb-ethernet/comment-page-1/#comment-1268 eli Sat, 17 Jun 2017 07:29:14 +0000 https://billauer.se/blog/?p=1437#comment-1268 It's DMA controlled by the FPGA, of course. I/O-capable DMA controllers/engines is something found on some embedded processors and DSPs, not on x86-like platforms (not that I've seen, anyhow). And this post talks about embedded PCs. BTW, it's from 2011, when embedded processors didn't have PCIe, which is slightly different today. It’s DMA controlled by the FPGA, of course.

I/O-capable DMA controllers/engines is something found on some embedded processors and DSPs, not on x86-like platforms (not that I’ve seen, anyhow). And this post talks about embedded PCs.

BTW, it’s from 2011, when embedded processors didn’t have PCIe, which is slightly different today.

]]> By: Tony https://billauer.se/blog/2011/07/pc-104-embedded-pc-fpga-usb-ethernet/comment-page-1/#comment-1267 Tony Fri, 16 Jun 2017 22:15:51 +0000 https://billauer.se/blog/?p=1437#comment-1267 I have a similar question. You state it IS with DMA, but which DMA is this? Is this host CPU programming a DMA engine to receive all this data from PCIe, or does and FPGA engine somehow have access to host RAM through the PCIe interface? This isn't clear to me yet. I have a similar question. You state it IS with DMA, but which DMA is this? Is this host CPU programming a DMA engine to receive all this data from PCIe, or does and FPGA engine somehow have access to host RAM through the PCIe interface? This isn’t clear to me yet.

]]> By: eli https://billauer.se/blog/2011/07/pc-104-embedded-pc-fpga-usb-ethernet/comment-page-1/#comment-760 eli Fri, 06 Apr 2012 14:32:26 +0000 https://billauer.se/blog/?p=1437#comment-760 A 1x lane with 2.5 Gb/s has an effective bandwidth of 2.0 Gb/s, so 250 MB/s is the theoretic upper bound for all data transfer, including TLP and data layer overhead. When taking these into account, 200 MB/s is within 90% efficiency. So yes, this must be with DMA. Without DMA it's down to your processor and PCIe infrastructure. In particular if it has the ability to join subsequent writes in TLP packets. Anyhow, DMA is the way. A 1x lane with 2.5 Gb/s has an effective bandwidth of 2.0 Gb/s, so 250 MB/s is the theoretic upper bound for all data transfer, including TLP and data layer overhead. When taking these into account, 200 MB/s is within 90% efficiency. So yes, this must be with DMA.

Without DMA it’s down to your processor and PCIe infrastructure. In particular if it has the ability to join subsequent writes in TLP packets. Anyhow, DMA is the way.

]]> By: Roger https://billauer.se/blog/2011/07/pc-104-embedded-pc-fpga-usb-ethernet/comment-page-1/#comment-759 Roger Fri, 06 Apr 2012 13:38:25 +0000 https://billauer.se/blog/?p=1437#comment-759 Is the 200 MBytes/s using DMA rate stated, using DMA? If so, what would a rate be that does not use DMA? Is the 200 MBytes/s using DMA rate stated, using DMA? If so, what would a rate be that does not use DMA?

]]> By: Dan https://billauer.se/blog/2011/07/pc-104-embedded-pc-fpga-usb-ethernet/comment-page-1/#comment-569 Dan Fri, 29 Jul 2011 10:51:26 +0000 https://billauer.se/blog/?p=1437#comment-569 A lot o f good information. I have prited because I have to reserch the embedded PC more. A lot o f good information. I have prited because I have to reserch the embedded PC more.

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