I was going to implement the LVDS line indeed, using the DDR output. Glad that you mentioned it too :)

Thanks again!

Otherwise, I would go for a single data-clock pair with a couple of LVDS pairs. 400 Mbps isn’t such a high rate, and can be implemented with plain logic running at 200 MHz and DDR I/O. To make life easier, you may want to work with the FPGA’s silicon SERDES if there’s one available, or even one of those external chips. There are plenty of those out there, primarily for the use with Camera Link and LCD monitors.

Really nice post, thank you. What kind of link would you recommend between two FPGAs on separate boards? I need minimum latency and 400Mbps data rate, while the packets are about 1kB to 4kB, constant size, and no buffer can be kept in either FPGA. Is there any standard solution?

Thanks!

i have design a board using fpga spartan3e (hardware side algorithms) and coldfire module as a controller (mod5282 module , with RT ucos as OS) for data acq.
but in my design i have interface fpga with controller through bus (data bus,address bus and control line) and design tri-state logic in fpga for that for data interchage.

But now for new design with high data transfer rate and complex hardware design with large size , i want to use spartan6 with avnet nano itx/sparan6 kit , with embedded OS, Linux, which has PCIe interface for data interchange.

I am new for this board. i don’t have idea to interface my hardware design in FPGA and with PCIe and how to read data from PCIe bus in processor board. if u guide me then it is very use full for me. i want some example module for controller to interface with PCIe.