Comments on: Verilog and bit shifting (‘’): Don’t push your luck https://billauer.se/blog/2011/12/verilog-shift-calculated-xst/ Anything I found worthy to write down. Thu, 26 Mar 2026 13:15:15 +0000 hourly 1 http://wordpress.org/?v=3.1.2 By: eli https://billauer.se/blog/2011/12/verilog-shift-calculated-xst/comment-page-1/#comment-696 eli Fri, 13 Jan 2012 09:08:05 +0000 https://billauer.se/blog/?p=2472#comment-696 Actually, I don't think this should have confused the synthesizer. The format_shift was either a wire or register with two bits. That's all. Actually, I don’t think this should have confused the synthesizer.

The format_shift was either a wire or register with two bits. That’s all.

]]> By: Andy https://billauer.se/blog/2011/12/verilog-shift-calculated-xst/comment-page-1/#comment-695 Andy Fri, 13 Jan 2012 00:40:32 +0000 https://billauer.se/blog/?p=2472#comment-695 Good point. It is always best not to confuse XST. What is the declaration of the reduce register in your example? Good point. It is always best not to confuse XST. What is the declaration of the reduce register in your example?

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