Comments on: Vivado: An ISE guy’s exploration notes https://billauer.se/blog/2014/05/vivado-random-howto-notes/ Anything I found worthy to write down. Thu, 26 Mar 2026 13:15:15 +0000 hourly 1 http://wordpress.org/?v=3.1.2 By: Evgeni Stavinov https://billauer.se/blog/2014/05/vivado-random-howto-notes/comment-page-1/#comment-1229 Evgeni Stavinov Thu, 02 Feb 2017 19:51:31 +0000 https://billauer.se/blog/?p=4219#comment-1229 Another useful thing is to compress bitstream property. set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] By default the bitstream is not compressed. For small designs and large chips the gain is 50-60MByte. That translates into much faster configuration. Another useful thing is to compress bitstream property.

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]

By default the bitstream is not compressed. For small designs and large chips the gain is 50-60MByte. That translates into much faster configuration.

]]> By: PaulB https://billauer.se/blog/2014/05/vivado-random-howto-notes/comment-page-1/#comment-1173 PaulB Fri, 18 Mar 2016 15:57:39 +0000 https://billauer.se/blog/?p=4219#comment-1173 Thanks for this post. The old ISE would win not any interface awards from me, but the Vivado GUI is like they read multiple top 20 lists of "Common GUI Errors & User Hostility" and then implemented every thing on them. At the end of the work day I'd rather they spent the dev dollars on the back end, but, my gods, hire *one* GUI consultant at least. Faster synthesis stymied by slower interfacing isn't an overall gain. Thanks for this post.

The old ISE would win not any interface awards from me, but the Vivado GUI is like they read multiple top 20 lists of “Common GUI Errors & User Hostility” and then implemented every thing on them.

At the end of the work day I’d rather they spent the dev dollars on the back end, but, my gods, hire *one* GUI consultant at least. Faster synthesis stymied by slower interfacing isn’t an overall gain.

]]> By: Jack Lovell https://billauer.se/blog/2014/05/vivado-random-howto-notes/comment-page-1/#comment-1035 Jack Lovell Thu, 18 Dec 2014 12:55:46 +0000 https://billauer.se/blog/?p=4219#comment-1035 Regarding the PS pins bug, it seems that the Vivado processing_system7 IP makes these 4 pins inout, rather than the in (for PS_*) and out (DDR_WEB) pins that XPS creates. I've found that simply changing them to inout and connecting them as top level ports results in no errors or warnings. This does however mean that any HDL needs to be modified depending on whether the design is in ISE or Vivado. I did also have a similar issue with DDR_Clk in a Xillybus design, but it turned out to be a typo in the system.v file: DDR_ck_p was mapped to processing_system7_0_DDR_Clk_p when processing_system7_0_DDR_Clk was declared as a port. Regarding the PS pins bug, it seems that the Vivado processing_system7 IP makes these 4 pins inout, rather than the in (for PS_*) and out (DDR_WEB) pins that XPS creates. I’ve found that simply changing them to inout and connecting them as top level ports results in no errors or warnings. This does however mean that any HDL needs to be modified depending on whether the design is in ISE or Vivado.

I did also have a similar issue with DDR_Clk in a Xillybus design, but it turned out to be a typo in the system.v file: DDR_ck_p was mapped to processing_system7_0_DDR_Clk_p when processing_system7_0_DDR_Clk was declared as a port.

]]> By: xhay https://billauer.se/blog/2014/05/vivado-random-howto-notes/comment-page-1/#comment-1007 xhay Sun, 12 Oct 2014 17:53:30 +0000 https://billauer.se/blog/?p=4219#comment-1007 Hi Iam using Vivado 2014.2 and using virtex 7, Iam trying to flush a design through pnr implementation and wnated to know if it could be done without any constraints, just the netlist and go ahead with implementation. Is it possible at all in Vivado, as Iam trying to identify specific design parameters by doing this exercise and do not have a lot time to make a xdc for the design given the fact that the design is pretty complex and huge...Could you help with this regards. Thanks & Regards xhay Hi
Iam using Vivado 2014.2 and using virtex 7, Iam trying to flush a design through pnr implementation and wnated to know if it could be done without any constraints, just the netlist and go ahead with implementation. Is it possible at all in Vivado, as Iam trying to identify specific design parameters by doing this exercise and do not have a lot time to make a xdc for the design given the fact that the design is pretty complex and huge…Could you help with this regards.

Thanks & Regards
xhay

]]> By: Anonymous https://billauer.se/blog/2014/05/vivado-random-howto-notes/comment-page-1/#comment-953 Anonymous Tue, 10 Jun 2014 07:25:05 +0000 https://billauer.se/blog/?p=4219#comment-953 Thank you for your answer. Actually in ISE 14.7, everything works fine. I can see the output. It just happens in Vivado. However another mysterious thing is, after ISE works and if I dont powercycle the board and download the VIVADO bitstream, it works as well. No idea of whats going on.. Thank you for your answer. Actually in ISE 14.7, everything works fine. I can see the output. It just happens in Vivado. However another mysterious thing is, after ISE works and if I dont powercycle the board and download the VIVADO bitstream, it works as well. No idea of whats going on..

]]> By: eli https://billauer.se/blog/2014/05/vivado-random-howto-notes/comment-page-1/#comment-950 eli Fri, 06 Jun 2014 16:35:30 +0000 https://billauer.se/blog/?p=4219#comment-950 Hi, If you're referring to a situation where the board sometimes boots up when you power it on, and sometimes it doesn't, it's indeed not a pleasant situation. It can be basically everything, but I would start with taking an oscilloscope and verify that supply voltages, clocks and resets are waking up in the right timing sequence. Hi,

If you’re referring to a situation where the board sometimes boots up when you power it on, and sometimes it doesn’t, it’s indeed not a pleasant situation.

It can be basically everything, but I would start with taking an oscilloscope and verify that supply voltages, clocks and resets are waking up in the right timing sequence.

]]> By: Berk https://billauer.se/blog/2014/05/vivado-random-howto-notes/comment-page-1/#comment-949 Berk Fri, 06 Jun 2014 15:15:04 +0000 https://billauer.se/blog/?p=4219#comment-949 Hello, I am using Vivado 2014.1 WebPack on a custom ZYNQ board. I have run into a strange issue, I run a Helloworld, see the output. Then I power-cycle the board. I can not get to see the Hello World again. So the project I created seems to be one shot. Have you faced something like this before? Best Regards, Berk Hello,

I am using Vivado 2014.1 WebPack on a custom ZYNQ board. I have run into a strange issue, I run a Helloworld, see the output. Then I power-cycle the board. I can not get to see the Hello World again. So the project I created seems to be one shot. Have you faced something like this before?

Best Regards,
Berk

]]>