Comments on: Using Verilog “initial” blocks for FPGA synthesis: Legit? Portable? https://billauer.se/blog/2018/02/verilog-initial-xst-quartus-vivado/ Anything I found worthy to write down. Thu, 26 Mar 2026 13:15:15 +0000 hourly 1 http://wordpress.org/?v=3.1.2 By: Martoni https://billauer.se/blog/2018/02/verilog-initial-xst-quartus-vivado/comment-page-1/#comment-1382 Martoni Tue, 27 Nov 2018 08:40:04 +0000 https://billauer.se/blog/?p=5391#comment-1382 I tested it on Machxo3 with Lattice Synthesis engine, and it doesn't work: /* generate reset */ reg [3:0] resetcount; wire reset = !resetcount[3]; wire resetn = resetcount[3]; initial resetcount = 4'b0; always@(posedge clock) if(reset) resetcount = resetcount + 1; No reset pulse are emitted :( I tested it on Machxo3 with Lattice Synthesis engine, and it doesn’t work:

/* generate reset */
reg [3:0] resetcount;
wire reset = !resetcount[3];
wire resetn = resetcount[3];

initial resetcount = 4′b0;

always@(posedge clock)
if(reset)
resetcount = resetcount + 1;

No reset pulse are emitted :(

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