<?xml version="1.0" encoding="UTF-8"?><rss version="2.0"
	xmlns:content="http://purl.org/rss/1.0/modules/content/"
	xmlns:dc="http://purl.org/dc/elements/1.1/"
	xmlns:atom="http://www.w3.org/2005/Atom"
	xmlns:sy="http://purl.org/rss/1.0/modules/syndication/"
		>
<channel>
	<title>Comments on: Combining PCIe and Gigabit Transceiver on Cyclone V</title>
	<atom:link href="http://billauer.se/blog/2018/04/pcie-mgtxcvr-qsys/feed/" rel="self" type="application/rss+xml" />
	<link>https://billauer.se/blog/2018/04/pcie-mgtxcvr-qsys/</link>
	<description>Anything I found worthy to write down.</description>
	<lastBuildDate>Thu, 26 Mar 2026 13:15:15 +0000</lastBuildDate>
	<sy:updatePeriod>hourly</sy:updatePeriod>
	<sy:updateFrequency>1</sy:updateFrequency>
	<generator>http://wordpress.org/?v=3.1.2</generator>
	<item>
		<title>By: Arti</title>
		<link>https://billauer.se/blog/2018/04/pcie-mgtxcvr-qsys/comment-page-1/#comment-1357</link>
		<dc:creator>Arti</dc:creator>
		<pubDate>Fri, 31 Aug 2018 18:28:14 +0000</pubDate>
		<guid isPermaLink="false">https://billauer.se/blog/?p=5413#comment-1357</guid>
		<description>Hello, I was able to get it to compile with those transceivers. You probably already know about this and it probably didn&#039;t fix your issue, but I want to tell you the solution that worked for me. 

In qsys for the TSE IP, it allows me to choose a TX PLL Clock network. The default x1 or selecting xN which allows the TX PLL to be placed inside or out of the six-pack. 

For me it worked because TSE IP is what I need and it happens to have that configuration available.</description>
		<content:encoded><![CDATA[<p>Hello, I was able to get it to compile with those transceivers. You probably already know about this and it probably didn&#8217;t fix your issue, but I want to tell you the solution that worked for me. </p>
<p>In qsys for the TSE IP, it allows me to choose a TX PLL Clock network. The default x1 or selecting xN which allows the TX PLL to be placed inside or out of the six-pack. </p>
<p>For me it worked because TSE IP is what I need and it happens to have that configuration available.</p>
]]></content:encoded>
	</item>
	<item>
		<title>By: eli</title>
		<link>https://billauer.se/blog/2018/04/pcie-mgtxcvr-qsys/comment-page-1/#comment-1342</link>
		<dc:creator>eli</dc:creator>
		<pubDate>Sat, 04 Aug 2018 06:50:08 +0000</pubDate>
		<guid isPermaLink="false">https://billauer.se/blog/?p=5413#comment-1342</guid>
		<description>Hello,

As mentioned above, I didn&#039;t pursue this direction, so there&#039;s no additional info to offer.</description>
		<content:encoded><![CDATA[<p>Hello,</p>
<p>As mentioned above, I didn&#8217;t pursue this direction, so there&#8217;s no additional info to offer.</p>
]]></content:encoded>
	</item>
	<item>
		<title>By: Arti</title>
		<link>https://billauer.se/blog/2018/04/pcie-mgtxcvr-qsys/comment-page-1/#comment-1341</link>
		<dc:creator>Arti</dc:creator>
		<pubDate>Sat, 04 Aug 2018 00:30:21 +0000</pubDate>
		<guid isPermaLink="false">https://billauer.se/blog/?p=5413#comment-1341</guid>
		<description>Hey, 

I&#039;m a big fan of your blogs. I actually am trying to get PCIe x2 and Transceivers for SGMII to work on Cyclone V. It seems like you were not successful, but is it possible if you have more details, information that you could email me a bit more. 

For me, I have to get this to work somehow, and would like all the help I can get.</description>
		<content:encoded><![CDATA[<p>Hey, </p>
<p>I&#8217;m a big fan of your blogs. I actually am trying to get PCIe x2 and Transceivers for SGMII to work on Cyclone V. It seems like you were not successful, but is it possible if you have more details, information that you could email me a bit more. </p>
<p>For me, I have to get this to work somehow, and would like all the help I can get.</p>
]]></content:encoded>
	</item>
</channel>
</rss>
