Comments on: Quartus / sdc: Constraining I/O ports clocked by an internal clock https://billauer.se/blog/2018/08/quartus-sdc-constraining-pins-derived-clock/ Anything I found worthy to write down. Thu, 26 Mar 2026 13:15:15 +0000 hourly 1 http://wordpress.org/?v=3.1.2 By: eli https://billauer.se/blog/2018/08/quartus-sdc-constraining-pins-derived-clock/comment-page-1/#comment-1387 eli Thu, 13 Dec 2018 07:40:58 +0000 https://billauer.se/blog/?p=5474#comment-1387 Actually, the delays by the PLL and the clock network can be, and usually are, corrected by the PLL itself, as its reference can be set to be the global clock network. Actually, the delays by the PLL and the clock network can be, and usually are, corrected by the PLL itself, as its reference can be set to be the global clock network.

]]> By: Kelly lindseth https://billauer.se/blog/2018/08/quartus-sdc-constraining-pins-derived-clock/comment-page-1/#comment-1386 Kelly lindseth Thu, 13 Dec 2018 06:41:03 +0000 https://billauer.se/blog/?p=5474#comment-1386 Is this necessary if your pll is multiplying by a power of two, such as 4 let’s say? It would seem so, because the pll is internal and has a bunch of delays that get added into the calculation incorrectly apparently. Is this necessary if your pll is multiplying by a power of two, such as 4 let’s say?

It would seem so, because the pll is internal and has a bunch of delays that get added into the calculation incorrectly apparently.

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