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	<title>Comments on: Writing about timing and timing constraints: Kind-of behind the scenes</title>
	<atom:link href="http://billauer.se/blog/2023/03/timing-constraints-writing/feed/" rel="self" type="application/rss+xml" />
	<link>https://billauer.se/blog/2023/03/timing-constraints-writing/</link>
	<description>Anything I found worthy to write down.</description>
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		<title>By: Andrew</title>
		<link>https://billauer.se/blog/2023/03/timing-constraints-writing/comment-page-1/#comment-1819</link>
		<dc:creator>Andrew</dc:creator>
		<pubDate>Mon, 27 Jan 2025 11:04:22 +0000</pubDate>
		<guid isPermaLink="false">https://billauer.se/blog/?p=6803#comment-1819</guid>
		<description>Been reading you io timing , clock pages . 
Fantastic, it&#039;s what I&#039;ve been looking for for my students , 
But 
Lack if pictures , and lack of vhdl,</description>
		<content:encoded><![CDATA[<p>Been reading you io timing , clock pages .<br />
Fantastic, it&#8217;s what I&#8217;ve been looking for for my students ,<br />
But<br />
Lack if pictures , and lack of vhdl,</p>
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		<title>By: KE5FX</title>
		<link>https://billauer.se/blog/2023/03/timing-constraints-writing/comment-page-1/#comment-1800</link>
		<dc:creator>KE5FX</dc:creator>
		<pubDate>Thu, 19 Sep 2024 03:24:58 +0000</pubDate>
		<guid isPermaLink="false">https://billauer.se/blog/?p=6803#comment-1800</guid>
		<description>Having read this entry and browsed a few others, I think you&#039;ve made a good attempt at doing for FPGAs what Cliff Cummings did for ASICs, which is something that was (and is) badly needed.  As you noted, lots of received wisdom in the ASIC world simply doesn&#039;t apply to FPGAs, but the way Cliff imparted it, newcomers are left with no idea what&#039;s still important.

As far as &quot;why,&quot; that&#039;s simple enough: you wrote the series of posts to confirm your own knowledge by codifying it, and to encourage the &quot;Someone Is Wrong On the Internet&quot; crowd to offer free notes and corrections.  You wrote it to teach yourself, in other words.  I&#039;ll take plain cheese on mine. :)</description>
		<content:encoded><![CDATA[<p>Having read this entry and browsed a few others, I think you&#8217;ve made a good attempt at doing for FPGAs what Cliff Cummings did for ASICs, which is something that was (and is) badly needed.  As you noted, lots of received wisdom in the ASIC world simply doesn&#8217;t apply to FPGAs, but the way Cliff imparted it, newcomers are left with no idea what&#8217;s still important.</p>
<p>As far as &#8220;why,&#8221; that&#8217;s simple enough: you wrote the series of posts to confirm your own knowledge by codifying it, and to encourage the &#8220;Someone Is Wrong On the Internet&#8221; crowd to offer free notes and corrections.  You wrote it to teach yourself, in other words.  I&#8217;ll take plain cheese on mine. :)</p>
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		<title>By: eli</title>
		<link>https://billauer.se/blog/2023/03/timing-constraints-writing/comment-page-1/#comment-1664</link>
		<dc:creator>eli</dc:creator>
		<pubDate>Fri, 17 Mar 2023 03:35:07 +0000</pubDate>
		<guid isPermaLink="false">https://billauer.se/blog/?p=6803#comment-1664</guid>
		<description>Interestingly enough, I didn&#039;t even relate to that concept in the said series of pages. The reason is simple: I never paid attention to TNS, exactly because of the reasons you mentioned. :)</description>
		<content:encoded><![CDATA[<p>Interestingly enough, I didn&#8217;t even relate to that concept in the said series of pages. The reason is simple: I never paid attention to TNS, exactly because of the reasons you mentioned. :)</p>
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		<title>By: Evgeni Stavinov</title>
		<link>https://billauer.se/blog/2023/03/timing-constraints-writing/comment-page-1/#comment-1663</link>
		<dc:creator>Evgeni Stavinov</dc:creator>
		<pubDate>Fri, 17 Mar 2023 03:29:27 +0000</pubDate>
		<guid isPermaLink="false">https://billauer.se/blog/?p=6803#comment-1663</guid>
		<description>I did read the post from top to bottom.
One thing I absolutely dislike during timing closure is using aggregated measures such as TNS (Total Negative Slack). If you plot a histogram of a typical TNS - slack bin on the x-axis, and count of paths on the y-axis - it&#039;d look like a long-tail distribution. All those paths with smaller slacks are totally unrelated to the ones with WNS (Worst Negative Slack). WNS paths are actually those that
prevent Place &amp; Route to close timing, and the rest of the paths participating in TNS are just a distraction, making it more difficult to correctly interpret the results.</description>
		<content:encoded><![CDATA[<p>I did read the post from top to bottom.<br />
One thing I absolutely dislike during timing closure is using aggregated measures such as TNS (Total Negative Slack). If you plot a histogram of a typical TNS &#8211; slack bin on the x-axis, and count of paths on the y-axis &#8211; it&#8217;d look like a long-tail distribution. All those paths with smaller slacks are totally unrelated to the ones with WNS (Worst Negative Slack). WNS paths are actually those that<br />
prevent Place &amp; Route to close timing, and the rest of the paths participating in TNS are just a distraction, making it more difficult to correctly interpret the results.</p>
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