These are my notes to self for the next time I’ll have a PCB design to make. This is definitely not my expertise.

My original intention was to start this post with some kind of apologize, saying I only needed to make a simple board, so KiCad was good enough for this purpose. However it seems like KiCad is about to become the preferred tool many PCB designers quite soon, if it’s not there already. It’s surely handy and relatively easy to learn (at least for me, an experienced Electrical Engineer with no previous hands-on in board design). Does it match up with the expensive tools out there for a heavy and complicated design? I don’t know.

Everything in KiCad is text based in a simple manner. Important for version control, and using it to monitor my changes. Also very handy for fiddling with the files to get the things right on spot. In particular useful when creating footprints.

All said here relates to KiCad 5.1.4 under Linux Mint 19.

Getting started

• The KiCad version that went along with Mint 19 was heavily outdated. Compare what packages are available directly from KiCad.
• When upgrading from 4.x to 5.x, be sure to uninstall the previous version and purge it (apt purge) before installing the new one. Also, delete .config/kicad/ as it contains the paths to libraries for symbols and footprints.
• The ‘Footprint library path “…” does not exist’ error may be a result of not cleaning up an old installation as mentioned in the previous item.
• The official documentation, in particular the Getting Started with KiCad guide, is definitely the right place to start and refresh memory.

EESchema

• Before starting to work: Verify that the page size is correct and that the grid is 50 mils or so, no lower: View > Grid Settings… to ensure this.
• Basic components: In the “Device” library.
• Aiming the cursor on something accurately and right-clicking is usually the start for modifying virtually anything.
• Better still: Note the hotkey and use it while hovering over the relevant place.
• “Drag” keeps connections. “Move” doesn’t. Use “Drag”.
• If wires don’t snap to the ports, and components are placed regardless to the grid, it’s most likely that the grid is too dense.
• Useful hotkeys: Hover-Delete (well, delete), Hover-G (drag, think Blender) and Hover-C (duplicate).
• “Value”: Each component has a value assigned to it. The value appears on the assembly layer (F.Fab or B.Fab) of the PCB. In other words, the person doing the assembly of the board will see this value in the component’s position, and select what to put there accordingly. For resistors and capacitors, it’s obviously the value of the component. For other components, a useful hint on the nature of the device should be there.
• “Reference”: The symbol’s unique identifier in the schematics and netlist. U1, J15, C225 etc. By default, they’re C?, R? etc. until Annotate Schematic… is done.
• Net names: Designated with “Place Net Label” or by pressing “l”. Makes things easier during layout, and differential pairs must be with “+” and “-” suffixes (or _p/_n), or PCBNew won’t play ball later on.
• Footprints are assigned on each component’s Properties (and are not associated with symbols, unlike other tools), or more conveniently, with Tools > Assign Footprints. The association affects the schematic (.sch) file, appearing as a string property consisting of the library name and the footprint’s name, separated by a colon. Don’t associate to library footprints, but copies of them, defined explicitly on a local library. Or upgrading KiCad may change the design. See below on footprints.
• Plain holes are “virtual components”. Add a MountingHole symbol for each, and assign a matching footprint (hole only).

Symbol Editor

• Read the Symbol Guidelines in KiCad Library Convention document (KLC), after the daunting naming convention part (start at S3, maybe). It’s how to get it right.
• Check the grid. 50-100 mils, or the wires won’t snap to ports when the symbol is used (official guideline is 100 mils).
• Symbol Editor: When drawing a rectangle, click at the corner points, don’t hold the mouse button.
• It doesn’t hurt setting the “Description” property for each symbol — it appears on the library’s list as well as the output netlist.
• If a pin has multiple pads assigned to it, KiCad expects them to have track wires on the PCB connecting between them all.

Understanding footprints

Footprints are a set of graphical shapes in different layers that serve several purposes, all of which much be addressed when setting up a custom footprint:

• Putting the pads in place: Front copper layer (F. Cu, and also B. Cu with thru pads) and solder mask (F. Mask). Actually, the solder mask layer is the hole in the solder mask. Even though the shape of these is the same, the solder mask is widened slightly when Gerber files are created.
• Solder paste: When used, where the stencil holes should allow solder paste to be applied (F. Paste). As with solder mask, the shape is usually the same as the pads, but the datasheet may require a different pattern.
• Holes (drilling): These are a side effect of thru-hole pads, and appear in the footprint layers as is there was copper there.
• Silk Screen: Descriptive information on the board, in particular the component reference (F. SilkS)
• Assembly: Mark the place where the device actually is (F. Fab). The placement’s origin should also be the footprint’s (x,y) origin for automatic placement. The reference designator (“%R”) is written inside the component’s boundaries, and its “value” (what it is) typically underneath.
• Clearance: Ensure that nothing else is placed in the space that the device requires. This no-place space is called “courtyard” (F. CrtYd). The idea is simple: If, during layout (with PCBnew), the courtyards of two components overlap, it’s a DRC error at the very least, and possible also a refusal to generate Gerber files. So the courtyard should be the area that the component must occupy exclusively.

Footprints

There’s another post of mine, which discusses pads and footprint manipulation.

• Rule number one: Copy or imitate an existing library footprint rather than reinventing the wheel. Preferably imitate one that is likely to be heavily used.
• Read the Footprint Guidelines in KiCad Library Convention document (KLC). Skip the naming convention, and start at F4 (or so). This might be the best source on the planet for setting up a footprint. Odds are that these rules are tuned based upon real-life experience of a lot of people.
• Never ever use a footprint directly from the libraries to a component in the design. That makes the outcome dependent on the KiCad version running.
• Rather, create a project-dedicated footprint library (a directory with a .pretty suffix) in the Footprint editor, and put it in the Project’s library table. Then open the desired footprint in Footprint editor, and save it into the project’s library.
• Note that the 3D model still points at a KiCad library even after this, but that’s less important.
• Monitor the changes with git. It’s quite straightforward and allows a safe double-check.
• Don’t hesitate editing the footprint file manually, in particular for nailing exact positions. Exit the Footprint Editor and re-enter it, and then load the footprint. Using “Revert” for updating changes won’t work.
• To verify that a footprint is OK:
  • At the very least view each layer separately, and make sure it contains what it should. Drill holes are covered by absence of material in the copper layers.
  • Verify that SMT pads cover F.Cu, F.Mask and F.Paste (check each separately!). For thru pins, also on the back.
  • Read through the text file (with _mod suffix) and look for unexpected stuff (one pad having different dimensions for no reason etc.)
• Pads may not have a pad number. This is useful for e.g. stencil pattern not matching the shape of the pad.
• If multiple pads have the same pin number assigned to them, track wires must be connected between them during the layout.
• Pads and other elements may very well not be on the footprint nor layout grid. I find myself calculating their X/Y position rather than placing them, so any position goes.
• For adding anything other than a pad, the drawing or text falls on the layer marked with a small arrow in the list of layers.
• Text substitutions: %R is replaced with the reference, %V with the value.
• Even though the name of the footprint is shown as the “value” in the Footprint Editor, it will be the component’s “value” field in Pcbnew. So it’s useful information during assembly of the board.
• Right-click on a pad, select “Array” to produce several identical pads with equal spacing. In extreme cases, write a simple script to manipulate the footprint file directly (exotic positions or pad naming).
• Use the measurement tool for assurance. It snaps to the grid.
• Any line thickness is implemented as a filled circle drawing along the line. This makes rounded corners.
• Pads can have arbitrary shapes. See this post.

PCBnew (layout)

• When starting a new project, remove the *.kicad_pcb file as well as .config/kicad directory, and start from scratch. KiCad’s defaults are usually good, so if a detail is overlooked, better have the default than some previous setting.
• File > Board Setup… and set the board’s thickness, trace parameters etc. It’s also a good idea to define the net classes (in particular high frequency nets).
• PCBnew depends on the current netlist as well as the footprint libraries. They are updated only on explicit request, so each time the schematics or footprints in use are updated, the changes must be synchronized by user request. As for the schematics, there an “Update PCB from Schematics” button. Or export the netlist from EESchema in default format and load it into PCBnew. It’s fine to do this iteratively (and even finer when covered by version control to cover up for mishaps).
• Grid: Pads may be off the grid, and there’s no problem selecting them as a start and end point for a route. The track itself will generally go on the grid, except for leaving it in order to reach a pad in a sane manner (usually with a 45-degree detour, not on a grid point). The grid pitch should hence be the approximately most used track width + the track clearance if a dense design is desired. Possibly make it in line with crucial footprints’ pitch, to keep straight traces, aligned with the grid.
• Ratsnest: Straight lines showing connections between pads. View all at once with View > Show Ratsnest (default on) or turn off, and view individual lines with “Display local ratsnets” icon on the toolbar to the right.
• The origin’s position has no significance, expect that it places the grid. However the absolute position values appear in the Gerber files, but this can be fixed by adding an auxiliary axis (more on this below).
• There are no 90 degree turns on tracks (except for power lines), only 45 degrees (and possibly smaller angles when aligning to the grid). Feels a bit awkward in the beginning but sharp turns are evil.
• There is no dragging of components (footprints), only moving them, which results in disconnection of all tracks going to it.
• While drawing tracks, press “v” for a via, press “/” to change the posture (the position of the 45 degree detour, if present).
• Always start and end a track by clicking at the center of a pad (the “anchor”), in particular if it’s off-grid.
• Ground / power planes: Create a fill zone, which is a polygon which is designated to a net. After setting up the zone, select it, right-click and pick Zones > Fill. This may not work unless there is already a track with the desired net going through the area. The track may remain, as it’s harmless. It’s probably the via, which connects the area to the net that does the trick. Once set up, a via is enough to connect to the plane.
• Repeat the zone fill after each change that may affect it.
• If the zone fill gets too close to a specific footprint’s pads, open the “Local Clearance and Settings” tab on the footprint’s Properties, and set a larger (actually, non-zero) clearance.
• In the end, tracks are a sequence of segments with a start and end position, width, layer and net designation in the *.kicad_pcb file (with “segment” keyword), vias are elements with the “via” keyword etc. Everything is absolutely positioned. Therefore moving a component (actually, its footprint) disconnects everything. All in all, PCBnew is just a smart drawing program for geometric shapes.
• Differential pairs: Route > Differential Pair. Then Route > Tune Differential Pair Skew / Phase, in order to check the skew and possibly tune it (or possibly move a component if that helps).
• Setting the parameters for track length and skew tuning: After selecting the track to tune, instead of moving the mouse to get those humps, right click and select Length Tuning Settings (or CTRL-L). The amplitude and length of these humps can be set, as well as the target length (instead of the default 100 mm).
• There’s a measurement tool (“Add dimension”) which is handy to verify certain distances, in particular the dimension of the board. The tool shown an indication when it’s on a line end, so one can be sure the accurate measurement is made. Best done on a separate drawing layer.
• Optionally, add an auxiliary axis origin to the layout, placing the (0,0) point of Gerber and drill files. This changes the aux_axis_origin parameter of the PCB design from (0 0) to whatever it was set to, and the coordinates in the Gerber files will have an offset relative to the layout files. Useful if the entire layout was drawn with some meaningless origin position. Then check “Use auxiliary axis as origin” when generating Gerbers and drill files.

3D viewer

I didn’t understand the point of a 3D view at first, but it’s surprisingly helpful, in particular during PCB layout — even though it’s also handy with the Footprint Editor. There’s something reassuring seeing the silk screen as white text on a green solder mask, and the drill holes as see-throughs. Click the mouse’s middle button to move the scenery.

Launch with View > 3D viewer (or Alt-3).

Generate Gerber files

You have reviewed the DRCs in EESchema and PCBnew, right…?

So to the final check before taping out. Export the files in PCBnew with File > Plot… and as follows (for a two-layer design):

(click image to enlarge)

and then generate a drill file (click “Generate Drill File”, of course).

(click image to enlarge)

All the settings above are KiCad’s defaults, by the way. Changes in these settings are stored in the *.kicad_pcb file for the next time these windows are opened (and not KiCad-globally).

Note that two drill files are (usually) generated: One for plated holes (vias and pads) and one for non-plated holes (typically mechanical holes for mounting).

A component positioning file can be generated with Fabrication Outputs > Footprint Position (.pos) file, however this file uses the internal footprints and their names. In particular, if the footprint’s origin isn’t where the automatic placement machine thinks it should be, the device may end up in the wrong place.

Viewing Gerber files

KiCad’s Gerber is fine, but it’s recommended to install gerbv as well (plain “apt install gerbv” on Mint 19). It’s part of gEDA, and it allows changing the order of the layers, but even more important, to export the current view to pdf. KiCad’s viewer prints one layer per page, and it’s hardly helpful. Use the export feature, don’t print — the latter generates a microscopic printout.

The main motivation for printing layers is to print the fabrication layer (preferably without values, KiCad has that option) on top of the edge cut and possibly a copper layer. For manual assembly, this gives a good indication of what goes where. To run it, just go

$ gerbv &

For KiCad’s viewer, load both the Gerber files and the drill files into Gerbview, and take a close look. The layers are displayed in the order they were loaded, so load the drill files first. As they are usually loaded with multiple selection of files, that’s probably alphabetical order, putting the bottom layer above the front.

Right-click on the layer list and select “Sort Layers if X2 mode” (should be “in X2 mode”, I guess) for layers ordered in physical order.

The active layer is always visible (drawn last).

Most important: Verify that the drill holes, plated and not, are in the correct places.

The DCodes are the aperture with which each line is drawn. An aperture is like a paintbrush, which is defined in each Gerber file for its own drawings. It’s usually a filled circle or rectangle with specific dimensions. The benefit of having these on the screen is to identify tracks with the same width and pads with the same dimensions, if they have the same DCode and are on the same layer. The same DCode on different layers (and hence Gerber files) has no meaning. For example, D10 and D11 are typically the DCodes of the first apertures defined in Gerber file, and are practically on every layer.

Create assembly sheet

If the design is going to be hand-assembled, better have a simple drawing that tells what goes where. To do this, plot the Gerber files as before, but uncheck “Plot footprint values” (but keep “Plot footprint references” checked, of course). Check F.Fab layer for plotting.

Recall that PCBnew remembers this in the *.kicad_pcb file, so be sure to revert it (with git) afterwards.

Next, open the files with gerbv (not KiCad’s Gerber viewer). Display the F_Fab layer, which should have the component references printed small inside boxes, along with the edge cuts and a copper layer. Change the colors for convenience.

Then File > Export > SVG… and generate a file. Import that file into a Libreoffice Writer document, and export that document as a pdf. Why not directly as pdf? Because the output pdf is broken, and even when I managed to open it, turning it into a pdf with a decent size turned out impossible.

A similar SVG export can be done from PCBNew: Pick File > Export > SVG… and select “Board area only” under “SVG Page Size”. For Pagination, pick “All layers in a single file”. However I haven’t figured out how to get rid of the values, and they clutter everything.

Manufacture

• Holes: Manufacturers typically make the hole slightly larger than required, as commented on this thread. The difference is typically no more than 0.1mm, so it’s not a big deal.
• PCB material: FR-4 is de-facto industry standard for rigid boards. 1 oz copper thickness is by far the most common. Pick thicker only for high currents. Board thickness: 0.6/0.8/1.0/1.2/1.6/2.0 mm. Tolerance is typically ±0.1 mm.
• Drill size: 0.2 – 6.3mm (but don’t go lower than 0.4 mm = 16 mils for basic PCB)
• Trace width: 6 mil seems to be a common minimal trace width, but Protel used to set 10 mil as the default (the latter seems to carry up to 1A, but check with a calculator). Unless there are current to carry, stick to these figures in general.
• Minimal trace space: 3 mil seems to be possible, but 10 mils should be chosen unless there’s a reason to push it. Minimal trace to board edge clearance should be 0.3 mm, but standard edge connector footprints tend to take 0.5mm for their pads. So better go for the latter.
• All in all, it seems like 10 mils for minimal trace width and space, and 0.4mm mils for vias are the sane choice. If the board gets tight, go smaller.
• If the board has an edge connector (“Gold Finger”), it’s ENIG (Electroless Nickel Immersion Gold) surface finish (sometimes referred to as just Immersion Gold). This is required only at the edge connector itself, because the gold’s role is to ensure good contact. According to the IPC-4552 standard, the default thickness of the gold layer is 0.05μm (sometimes referred to as 2U”). Sometimes ENIG is offered as the finish only for the edge connector, but this is relevant only for a large board. For a small board like mine, ENIG applies to the entire board.
• The assembly is the expensive part. Manufacturing should be at around $5-10 for 5 copies for a small board.
• HASL is not RoHS compliant, because of the use of lead. Lead-free HASL should be used instead (or any of the other, more expensive, options).

Finding a manufacturer

My board involved small SMT components, so no chance to do the assembly myself. Actually, 10 simple components, on a plain FR4 53 x 22 mm board with two 1 oz layers and an edge connector (hence ENIG finish). The price for a turn-key project is at least $100. Don’t expect less.

And the minimal order quantity is 5. Everywhere.

The place to make a comparison is  PCB shopper. I also suggest look at Manufacturing Reports for some painfully detailed reviews on PCB quality. If you need assembly (PCBA service, A for assembly), select service by assembly costs, as it’s going to be the dominant part.

So these are the estimated prices I got for a small board.

• Smart Prototyping, assembly at $80.
• Elecrow, assembly at about $106.
• PCBWay, assembly at $30 as a Turnkey project, $88 as kitted or partly kitted. Something tells me they’re going to charge a lot for the devices. They do send stuff with regular E-Packet = 16 days.
• ShenZhen2U, assembly at $50 (pretty much fixed price), allowing plain mail shipping. Headquarters in Hong Kong, but apparently the factory is in Shenzhen (China).

I have no affiliation with any of these companies, and this reflects the situation as of September 2019.

These costs didn’t change much when I changed the parameters of the assembly task. It’s sensible to assume it’s mostly the tooling cost (the cost for programming and setting up the automatic manufacturing equipment).

So I sent the files to PCBWay and ShenZhen2U. My personal impressions:

• PCBWay: Nice web interface, quick and professional response (an hour or so, during Chinese daytime). The price difference between the turnkey and the kitted was indeed a hint to their tendency to make up for the low assembly cost by adding fees everywhere: The components were 50-100% more expensive than Mouser (in low quantity prices). When I asked about it, I got some BS answer that it’s more expensive for them, taxes etc. PCB manufacturing at $39, which is pretty high. And they add $8 Paypal fee and $20 for shipping and handling with E-packet. And then there’s an “assembly promotion discount” of $30, ending up at $108 next to the “Confirm & Pay” button.
• ShenZhen2U: Slightly slower response (1 day each time), the website is slightly less useful. The flow was that I ordered the assembly first, then a few emails back and forth (I filled in their BOM form, where I also defined the PCB, and then got an accurate quote) and then the order at the website was updated manually to reflect their quote. They stood behind the $50 assembly cost. Their BOM costs are only slightly higher than Mouser, and they charge $10 for E-packet shipping. PCB manufacturing at $26, which is pretty low. All in all $110, when paid though Paypal (including a Paypal fee of $4.86, which they were clear about and is reasonable).

So there we have it: Almost exactly the same bottom line. One company reached it after fiddling with the prices, and the second just listed them upfront. This is why I went for ShenZhen2U, even though its review on Manufacturing Reviews complained a lot about dirt and bad silkscreen. The parallel review for PCBWay complained about traces being too thin, which is much more serious IMHO.

My experience with ShenZhen2U is overall good: Even though there was very little communication with them, they manufactured and shipped the boards fairly quickly (I selected very slow shipping and was explicit about the project not being urgent). The five boards arrived, one of which had a defective Micro-B USB 3.0 connector, which short-circuited two pins under a certain mechanical load. This issue showed only with a certain (wiggling) USB plug, so I can’t rule out that they actually tested this connector but didn’t spot the issue because they used a proper USB plug, and not what I have.

As a surprise bonus, they sent a bunch of unassembled boards along. Doesn’t hurt.

Other than the said connector, all boards were OK. As they were manually assembled, there were slight imperfections that are seen in a very detailed view, but the work was definitely good enough for functional purposes. So all in all, the work was good, the price very good, and there was a sense that they know what they’re doing — this is me appreciate that there were zero misunderstandings on those unspoken details. I’m probably going to stay with these guys, and not just because of the price.

I then followed up the same project, with a production of 110 pieces with the same company (ShenZhen2U). In June 2020, I got it done at $690, including everything and shipping with DHL — which is a reasonable price drop for the amount. They got it done quicker than promised, and the result was flawless. They did the panelizing in a sensible way (following my request on which part of the circuit must be smooth) and all cards except one passed a rather rigorous electronic QA test. The one that failed had the same problem with the connector, which might be my fault this time (I might have broken it while pushing the card into its place). Bottom line: They’re good at automatic assembly too.

Finding a manufacturer reloaded (2023)

Fast forward three years, and I needed to fill up the stock with another round of boards. I would have loved to go back to Shenzhen2u again, but they were not responsive, and probably out of business, even though their website was fully functional (but a running website means nothing, as we all know).

So the initial question is: Should I make a test round of 5 boards, and then go for the 110 boards, or jump to the second phase immediately? Back in 2019, the first 5 boards served the purpose of validating my own design, but this time there’s no need for that. So is a test run of 5 boards really worth its cost? I was in no hurry.

For a project with few components like mine, one can expect that the assembly of 5 boards will be done completely by hand, but for 110 boards a machine will be used. So these 5 boards don’t mean much in that respect.

Quality of PCB? It will probably be the same, if both manufacturing rounds are made at the same place. But I will not be surprised if there are several manufacturing facilities behind a PCB company, so each time I’d issue an order it may be handled by a different facility. So making a test with 5 units doesn’t necessarily mean anything about what will happen when I order 110 of them.

And then we have components. There are a lot of replacement components out there, and some of the companies offered these replacements upfront with a lower BOM cost. And they are indeed much cheaper. But what if they use these cheap replacements without telling me? If they do that with a USB plug, I can tell that by the marking on the component, but what about SMT capacitors and resistors? They can put whatever junk they have. How would I tell?

Fake components is a problem even with the most respectable dealers. I’ve actually had a client of mine receive an FPGA that was completely different and incompatible with the one ordered. Yet the marking on the chip was as the one requested. So it was a deliberate fake job, probably by the component dealer’s vendor. And that happened even before COVID-19 and the shortage of components that came with it.

So a 5 board test round probably gives me an idea of whether they put components that aren’t catastrophic and something about the PCB quality. Plus if there are some China-style unexpected surprises in store. Never underestimate the Chinese capability of doing something unexpected.

Whether this round is worth its cost depends, well, on this 5-board round’s price.

What I learned from 3D printing: The only thing I know for sure about is the price. Higher price doesn’t necessarily mean better quality. Returning to the same vendor doesn’t necessarily mean the same result. So go for the offer in terms of price, unless there are bad omens during the initial communication. The chance for failing is basically the same no matter who I choose, so the strategy is to reduce the stake.

There are plenty of reviews for several PCB related companies. Except for the obvious problem that reviews may not be authentic, there’s also a great difference between the needs and expectations of the person who writes the review. An unprofessional maker who builds a simple 2-layer board is not like a professional engineer who submits a super tight and super-complicated multi-layer board and expects the same quality as an expensive European-standard alternative. That said, I’ve also seen expensive manufacturers screwing up completely. The difference is that the latter speak better English.

Which brings me back to the same conclusion: There is really no bulletproof way to know who to work with. The only thing you know for sure is the price.

Getting started, 2023 version

Even today, PCB shopper was the best place to start. There are also reviews on this website, but I had to Google for them – there was no direct link from the homepage to these review pages (only along with price estimations for a specific board). Even though they are clearly affiliated with some of the manufacturers, it still offers some automatic quotes to start with. Then I used ChatGPT in order to get a few additional names. The question was “which manufacturers are often mentioned along with X?”.

Another starting point is to submit the manufacturing files to PCB Directory. They forward the requirements to some manufacturers, and the quotes from these arrive through email. I got two quotes this way (from HiTech Circuits and CanmTech). Needless to say, use a temporary email for this purpose (I get tons of PCB related spam only because of this page).

That said, I checked how much spam I received to email addresses that I used with PCB manufacturers. Surprisingly enough, absolutely none. Except for direct follow-up offers from the same companies, nothing. None of them disclosed my email to third parties. Maybe I shouldn’t be surprised: These are serious businesses, after all.

Speaking of which, of course I didn’t think about turning to all those companies that have been spamming me for years about their PCB factory. I actually checked all candidates, and none of them had ever sent me spam randomly (“your coupon will soon expire” mails is something I won’t consider spam for this purpose).

Elecrow and Seeed Studio did however send me a newsletter promoting their products after subscription, but with an efficient option to unsubscribe. PCB Directory also sent me a newsletter later on, and I unsubscribed.

As for Manufacturing Reports, it doesn’t appear to have been updated since 2023, so it’s not relevant anymore.

So: Picking a manufacturer, 2023 version

Don’t ask me how and why, I ended up with 7 quotes. I asked them for a full turnkey project (including component sourcing) for 5 boards and 110 boards. These are the prices per board as I got them, in USD, including the lowest shipping option that each company offered and all kinds of weird extra fees. In short, these are the price per unit as it would actually cost me.

The table is sorted according to the price for 110 pcs. Keep in mind that this is a simple small board with two layers and 10 components. YMMV.

Don’t get upset if the price jumps up and down throughout the process, and that the estimate of the online calculated might have been too optimistic. Neither how the price is broken down into PCB, PCBA manufacturing, shipping and handling, possibly a separate cost for the stencil and whatnot. The only thing that counts is the total price in the final quote. The rest is just noise that comes from the company’s marketing guys, and they’re out of the way as soon as the order is made, no matter which company you choose.

It’s also fine that their component prices are higher than I can get from Mouser and similar component dealers. They probably get much better prices, yes, but they also add a fee for the work, risk and the extra amount that one has to buy in order to cover up possible mishaps during assembly. Actually, if the price is better that you can get yourself, ask if they didn’t give you a cheap Chinese replacement part, by any chance.

In short: Look at the bottom line only. Never mind how they got to it.

I wrote earlier that the only thing I know for sure is the price, and Elecrow, won with a margin in both quantities. The communication with them was brief, efficient and to the point (unlike several other companies that was between 10-22 mails, just to get the quoting done).

More about Elecrow below…

There were two companies that deserve a comment:

• JLCPCB is maybe the most controversial manufacturer out there. Some love them, some say that they’re a disaster. They have a lot of reviews, for example in Trust Pilot and in Facebook. The reviews of all sorts appear legit, so no doubt there were unhappy people out there. On the other hand, maybe it’s a result of having a lot of customers? Not clear. Anyhow, seeing those reviews, I stayed away.
• PCBWay: Communication with them was really lame and somewhat worrying. I asked for 110 boards, and they said the can only manufacture 125 PCBs. Is that OK? Yes, of course, throw 15 boards to the trash. But then they asked if it’s OK to panelize the board, and if so, if they should depanel them. Even just mentioning the silly idea of not depaneling the boards is worrying. One can only hope that the silliness is limited to their sales, and that the engineering people know better. Regardless, obtaining a quote from these guys was relatively very slow. And tedious.

My experience with Elecrow

They initially suggested a low-cost replacement for the most expensive part, and they were very upfront about it. When I refused, they gave a very reasonable BOM cost (not too low, but neither high).

Placing an order for a turn-key projects was a bit tricky, because their web interface doesn’t suggest how to do that. But I got instructions for that by email, which boils down to this: The idea is to request an online quote for a PCB Assembly, and that allows uploading Gerber files, BOM and files related to assembly. The quote is then found under My Account > Service Orders, and once it has been made, it’s just a matter clicking “Check out” in order to put it in the cart, and then from there to submit an order. The issue of shipping is a bit messed up, because it’s included in the original quote, and then there are shipping options while checking out. So pick “free shipping” to prevent the price from increasing. All in all, their web interface for obtaining quotes and placing orders is not ideal, but once you get the principle it’s smooth.

I put an order for five pieces with Elecrow (92 USD). The Service Orders section in my web account got successively updated as the manufacturing went on, and they uploaded photos of an assembled PCB and even a small video. At some point, I got an email asking me to review the results and confirm shipment.

And this is where things got a little twist. I saw a small notch on the edge of the PCB, which was clearly going to be problematic. But since I only had the picture from one board, and this was a test round, I confirmed the shipment. In this situation, I preferred to see the situation as is, rather than having them fix the problem.

The shipping was quick and smooth, even though I selected a low-cost option:  It was a matter of just 10 days. Which is very quick from China.

Once the boards arrived, I tested them electronically, and they were all 100% OK. There were no surprises. The correct parts were used, no unsolicited replacements. As for the cutting of the boards, they all had this same notch, as shown in this picture that I’ve taken:

It’s important to reiterate: I saw this problem in the picture that was shown to me before confirming the shipment, and I had the opportunity to complain about it. So even though one can question their QA for passing through something like this, odds are that this would have ended well, had it not been for me insisting to get the boards as is.

I wrote a mail to them, asking for the reason to this notch. The answer I got was that the notch is between the cutting machine’s starting point and ending point, as it makes the trajectory to cut out this small board. They emphasized that this is something that happens only for small-volume orders, and that someone simply forgot to remove the notch manually. As for the rather odd position of this notch, I suppose they manufacture several small boards on the same PCB. So the position was convenient in the context of this larger PCB, I guess.

So the question was whether to continue with them or not. I decided to go on with them for the 110 pieces, mainly because everything was perfect, except for this notch thing. And even if this mishap would have happened on 110 boards, it’s not a big deal to remove the notches with a nail file. Silly, but not a big deal.

The results? Excellent. All 110 boards passed the electronic test with no issues at all. And there was no issue with any notch. I couldn’t ask for more.

What to track with git

For a project named projname, this is the list of files I found sufficient to track:

.gitignore
fp-lib-table
projname.dcm
projname.kicad_pcb
projname.lib
projname.pretty/*.kicad_mod
projname.pro
projname.sch
sym-lib-table

as for .gitignore itself, this is my somewhat bloated file, which eventually did the job.

*-save.pro
*-cache.lib
*-rescue.lib
*-save.kicad_pcb
_autosave-*.*
*.kicad_pcb-bak
*.000
*.net
*.net~
*.bak
*.sch-bak
*.bck
*.gbr
*.drl
*.pos
*.wrl
*.csv
*.rpt
*.step
*.stp
*.svg
*.ps
*.pdf
*.dxf
*.plt
*.cad
fp-info-cache
*~

This ignores files produced by KiCad as well as backups. Plus a lot of garlic against files that were never seen.

Even though this is definitely not my expertise, I made a simple adapter board carrying USB 3.0 signals.

The name of the game with such boards is to make a minimal impact on the signals, which means, among others, selecting the attributes of these two pairs of differential lines (SSRX and SSTX) in a way that minimizes the damage their very existence causes.

The other name of the game is to minimize the financial damage by ensuring that the board can be manufactured everywhere and by everyone, in particular those low-cost services.

There are a lot of things to be aware of, and I suggest reading application notes of devices that deal with the relevant type of signals. For example, TI’s board design guidelines for one of their SuperSpeed USB related devices, sllu149e.pdf.

This post focuses on selecting the track width (W) and spacing between the two differential pairs (S) of a coupled microstrip line. This is the widely recommended way to carry RF-frequency differential signals on a PCB, and it simply means that the two wires are routed at one of the exposed layers (top or bottom), and that there’s a ground plane layer immediately underneath it. See drawing at the bottom left of the image below.

Quite interestingly, there is little relation to the W and S of the differential pair in most application notes, so it’s not all that clear what considerations should be made. However, it’s well-known that W and S influence the differential impedance, and this is mentioned everywhere. The USB 3.0 specs requires the differential characteristic impedance to be 90Ω ± 7Ω in section 5.6.1.1.1. So there’s a start.

Assumptions on the PCB

These are the attributes of the most typical PCB one can find (and therefore hopefully low-cost to manufacture):

• Board material: 1 oz copper (0.035 mm thick) on FR4 resin
• Minimal track width: 10 mil. I’m generous here, as several low-cost manufacturers offer as low as 4 mil, but 6 mil is often the minimum for the lowest price. Often there’s a remark saying “>8 mil recommended”. So this indicates what’s considered easily manufactured.
• Minimal spacing between tracks: 10 mils, exactly for the same reasons. Manufacturers tend to give the same figures for both.
• Vias: I didn’t have any (on the differential pairs, that is).

The PCB calculator

There are plenty of online calculators and other utilities for calculating the impedance of microstrip pairs. Since I used KiCad 5.1.4 for the PCB design, I also went for its PCB calculator (image of screenshot below). It’s not the easiest one however.

(click image to enlarge)

Quite obviously, the board’s parameters are on the left column, and the track’s data to the right. So let’s start with the board’s parameters. Note that the “…” to the right allows selecting materials instead of feeding numbers, and guess what, they’re correct (at least those related to my board).

• Er: Select FR4, and the dialectric constant is set correctly to 4.6.
• TanD: Select FR4 here as well, and don’t bother that it’s not accurate (because of the frequency): It doesn’t influence the impedance, but the only the loss calculation.
• Rho: Select copper. It’s resistivity is correct.
• H: The height to the ground plane. In my case, it’s a dual-layer board, so the ground plane is the back side. Hence H is the thickness of the entire board, 1 mm.
• H_t: The height to the ground plane (?) above the board. Luckily, doesn’t have much influence on the impedance unless it’s really small.
• T: The strip thickness. 0.035 mm for 1 oz.
• Conductor roughness: Irrelevant for impedance calculation, but will influence conductor loss calculations
• Relative permeability of conductor: Set to 1 for copper. Copper’s relative permeability, according to Wikipedia, is 0.999994, and this has no influence on impedance calculations.
• Frequency: For a USB 3.0 link, I set it to 5 GHz. Its influence on the impedance is quite small, so no need to be worried about the idea that a digital signal isn’t really band limited and such.

OK, so now what?

The goal is to find W and S. To the right, there’s also L, the length of the trace. It has no influence on the impedance, so any positive number goes. Likewise, we don’t care about the electrical length (Ang_l) which basically says how much delay, in terms of sinusoidal phase of the given frequency, the conductor imposes.

So there are two input parameters, W and S, and two output parameters, Zeven and Zodd. As the signal is differential with no common mode component, we don’t care about Zeven at all: Since Zdiff = Zodd * 2, we just need to make Zodd = 45Ω, more or less.

Or in other words, there is one degree of freedom. There isn’t one pair of W and S for a given board and impedance, but we get to select one of them.

So the rather silly methodology is to pick some initial W and S, more or less at random, and click the down arrow (or “Analyze”). See what we got. Then set Zodd to 45, and click the up arrow (or “Synthesize”). And then some manual iteration, until the result is fine.

But that leaves us with the need to make a decision.

What is a good pair of W and S?

To make a long story short, as small as possible. These wires aren’t carrying any significant currents, so their size is only limited by the manufacturing process (or: How much we’re ready to pay for it). For low-cost manufacturing, consider that they sometimes make the trace thinner by a mil or two (this is the low-quality side of low-cost). So it’s important to be aware of how this would impact the impedance.

Why is small good? Mainly for crosstalk and noise immunity: The closer the wires are to each other, the more do they behave as a differential pair. Being closer to each other, noise signals are added more equally, leading to a smaller differential noise signal. A common rule of thumb is that a differential pair should have a clearance of 5W from any other conductor.

It’s also a matter of taking up less physical space on the board (in particular when respecting the 5W rule above).

As for signal losses, it doesn’t seem to make a big difference.

There is however no defined way to iterate with the calculator to obtain good values. One may select a minimal W and try out several S until Zodd is 45Ω, but it may be below the minimal S allowed.

In that case, start with the minimal S, and increase W until Zodd is 45Ω. If we want to follow the 5W rule, that is probably the best pair achievable.

As for my own choice, it’s the one shown in the image above: W = 0.8 mm, S = 0.2 mm. This makes S a bit smaller than 8 mils. Even though me original intention was not to go below 10 mils, this settings allows me to meet the 5W rule. And it should still be fine to manufacture virtually anywhere.

These rather bulky tracks weren’t easy to connect to the USB receptacle’s footprint, as discussed in another post.

Other calculators

Given the importance of getting these figures right, it’s reassuring to feed the results into other calculators before etching them in metal.

Note that some calculate Zodd and some give you the differential impedance (plus, possibly some other figures). Don’t get confused, and no panic.

• Multi-Teknik’s calculator is much simpler, and also shows the formula.
• Everything RF, also showing the formulas.
• EEweb is more like the PCB calculator (i.e. requires some brain) and shown more math that you probably want to know about.
• All About Circuits is also on the heavier part with the math.

It just so happened that I went for a pair of 0.8mm thick wires, with 0.2mm between them, in order to achieve 90Ω differential impedance on a 1 mm thick FR4 board. No wonder PCBnew (KiCad’s layout program) refused connecting these wires to a USB SuperSpeed receptacle’s footprint, with its 0.4 mm side pads, spaced 0.65 mm apart: They simply can’t get squeezed in.

A similar problem occurred with the 0402-sized coupling capacitors in series with one of the differential pairs: Even though there was no problem connecting the differential wires to the capacitors (after reducing the clearance limit for the relevant tracks), the tracks ran over the capacitors’ pads.

This post suggests manipulating the footprints to match the specific width and spacing of a differential pair. Not the easiest way out, but the result is clean and elegant.

The quick and dirty solution is to draw the tracks until close to the footprint, and do the last segment with a thinner track width. Possible, works, but creates ugly discontinuities, and maybe even signal integrity issues due to reflections.

There is more than one way to do it, and I hope it won’t be too confusing as I jump around between the different options. Each has its advantages and disadvantages.

As a side benefit, this post goes into the technique of making arbitrarily shaped pads.

All said below relates to KiCad 5.1.4, which is up to date as of September 2019. On Linux Mint 19, not that it matters.

Footprints, pads, tracks

Before getting into business, let’s talk a bit about pads and how wire tracks are connected to them.

First of all, the footprint: It’s a collection of graphic elements, each assigned to one or more layers, that are plotted on the PCB layout as a group. The relative position between some elements are fixed, and others can be moved (text labels in particular).

A well-known special element is the pad. Aside from the fact that it’s a useful shortcut to draw a shape on several layers at a time, there are three things that are exclusive for pads:

• Only a pad can be assigned a pin number
• A pad is the final destination for a wire track (it has an “anchor”).
• Drill holes (plated or not) can only be defined with pads.

The first two relate to the capability to connect wires to the component’s pin: The pin number, with respect to the netlist, tells PCBnew which wire track to connect to the pad. The anchor tells where to, geometrically, the wire should be connected. Each wire track starts and end at an anchor point. For simple pads, it’s always at their center.

Remember that if you want to draw something on copper or some other layers, and don’t need any of the three exclusives listed above, just drawing filled polygons on the relevant layers might be a better idea.

And now to the wire track’s geometry.

The final product of the PCB layout is Gerber files. Without getting into the details, the way graphics is defined in these files is with straight lines or arcs (part of a circle, or the entire circle), which are given their thickness with an aperture. This aperture is a filled geometric shape, in most cases either a circle or a square with a per-aperture given size.

The circle aperture is apparently dominant in KiCad: When drawing a wire track on a copper layer, it’s effectively a line with a circular aperture. Think of painting the track’s with a marker having a circular shape, with the diameter of the track’s designated thickness.

Actually, it seems like any line thickness in KiCad is implemented with circular aperture. For example, when drawing filled polygons, there are rounded corners when the line thickness is non-zero, due to the circular aperture.

The conclusion of all this: If the pad is circular, with a diameter matching the wire track’s thickness, there will be a perfect overlap between the pad and the track’s end, no matter what direction the track came from. For a rectangular pad, this holds true only if the track comes straight in, and its edge length matches the thickness of the pad in the same direction.

Modifying footprints

We’ll start with the simpler, and less impressive example: The capacitors’ 0402 footprint. The original 0402 footprint looks like this, with 0.59 x 0.64 mm rounded rectangle pads:

The 0.8 mm thick tracks do connect to a pair of such capacitors, but only after reducing the minimal clearance to 0.15 mm (which is the wrong thing to do):

(click image to enlarge)

It’s quite evident that the tracks are all over the pads. This isn’t all that bad, because the solder mask is still correct (not visible on image above). And yet, the tracks get too close to each other, and they’re not supposed to extend the pads on the copper layer.

So this is what an extended 0402 looks like, with the beginning of a 0.8 mm track on each side:

Each pad actually consists of three elements: The original pad (without the pad number), a filled polygon and a circular pad, which has the pad number assigned to it.

Moving these elements apart a bit for clarity, it looks like this:

But the real need for this technique came from the USB 3.0 receptacle’s footprint, having pads too small for the 0.8 mm tracks:

(click image to enlarge)

To overcome this, extension were added, making pads 0.8 mm wide and 0.2 mm apart. The pad is square in this example, so the track can only arrive directly from above:

(click image to enlarge)

Pad 10 of the image above has been separated for the sake of demonstration.

This is what the result looks like in a PCB design using these:

(click image to enlarge)

Exaggerated perfectionism or the right thing for a 5 or 10 GHz signal, who knows.

How to do this

A pad with type Custom (having rectangular or circular anchor) can be merged with any number of geometrical shapes, turning it into a larger pad, with the shape of the union of all merged areas.

So:

• Draw a filled polygon (on the F.Silk for example) and then change its line thickness to 0.
• Create a pad with “Shape” set to “Custom (Rect. Anchor)”, which will be the actual pad that the wire will be connected to.
• Select both, right-click, and pick “Create Pad from Selected Shapes”.

The attributes (which layers etc.) are taken from the anchor pad, but the shape is the union of the pad and the polygon. As mentioned above, a circular anchor pad with the diameter of the track width is easiest to work with later (but more difficult to match the polygon for).

Note that the extra pad (actually, the anchor pad) should be designated for the copper layer only: No solder mask nor paste layers. We define it as a pad so a track will connect to it, but it’s not going to be soldered on.

What about the courtyard? Should it be extended? Well, no: There’s no problem having other components placed over the extended area, which is part of the wiring. PCBnew ensures no other copper traces get near by virtue of clearance requirements.

Having said all this, note that the trickery with “Create Pad from Selected Shapes” isn’t really necessary. It just makes it simpler to manipulate the shapes as one unit. It also moves the filled polygon from its original layer to the copper layer, but that can be done on the polygon’s own attributes. This way or another, the track connects to the anchor pad (in the merged version) or a simple pad. It doesn’t really matter if the extra geometry is linked to the pad or not.

But now we have two pads

There is the original pad, which is left in place, partly for laziness: It’s already at the right size and place, covering the correct layers (including solder mask and paste), so why mess with it? And then there’s the new pad, which is part of the extension, only for the copper layer.

The question is whether the original pad should also have the pin number, or if it should be pinless. There are basically three options:

1. Keep the pin number, so both pads have the same number. In this case, PCBnew requires both pads to be connected (wires explicitly with tracks) or the original pad is considered unconnected, and will generate a DRC error. Signing off a PCB layout with unconnected nets errors requires a certain amount of courage. And drawing the internal wire without adding dirt may be tricky.
2. Remove pin number designation from original pad. But this will cause PCBnew to complain that the new and original pads are too close (in fact, they’re touching). They are considered two different pads, and generate a DRC error like the following:

   ErrType(19): Pad too close to pad
       @(201.775 mm, 57.300 mm): Pad of J1 on F.Cu and others
       @(204.850 mm, 57.950 mm): Pad 9 of J1 on F.Cu

   Well, in some cases this can be solved by skipping the “Create Pad from Selected Shapes” part, and have two (non-custom) pads, with the filled polygon on the copper layer between them, and hence also making enough space between the pads. It’s a question of the size of the polygon vs. the required pad clearance.

3. Replace the original pad with plain graphics, drawing it as three distinct and overlapping polygons: One for the copper layer, one for the solder mask and one for the solder paste. Rounded corner are achieved with the polygon’s line thickness, if so desired. Haven’t tried this (it’s a bit tedious, after all), but it should work. Note that just merging the original pad’s geometry into the new pad will only cover the copper layer (as the new pad is defined not to cover the two other layers).

I went for the second option, because I allow myself to ignore DRCs on pad-to-pad clearances, but not unconnected net errors. If pad-to-pad clearances are violated because of components placed too close, courtyards are there to prevent them. So making a habit of ignoring pad-to-pad DRC errors is fairly OK.

Impact on signal integrity

I started with this pad manipulation thing because I thought I had no choice, but then I asked myself what this does to the signals. Short answer: I don’t really know, because I haven’t run an electromagnetic simulation on this.

But the word is that any sudden change and discontinuity causes reflections, so connecting to a pad with a gradually changing track width should be better. Maybe, one day, there will be a KiCad feature making all or selected connections between pads and tracks adapting this way.

In fact, think of a thin wire connected to a thicker pad. Wouldn’t it be better if it became gradually thicker as it approaches the pad, so there’s no discontinuity there?

Or maybe it won’t make enough difference to care about this at all. Once again, I don’t know. I guess it’s something the RF guys care more about, and much less us dealing with digital signals.

I should also mention that the way that the pads go sideways on the receptacle shown above, creates a certain difference in the track length, which isn’t accounted for. One can measure the difference manually and feed it into “Pad to die length” in the pad’s attributes, but that was a bit too much for me.

While implementing Xillybus‘ USB 3.0 general purpose IP core for FPGAs, I found the USB Implementers Forum’s compliance tool handy, yet somewhat quirky, for verifying I got things right. It was USB3CV version 2.1.12.1, running on Windows 10 @32 bit. The 64 bit version works the same (I’ve tested it as well).

A GPLed open-source version for Linux is something one could have wished for (and would probably improve things considerably), but that’s probably too much to expect when Microsoft is all over the USB standard.

These are my notes as I went along.

Obtaining and installing

Download USB3CV from this page. Installation went smooth on Windows 10 @32 bits (and 64 bits as well).

As suggested by the utility’s author, disable UAC completely on the system by invoking regedit, setting the EnableLUA to 0 on the following path: HKEY_LOCAL_MACHINE\SOFTWARE\Microsoft\Windows\CurrentVersion\Policies\System. And restart Windows. This seems to be a matter of convenience, and not something to do on anything else but an internal computer intended for testing only, as it’s a security hole.

A usbif.json file can be obtained from USB-IF for use by USB3CV. This only allows looking up the Vendor ID, so there’s no problem working without it. There will be two red lines in the log, but the relevant tests passes without this file as well.

Installing on Windows 7 (32 bit) failed on installing the Microsoft Visual C++ 2017 Redistributable (vc_redist.x86.exe) prerequisite. Despite removing everything installed on that computer (under Programs and Features), the problem remained — it’s probably because SP1 isn’t installed on that machine.

The hijack

When invoked, the USB3CV program replaces the original xHCI driver in Window’s I/O stack with one it uses for testing, and returns the original one when exiting. This means that all USB devices that are connected to the USB controller (possibly all USB devices on a motherboard) become effectively disconnected. That includes USB 2.0 and USB 1.1 devices. To work around this, either use good-old PS/2 keyboard and mouse, employ a remote session, or plug in an extra USB board (possibly as low as USB 1.1) and plug the USB mouse and keyboard there. Otherwise, well, no mouse and keyboard on a Windows system.

Also, be sure to close USB3CV before shutting down Windows, or it may not have enough time to bring the original driver back. See more notes on this issue below.

USB3CV is kind enough to prompt for which USB controller to take over, and it’s also fine if you accidentally knock out your own USB mouse and keyboard (a second dialog box requires confirming the takeover with a mouse click, or it times out and reverts it).

The immediate difference when plugging in a device when USB3CV is running (and has taken over the relevant controller) is that nothing happens — there is no enumeration nor descriptor fetching, as there would usually be. This happens only later on, when requesting tests, in which case the controller is scanned for devices. Several times, actually.

Another significant difference is that the test xHCI driver doesn’t have these small workaround features that a usual xHCI driver has for getting unstuck from protocol bug deadlocks, and it doesn’t attempt to smooth protocol errors. Which makes sense: A regular xHCI driver’s goal is to make the device work. The test driver is there to expose errors, so it should get stuck when things are done wrong. Hence it may expose bugs that were smoothed out when the device was connected in a regular manner to a computer. For example, a bug in the device’s LTSSM implementation may be smoothed out by a regular driver by issuing a warm reset and starting all over again, without any log message, but USB3CV’s driver will just fail.

So if weird stuff happens with USB3CV, check your own implementation, and don’t look for bugs in USB3CV. Reject the immediate “but it worked before” instinct to blame something else than your own design.

Hands on

Double-click the USB 3 Gen X CV icon. A dialog box with a list of USB controller(s) opens. Select the one that the device is attached to. All other USB devices on that controller, of all speeds, will be disconnected from the computer. Then the “Command Verifier” asks to verify this choice. If you just disabled your own mouse and keyboard you can’t click “Continue”, and that dialog box will time out, and the hijacked USB controller is released.

Then the main windows opens. Select “Chapter 9 Tests (USB 3 Gen X devices)”, Compliance Test (or Debug for individual tests), and click Run.

This is when USB3CV tries to find devices on the hijacked USB controller (it’s complete silence on wires until then). Sometimes this fails for no apparent reason — see below. A dialog box asking to select the device to work with appears, and is then followed by three dialog boxes asking for the number of retimers. If you don’t know what it’s about, you don’t have any, so select zero on all three.

When tests fail, the error messages may be misleading. For example, a problem with the device’s LTSSM made the GetDecriptor() test fail, spitting out the paragraphs in the spec that aren’t met, but on the wires there was no related SETUP packet sent (because the link wasn’t up, it turned out eventually). However the SET_SEL test went through OK nevertheless. So it may be really confusing. This is easily mistaken for a bug in USB3CV.

Even worse, it seems like a test failure can lead to all kind of unexpected and unrelated errors in following tests.

The tool also complains when the device declares itself as USB 3.0 in the device descriptor rather than USB 3.2, considering it to be a test failure. What about USB 3.0 devices, not supporting anything related to SuperSpeedPlus? Why should they even mention USB 3.2?

When things get stuck

If weird things happen (in particular if the device isn’t found by USB3CV and/or otherwise) re-run USB3CV and exit it, so the original xHCI controller is brought back upon exit. That’s what USB3CV expects to see on invocation, and it doesn’t work properly otherwise. So just run the tool and exit immediately, and then run it again.

It’s better to start USB3CV with the device already plugged in. Moving it to another plug while USB3CV is running often helps.

Crashes

Unfortunately, USB3CV crashes quite a lot (mostly in relation with test failures, in particular failing tests related to low power states). The “Command Verifier Tool has stopped working” dialog box may appear. A rather ironic workaround seems to work: Clicking “Abort” as the tests run (towards the end, actually), and then clicking “No”, a bit before the end of the tests, in the dialog box asking if you really want to abort (so the test isn’t aborted, after all). Sometimes the enumeration test is done, sometimes it isn’t (and fails with some ugly error), so maybe that’s related.

Sometimes USB3CV just gets stuck in a test, and attempting abort the test doesn’t help. Closing the USB3CV windows brings up “Wait for a stack switch” after which Windows crashes with a “Your PC ran into a problem and needs to restart. You can restart”. Which probably means that it’s OK to recycle power (no other possibility left). Windows suggest searching online for “WDF_VIOLATION” too.

Whether the power recycle took place or not, USB3CV didn’t have the opportunity to return the original xHCI driver as it usually does upon a normal exit. Therefore, be sure to invoke and exit USB3CV as mentioned above to get the system back to its original state.

After quite a while of working perfectly well, the mini HDMI2AV module I have (in the picture above, mentioned in this post) started producing an unstable picture, and in the end a completely garbled one. It took some time to nail down this specific component in the foodchain, because there was also an HDMI splitter involved.

The problem, as it turned out, was that this module takes voltage from the HDMI plug, if such is available, instead of the dedicated power plug. In my specific setup, it seems like there was some voltage was available, but not enough to drive the device — because the HDMI plug was connected to the HDMI splitter. I suppose some internal power supply switch went into some not-here-not-there kind of situation, and eventually got some permanent damage. The other HDMI2AV unit I have didn’t work either in the same conditions, but probably didn’t reach the point of permanent damage (so it’s working right now).

On an HDMI connector, Pin 18 is +5V, minimum 55 mA, intended originally to feed the monitor with voltage even if it’s shut off, so its DDC (EDID) information can be obtained. Some devices (e.g. cheap HDMI splitters and HDMI to AV converters) might use this voltage instead of the supplied external voltage in some cases.

Not all cables conduct this pin. It’s therefore advisable to check the cable before working with it, when the setup is more than just a direct connection. It’s not easy, even with a multimeter. Pushing a thin wire into the tiny holes at the front may give contact with the relevant pin, but this isn’t bulletproof. Possibly try with an HDMI/DVI adapter (pin 14 on a DVI connector is +5V). Or test with a device that is known to rely on this voltage (e.g. this HDMI2AV module).

The solution in my case was to replace the HDMI2AV module and all cables with such that don’t let the +5V wire through. In particular, it seems like the cable to the TV set (via HDMI) that went to the HDMI splitter (which connects to the HDMI2AV module on its other output) was the issue.

This is the information obtained with xrandr from the HDMI to AV converter  (Composite Video + Audio on RCA plugs) shown above:

Screen 0: minimum 8 x 8, current 1280 x 720, maximum 32767 x 32767
DP1 disconnected (normal left inverted right x axis y axis)
DP2 disconnected (normal left inverted right x axis y axis)
DP3 disconnected (normal left inverted right x axis y axis)
HDMI1 disconnected (normal left inverted right x axis y axis)
HDMI2 disconnected (normal left inverted right x axis y axis)
HDMI3 connected primary 1280x720+0+0 (normal left inverted right x axis y axis) 708mm x 398mm
 1280x720      60.00*+  59.94 
 1920x1080     60.00    59.94 
 1600x1200     60.00 
 1680x1050     59.88 
 1400x1050     59.95 
 1600x900      60.00 
 1280x1024     60.02 
 1440x900      59.90 
 1280x960      60.00 
 1280x800      59.91 
 1024x768      60.00 
 800x600       60.32 
 720x480       60.00    59.94 
 640x480       60.00    59.94 
VIRTUAL1 disconnected (normal left inverted right x axis y axis)

And with “verbose” flag:

Screen 0: minimum 8 x 8, current 1280 x 720, maximum 32767 x 32767
DP1 disconnected (normal left inverted right x axis y axis)
 Identifier: 0x43
 Timestamp:  919743
 Subpixel:   unknown
 Clones:   
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This was done with the switch in “PAL” position, but I’m not sure it matters.

Not to mention that it’s impossible to tell what’s going on looking at the pdf schematics: Try to search for the net’s name, and you’ll find it in 20 places, 18 of which are the inter-hierarchy connections of that net. One of which, is maybe wrong, but is virtually impossible to spot.

On a good day, everything looks fine and in order, and noone notices small killers like the one below. It’s easy (?) to spot it now that I’ve put the focus on it, but would you really see this on page 23 of yet another block connection in the schematics?

Click to enlarge (this is from a real-life design made by a serious company):

So please, PCB designers, wherever you are: Look at any reference design you can find, and do the same: Just put the net names that belong to another page. Don’t try to show the connections between the blocks. They help nobody. If the net name is meaningful, we will all understand on which page to look for it. And if we don’t, we use our pdf browser’s search feature. Really.

At first I thought that there was something wrong with my reference clock. But it was OK.

Only after a while did I realize that the PLL needs to be recalibrated after the registers are set. The CDCE62002 wasn’t intended to be programmed after powerup, like the CDCE906. The by-design use is to program the EEPROM once, and then power it up. Doing it this way, the correct values go into the RAM from EEPROM, after which calibration takes place with the correct parameters.

Solution: Power down the device by clearing bit 7 in register #2, write the desired values in registers #0 and #1, and then power up again by setting bit 7 (and and bit 8, regardless) in register #2. This way the device wakes up as is the registers were loaded from EEPROM, and runs its calibration routine correctly.

What I still don’t understand, is why I have to do this twice. The VCO seems to go to its highest frequency now, unless I repeat the ritual mentioned above again 100 ms after the first time. If I do this within microseconds it’s no good.

I’ve written a Verilog module to handle this. Basically, send_data should be asserted during one clock cycle, and the parameter inputs should be held steady for some 256 clock cycles afterwards. As I’m using this module, there are constant values there.

This is not an example of best Verilog coding techniques, but since I didn’t care about either slice count or timing here, I went for the quickest solution, even if it’s a bit dirty. And it works.

Note that the module’s clock frequency should not exceed 40 MHz, since the maximal SPI clock allowed by spec is 20 MHz. And again, for this to really work, send_data has to be asserted twice, with some 100 ms or so between assertions. I’ll check with TI about this.

module cdce62002
  (
   input          clk, // Maximum 40 MHz
   input 	  reset, // Active high

   output 	  busy,

   input          send_data,
   output reg     spi_clk, spi_le, spi_mosi,
   input          spi_miso,  // Never used

   // The names below match those used in pages 22-24 of the datasheet

   input  INBUFSELX,
   input  INBUFSELY,
   input  REFSEL,
   input  AUXSEL,
   input  ACDCSEL,
   input  TERMSEL,
   input [3:0]  REFDIVIDE,
   input [1:0]  LOCKW,
   input [3:0]  OUT0DIVRSEL,
   input [3:0]  OUT1DIVRSEL,
   input   HIPERFORMANCE,
   input   OUTBUFSEL0X,
   input   OUTBUFSEL0Y,
   input   OUTBUFSEL1X,
   input   OUTBUFSEL1Y,

   input  SELVCO,
   input [7:0]  SELINDIV,
   input [1:0]  SELPRESC,
   input [7:0]  SELFBDIV,
   input [2:0]  SELBPDIV,
   input [3:0]  LFRCSEL
   );

   reg [7:0] 	  out_pointer;
   reg 		  active;

   wire [255:0]   data_out;
   wire [255:0]   le_out;
   wire [27:0] 	  word0, word1, word2, word3;
   wire [27:0] 	  ones = 28'hfff_ffff;

   // synthesis attribute IOB of spi_clk is true;
   // synthesis attribute IOB of spi_le is true;
   // synthesis attribute IOB of spi_mosi is true;

   // synthesis attribute init of out_pointer is 0 ;
   // synthesis attribute init of active is 0 ;
   // synthesis attribute init of spi_le is 1;

   assign 	  busy = (out_pointer != 0);

   // "active" is necessary because we don't rely on getting a proper
   // reset signal, and out_pointer is subject to munching by the
   // synthesizer, which may result in nasty things during wakeup

   always @(posedge clk or posedge reset)
     if (reset)
       begin
	  out_pointer <= 0;
	  active <= 0;
       end
     else if (send_data)
       begin
	  out_pointer <= 1;
	  active <= 1;
       end
     else if ((spi_clk) && busy)
       out_pointer <= out_pointer + 1;

   always @(posedge clk)
     begin
	if (spi_clk)
	  begin
	     spi_mosi <= data_out[out_pointer];
	     spi_le <= !(le_out[out_pointer] && active);
	  end
	spi_clk <= !spi_clk;
     end 

   assign data_out = { word3, 4'd2, 2'd0, // To register #2 again.
		       64'd0, // Dwell a bit in power down
		       word1, 4'd1, 2'd0,
		       word0, 4'd0, 2'd0,
		       word2, 4'd2, 4'd0
		       };

   assign le_out = { ones[27:0], ones[3:0], 2'd0,
		     64'd0, // Dwell a bit in power down
		     ones[27:0], ones[3:0], 2'd0,
		     ones[27:0], ones[3:0], 2'd0,
		     ones[27:0], ones[3:0], 4'd0 };

   assign word0[0] = INBUFSELX;
   assign word0[1] = INBUFSELY;
   assign word0[2] = REFSEL;
   assign word0[3] = AUXSEL;
   assign word0[4] = ACDCSEL;
   assign word0[5] = TERMSEL;
   assign word0[9:6] = REFDIVIDE;
   assign word0[10] = 0; // TI trashed external feedback
   assign word0[12:11] = 0; // TI's test bits
   assign word0[14:13] = LOCKW;
   assign word0[18:15] = OUT0DIVRSEL;
   assign word0[22:19] = OUT1DIVRSEL;
   assign word0[23] = HIPERFORMANCE;
   assign word0[24] = OUTBUFSEL0X;
   assign word0[25] = OUTBUFSEL0Y;
   assign word0[26] = OUTBUFSEL1X;
   assign word0[27] = OUTBUFSEL1Y;

   assign word1[0] = SELVCO;
   assign word1[8:1] = SELINDIV;
   assign word1[10:9] = SELPRESC;
   assign word1[18:11] = SELFBDIV;
   assign word1[21:19] = SELBPDIV;
   assign word1[25:22] = LFRCSEL;
   assign word1[27:26] = 2'b10; // Read only bits   

   // word2 and word3 are both sent to register #2 in order to
   // restart the PLL calibration after registers are set.

   assign word2 = 28'h000_0100; // Power down
   assign word3 = 28'h000_0180; // Exit powerdown
endmodule