my tech blog » timing https://billauer.se/blog Anything I found worthy to write down. Thu, 12 Mar 2026 11:36:00 +0000 en hourly 1 http://wordpress.org/?v=3.1.2 The PCF file: Xilinx timing constraints as the tools understood them https://billauer.se/blog/2009/07/xilinx-timing-constraints-ucf-pcf-tnm-period-from-to/ https://billauer.se/blog/2009/07/xilinx-timing-constraints-ucf-pcf-tnm-period-from-to/#comments Fri, 24 Jul 2009 09:39:53 +0000 eli https://billauer.se/blog/?p=302 One of the problems with setting up timing constraints in the UCF file, is to be sure that you got the right elements in, and kept the unnecessary ones out.

Suppose I wrote something like

NET "the_clock" TNM_NET = "tnm_ctrl_clk";
TIMESPEC "TS_ctrl_clk" = PERIOD "tnm_ctrl_clk" 40 ns HIGH 50 %;

What logic element does it apply to? Did it work like I expected?

The information can be obtained by creating a timegroup report in the Timing Analyzer, but it’s actually available in a much easier way: The PCF file, which is created by the MAP tool. This file has the same syntax as the UCF file, but it reflects the constraints as understood by the tools.

You will find the as-made pin placements there (not shown here), and the timing groups as TIMEGRP statements. It goes something like:

TIMEGRP tnm_ctrl_clk = BEL "controller/bus_oe_16" BEL
        "controller/ctrl_dout_15" BEL "controller/bus_oe_15" BEL
        "controller/ctrl_dout_14" BEL "controller/bus_oe_14" BEL
        "controller/ctrl_dout_13" BEL "controller/bus_oe_13" BEL
        "controller/ctrl_dout_12" BEL "controller/bus_oe_12" BEL
        "controller/ctrl_dout_11" BEL "controller/bus_oe_11" BEL
        "controller/ctrl_dout_10" BEL "controller/bus_oe_10" BEL
        "controller/ctrl_dout_9" BEL "controller/bus_oe_9" BEL
        "controller/ctrl_dout_8" BEL "controller/bus_oe_8" BEL
        "controller/ctrl_dout_7" BEL "controller/bus_oe_7" BEL
        "controller/ctrl_dout_6" BEL "controller/bus_oe_6" BEL
        "controller/ctrl_dout_5" BEL "controller/bus_oe_5" BEL
        "controller/ctrl_dout_4" BEL "controller/bus_oe_4" BEL
        "controller/ctrl_dout_3" BEL "controller/bus_oe_3" BEL
        "controller/ctrl_dout_2" BEL "controller/bus_oe_2" BEL
        "controller/ctrl_dout_1" BEL "controller/bus_oe_1" BEL
        "controller/ctrl_dout_0";

There you have it, in plain text. The relevant constraint is just a few rows away:

TS_ctrl_clk = PERIOD TIMEGRP "tnm_ctrl_clk" 40 ns HIGH 50%;

As simple as that.

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