my tech blog » Intel FPGA (Altera) https://billauer.se/blog Anything I found worthy to write down. Thu, 12 Mar 2026 11:36:00 +0000 en hourly 1 http://wordpress.org/?v=3.1.2 Quartus Pro 19.2: List of QSF parameter names https://billauer.se/blog/2021/10/quartus-pro-qsf-list/ https://billauer.se/blog/2021/10/quartus-pro-qsf-list/#comments Thu, 14 Oct 2021 15:15:34 +0000 eli https://billauer.se/blog/?p=6419 Due to rather peculiar reasons described in this post, I found myself looking for all QSF parameter names that Quartus recognizes. I ended up searching a binary file in Quartus’ installation directory. So this is by no means an authoritative list, but since I made it, I thought I should post it. Just in case someone else is in the business of guesswork.

So this was done with Quartus Pro 19.2 running Linux. For non-Pro Quartus 17.1, refer to this post.

This is plain text search, so quite clearly not all items appearing here are legal QSF parameters, and neither is it clear if this list is complete. Or otherwise useful, for that matter.

$ strings ./quartus/linux64/libdb_acf.so | perl -ne '/^[A-Z][A-Z0-9_]+\n*$/ && print' | sort -u
  • ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS
  • ACCEPTS_NEGATIVE
  • ACCEPTS_OPEN
  • ACCEPTS_SHORT
  • ACCEPTS_TRACK_VCCIO
  • ACCEPTS_WILDCARDS
  • ACCEPTS_ZERO
  • AC_COUPLING
  • ACEX1K
  • ACF_ASSIGNMENT_USE_STRING_POOL
  • ACF_NOTIFY_ACF_MANAGER_ASSIGNMENTS_CHANGED
  • ACF_STRING_POOL_MASSIVE_DUMP
  • ACF_VARIABLE_TRAIT_TYPE_MAX_TRAIT_TYPE
  • ACF_VARIABLE_TYPE_ACF_ACF_LAST_VARIABLE
  • ACLK_CAT
  • ACLK_RULE_IMSZER_ADOMAIN
  • ACLK_RULE_NO_SZER_ACLK_DOMAIN
  • ACLK_RULE_SZER_BTW_ACLK_DOMAIN
  • ACTION
  • ACTIVE_PARALLEL
  • ACTIVE_SERIAL_CLOCK
  • ACTIVE_SERIAL
  • ACTIVE_SERIAL_X1
  • ACTIVE_SERIAL_X4
  • ADCE_ENABLED
  • ADCE_FULL_BW
  • ADCE_HALF_BW
  • ADCE_HIGH_BW
  • ADCE_HIGH_FREQ_MODE
  • ADCE_LOW_BW
  • ADCE_LOW_FREQ_MODE
  • ADCE_MED_HIGH_BW
  • ADCE_MED_HIGH_MODE
  • ADCE_MED_LOW_BW
  • ADCE_MED_LOW_MODE
  • ADD_DEFAULT_PINS_TO_OUTPUT_VECTOR_FILE
  • ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS
  • ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
  • ADD_TO_SIMULATION_OUTPUT_WAVEFORMS
  • ADVANCED_CLOCK_OPTIMIZATION
  • ADVANCED
  • ADVANCED_PHYSICAL_OPTIMIZATION
  • ADVANCED_PHYSICAL_RETIMING
  • ADVANCED_PHYSICAL_SYNTHESIS
  • ADVANCED_PHYSICAL_SYNTHESIS_REGISTER_PACKING
  • ADVANCED_PRE_PHYSICAL_SYNTHESIS
  • ADV_NETLIST_OPT_ALLOWED
  • ADV_NETLIST_OPT_DONT_TOUCH
  • ADV_NETLIST_OPT_FIT_LE_DUPLICATION
  • ADV_NETLIST_OPT_FIT_LE_DUPLICATION_WITH_LUT_RESYNTHESIS
  • ADV_NETLIST_OPT_FIT_LE_RETIME
  • ADV_NETLIST_OPT_METASTABLE_REGS
  • ADV_NETLIST_OPT_RETIME_CORE_AND_IO
  • ADV_NETLIST_OPT_STRING
  • ADV_NETLIST_OPT_SYNTH_ALLOW_IP_WYS_UNMAPPING
  • ADV_NETLIST_OPT_SYNTH_GATE_RETIME_1
  • ADV_NETLIST_OPT_SYNTH_GATE_RETIME_2
  • ADV_NETLIST_OPT_SYNTH_GATE_RETIME
  • ADV_NETLIST_OPT_SYNTH_REMAP_1
  • ADV_NETLIST_OPT_SYNTH_REMAP_2
  • ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO
  • ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP
  • ADV_NETLIST_OPT_TEST
  • AFTER_INIT_DONE
  • AGGREGATE
  • AGGREGATE_REVISION
  • AGGRESSIVE_AREA
  • AGGRESSIVE_COMPILE_TIME___INTERNAL
  • AGGRESSIVE_COMPILE_TIME
  • AGGRESSIVE
  • AGGRESSIVE_POWER
  • AHDL_FILE
  • AHDL_INCLUDE_FILE
  • AHDL_LIMIT_INT_TO_32
  • AHDL_TEXT_DESIGN_OUTPUT_FILE
  • AHDL_USE_LPM_FOR_OPERATORS
  • ALIAS
  • ALL_EDGE
  • ALL_EXCEPT_COMBINATIONAL_LOGIC_ELEMENT_OUTPUTS
  • ALL_NODES
  • ALLOW_ACLR_FOR_SHIFT_REGISTER_RECOGNITION
  • ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION
  • ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION
  • ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION
  • ALLOW_CASCADE_GPLL_TO_LVDS_TX
  • ALLOW_CHILD_PARTITIONS
  • ALLOW_DSP_RETIMING
  • ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER
  • ALLOW_MULTIPLE_PERSONAS
  • ALLOW_PARALLEL_TERMINATION
  • ALLOW_POWER_UP_DONT_CARE
  • ALLOW_RAM_RETIMING
  • ALLOW_REGISTER_DUPLICATION
  • ALLOW_REGISTER_MERGING
  • ALLOW_REGISTER_RETIMING
  • ALLOW_ROUTING_TO_PERIPHERY_THROUGH_GLOBAL_NETWORK
  • ALLOW_SERIES_TERMINATION
  • ALLOW_SERIES_WITH_CALIBRATION_TERMINATION
  • ALLOW_SEU_FAULT_INJECTION
  • ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES
  • ALLOW_SYNCH_CTRL_USAGE
  • ALLOW_VCCR_VCCT_PER_BANK
  • ALLOW_VCCR_VCCT_PER_SIX_PACK
  • ALLOW_XOR_GATE_USAGE
  • ALL_PATHS
  • ALL_STAGES_ENABLED
  • ALM_REGISTER
  • ALM_REGISTER_PACKING_EFFORT
  • ALTERA_A10_IOPLL_BOOTSTRAP
  • ALTERA_INTERNAL_FIB
  • ALTERA
  • ALWAYS_ALLOW
  • ALWAYS_ENABLE_INPUT_BUFFERS
  • ALWAYS
  • ALWAYS_REGENERATE_IP
  • ALWAYS_REGENERATE_IP_SIM
  • ALWAYS_WRITE_TO_FILE
  • ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS
  • ANALYZE_LATCHES
  • ANALYZE_METASTABILITY
  • APEX20KC
  • APEX20K_CLIQUE_TYPE
  • APEX20K_CONFIG_DEVICE_JTAG_USER_CODE
  • APEX20K_CONFIGURATION_DEVICE
  • APEX20K_CONFIGURATION_SCHEME
  • APEX20K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
  • APEX20K_DEVICE_IO_STANDARD
  • APEX20KE_DEVICE_IO_STANDARD
  • APEX20KE
  • APEX20KF_DEVICE_IO_STANDARD
  • APEX20K_JTAG_USER_CODE
  • APEX20K
  • APEX20K_LOCAL_ROUTING_SOURCE
  • APEX20K_OPTIMIZATION_TECHNIQUE
  • APEX20K_TECHNOLOGY_MAPPER
  • APEX_FITTER_TYPE
  • APEXII_1_8V_HSTL
  • APEX_II_CONFIGURATION_SCHEME
  • APEXII_CONFIGURATION_SCHEME
  • APEXII_DEVICE_IO_STANDARD
  • AREA
  • AREF_VOLT_0
  • AREF_VOLT_0P5
  • AREF_VOLT_0P75
  • AREF_VOLT_1P0
  • ARM_ASM_COMMAND_LINE
  • ARM_CPP_COMMAND_LINE
  • ARM_LINK_COMMAND_LINE
  • ARMSTRONG_CARRY_CHAIN_LENGTH
  • ARMSTRONG_OPTIMIZATION_TECHNIQUE
  • ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE
  • AS_BIDIRECTIONAL
  • ASCII_REPORT_FILE
  • AS_FREQ_100MHZ
  • AS_FREQ_108MHZ
  • AS_FREQ_115MHZ_IOSC
  • AS_FREQ_125MHZ
  • AS_FREQ_133MHZ
  • AS_FREQ_166_6MHZ
  • AS_FREQ_25MHZ_IOSC
  • AS_FREQ_25MHZ
  • AS_FREQ_38MHZ_IOSC
  • AS_FREQ_50MHZ
  • AS_FREQ_58MHZ_IOSC
  • AS_FREQ_71_5MHZ
  • AS_FREQ_77MHZ_IOSC
  • AS_FREQ_80MHZ
  • ASIC_EMULATION_FAST_FLOW
  • ASIC_PROTOTYPING_ADVANCED
  • ASIC_PROTOTYPING_FEATURES
  • ASIC_PROTOTYPING_LATCH_SUPPORT
  • ASIC_PROTOTYPING
  • ASIC_PROTOTYPING_READBACK_WRITEBACK
  • AS_INPUT_TRI_STATED
  • AS_INPUT_TRI_STATED_WITH_BUS_HOLD
  • AS_INPUT_TRI_STATED_WITH_WEAK_PULL_UP
  • ASM_FILE
  • ASM_OPTIONS_FILE_KEYWORD
  • AS_OUTPUT_DRIVING_AN_UNSPECIFIED_SIGNAL
  • AS_OUTPUT_DRIVING_GROUND
  • AS_OUTPUT_DRIVING_VCC
  • ASP_ASM_COMMAND_LINE
  • ASP_CPP_COMMAND_LINE
  • ASP_LINK_COMMAND_LINE
  • ASSEMBLER_ASSIGNMENT
  • ASSG_CAT
  • ASSG_RULE_MISSING_FMAX
  • ASSG_RULE_MISSING_TIMING
  • AS_SIGNALPROBE_OUTPUT
  • ASSIGNMENT_GROUP_ASSIGNMENT
  • ASSIGNMENT_GROUP_EXCEPTION
  • ASSIGNMENT_GROUP
  • ASSIGNMENT_GROUP_MEMBER
  • AS_VREFA
  • AS_VREFB
  • AS_VREF
  • ATSH
  • ATTRACTION_GROUP
  • ATTRACTION_GROUP_SOFT_REGION
  • ATUH
  • ATUSH
  • ATUSL
  • AUATI
  • AUATL
  • AUATUH
  • AUATUSH
  • AUATUS
  • AUTO_C3_M9K_BIT_SKIP
  • AUTO_CARRY_CHAINS
  • AUTO_CARRY
  • AUTO_CASCADE_CHAINS
  • AUTO_CASCADE
  • AUTO_CLOCK_ENABLE_RECOGNITION
  • AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS
  • AUTO_DELAY_CHAINS
  • AUTO_DISCOVER_AND_SORT
  • AUTO_DISCOVERY
  • AUTO_DSP_RECOGNITION
  • AUTO_ENABLE_SMART_COMPILE
  • AUTO_EXPORT_INCREMENTAL_COMPILATION
  • AUTO_EXPORT_VER_COMPATIBLE_DB
  • AUTO_FAST_INPUT_REGISTERS
  • AUTO_FAST_OUTPUT_ENABLE_REGISTERS
  • AUTO_FAST_OUTPUT_REGISTERS
  • AUTO_FIT
  • AUTO_GLOBAL_CLOCK
  • AUTO_GLOBAL_CLOCK_MAX
  • AUTO_GLOBAL_MEM_CTRL
  • AUTO_GLOBAL_MEMORY_CONTROLS
  • AUTO_GLOBAL_OE
  • AUTO_GLOBAL_OE_MAX
  • AUTO_GLOBAL_REG_CTRL
  • AUTO_GLOBAL_REG_CTRL_MAX
  • AUTO_GLOBAL_REGISTER_CONTROLS
  • AUTO_IMPLEMENT_IN_ROM
  • AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE
  • AUTO_INCREMENT_EPROM_JTAG_CODE
  • AUTO_INCREMENT_USER_JTAG_CODE
  • AUTO_INPUT_REGISTER
  • AUTO_INPUT_REGISTERS
  • AUTO_INSERT_SLD_HUB_ENTITY
  • AUTO_INSERT_SLD_INCR_NODE_ENTITY
  • AUTO_INSERT_SLD_NODE_ENTITY
  • AUTO_LCELL_INSERTION
  • AUTO
  • AUTOMATICALLY
  • AUTOMATIC_DANGLING_PORT_TIEOFF
  • AUTOMATIC
  • AUTO_MERGE_PLLS
  • AUTO_MODIFIED_PACKED_REGISTERS
  • AUTONOMOUS_PCIE_HIP
  • AUTO_OPEN_DRAIN
  • AUTO_OPEN_DRAIN_PINS
  • AUTO_OUTPUT_ENABLE_REGISTER
  • AUTO_OUTPUT_REGISTER
  • AUTO_OUTPUT_REGISTERS
  • AUTO_PACKED_REG_CYCLONE
  • AUTO_PACKED_REGISTERS_ARMSTRONG
  • AUTO_PACKED_REGISTERS_CYCLONE
  • AUTO_PACKED_REGISTERS
  • AUTO_PACKED_REGISTERS_MAXII
  • AUTO_PACKED_REGISTERS_MAX
  • AUTO_PACKED_REGISTERS_STRATIXII
  • AUTO_PACKED_REGISTERS_STRATIX
  • AUTO_PACKED_REGISTERS_TSUNAMI
  • AUTO_PARALLEL_EXPANDERS
  • AUTO_PARALLEL_SYNTHESIS
  • AUTO_PERIPH
  • AUTO_PEXP
  • AUTO_QIC_EXPORT
  • AUTO_QXP_PARTITION
  • AUTO_RAM_BLOCK_BALANCING
  • AUTO_RAM_RECOGNITION
  • AUTO_RAM_TO_LCELL_CONVERSION
  • AUTO_RESERVE_CLKUSR_FOR_CALIBRATION
  • AUTO_RESOURCE_SHARING
  • AUTO_RESTART_CONFIGURATION
  • AUTO_RESTART
  • AUTO_ROM
  • AUTO_ROM_RECOGNITION
  • AUTO_SHIFT_REGISTER_RECOGNITION
  • AUTO_SLD_HUB_ENTITY
  • AUTO_TURBO_BIT
  • AUTO_USE_SIMULATION_PDB_NETLIST
  • AVAUA
  • AVAUATA
  • AVAUATI
  • AVAUATUH
  • AVAUATUSH
  • AVAUI
  • AVAUL
  • AVST_CLK_RESERVED
  • AVST_DATA15_0_RESERVED
  • AVST_DATA31_16_RESERVED
  • AVST_VALID_RESERVED
  • AVST_X16
  • AVST_X32
  • AVST_X8
  • AVUH
  • AWAVA
  • AWAVAUA
  • AWAVAUATA
  • AWAVAUATI
  • AWAVAUATL
  • AWAVAUATUH
  • AWAVAUATU
  • AWAVAUATUSH
  • AWAVAUATUS
  • AWAVAUI
  • AWAVAUL
  • AWAVAUM
  • AWAVE
  • AWAVI
  • AWAVL
  • AWAVM
  • BACKUP_BATTERY_RAM
  • BAK_AUTO_EXPORT
  • BAK_EXPORT_DIR
  • BALANCED
  • BASE_CLOCK
  • BASED_ON_CLOCK_SETTINGS
  • BASE
  • BASEO
  • BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE
  • BASE_REVISION
  • BASE_REVISION_PROJECT_OUTPUT_DIRECTORY
  • BASIC
  • BDF_FILE
  • BEST
  • BIAS_INT
  • BIAS_VCMDRV
  • BIDIRECTIONAL
  • BINARY_FILE
  • BLACKBOX
  • BLOCK_DESIGN_NAMING
  • BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES
  • BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS
  • BLOCK_RAM_TO_MLAB_CELL_CONVERSION
  • BOARD
  • BOARD_MODEL_CUSTOM
  • BOARD_MODEL_EBD_FAR_END
  • BOARD_MODEL_EBD_FILE_NAME
  • BOARD_MODEL_EBD_SIGNAL_NAME
  • BOARD_MODEL_FAR_C
  • BOARD_MODEL_FAR_DIFFERENTIAL_R
  • BOARD_MODEL_FAR_PULLDOWN_R
  • BOARD_MODEL_FAR_PULLUP_R
  • BOARD_MODEL_FAR_SERIES_R
  • BOARD_MODEL_NEAR_C
  • BOARD_MODEL_NEAR_DIFFERENTIAL_R
  • BOARD_MODEL_NEAR_PULLDOWN_R
  • BOARD_MODEL_NEAR_PULLUP_R
  • BOARD_MODEL_NEAR_SERIES_C
  • BOARD_MODEL_NEAR_SERIES_R
  • BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH
  • BOARD_MODEL_NEAR_TLINE_LENGTH
  • BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH
  • BOARD_MODEL_TERMINATION_V
  • BOARD_MODEL_TLINE_C_PER_LENGTH
  • BOARD_MODEL_TLINE_LENGTH
  • BOARD_MODEL_TLINE_L_PER_LENGTH
  • BOOST_1_STEP
  • BOOST_2_STEP
  • BOOST_3_STEP
  • BOOST_4_STEP
  • BOOST_5_STEP
  • BOOST_6_STEP
  • BOOST_7_STEP
  • BOOST
  • BOOT_SEL_PIN
  • BOTH_EDGES
  • BREAKPOINT_FILE
  • BREAKPOINT
  • BREAKPOINT_LINE_NUMBER
  • BREAKPOINT_STATE
  • BSF_FILE
  • BW_FULL_12P5
  • BW_HALF_6P5
  • BYPASS_ERROR_RELEASE_CLEARS_BEFORE_TRISTATES_1S25
  • BYPASS
  • BYPASS_OFF
  • BYPASS_STAGES_234
  • BYTE_ORDER
  • BYYPASS_STAGES_234
  • C0H9
  • C0M9
  • C3_M9K_BIT_SKIP
  • CALIBRATED
  • CALIBRATED_SSTL
  • CAL_SIM_ACTIVATOR
  • CAP_NAME
  • CARE
  • CARRY_CHAIN_LENGTH_ARMSTRONG
  • CARRY_CHAIN_LENGTH_DALI
  • CARRY_CHAIN_LENGTH_FLEX10K
  • CARRY_CHAIN_LENGTH_FLEX6K
  • CARRY_CHAIN_LENGTH
  • CARRY_CHAIN_LENGTH_TSUNAMI
  • CARRY_CHAIN_LENGTH_YEAGER
  • CARRY_OUT_PINS_LCELL_INSERT
  • CASCADE_CHAIN_LENGTH
  • CASE_SENSITIVE
  • CAT_ASSEMBLER
  • CAT_ASSIGNMENT_GROUP
  • CAT_DESIGN_ASSISTANT
  • CAT_FITTER
  • CAT_INCREMENTAL_COMPILATION
  • CAT_LOCATION_PIN
  • CAT_LOGICLOCK
  • CAT_MAPPER_SYNTHESIS
  • CAT_NETO
  • CAT_PARAMETERS
  • CAT_POWER_ESTIMATION
  • CAT_PROGRAMMER
  • CAT_SIGNALPROBE
  • CAT_SIGNALTAP
  • CAT_SIMULATION
  • CAT_SOFTWARE_BUILDER
  • CAT_TIMEGROUP
  • CAT_TIMING_ANALYSIS
  • CAT_TIMING
  • CB_CLKUSR
  • CB_INTOSC
  • CDF_FILE
  • CDR_BANDWIDTH_PRESET
  • CEI_11100_LR
  • CEI_11100_SR
  • CEI_4976_LR
  • CEI_4976_SR
  • CEI_6375_LR
  • CEI_6375_SR
  • CEI_9950_LR
  • CEI_9950_SR
  • CE_OPTION
  • C_FILE
  • CHAIN_FILE
  • CHECK_AGAINST_TSM_DELAY
  • CHECK_OUTPUTS
  • CHIP
  • CHIP_WIDE_OE
  • CHIP_WIDE_RESET
  • CKN_CK_PAIR
  • CLAMPING_DIODE
  • CLIQUE
  • CLIQUE_TYPE_APEX20K
  • CLIQUE_TYPE_DALI
  • CLIQUE_TYPE_FLEX10K
  • CLIQUE_TYPE_FLEX6K
  • CLIQUE_TYPE
  • CLIQUE_TYPE_MAX7K
  • CLK_CAT
  • CLK_FPLL_VREG_BOOST_1_STEP
  • CLK_FPLL_VREG_BOOST_2_STEP
  • CLK_FPLL_VREG_BOOST_3_STEP
  • CLK_FPLL_VREG_BOOST_4_STEP
  • CLK_FPLL_VREG_BOOST_5_STEP
  • CLK_FPLL_VREG_BOOST_6_STEP
  • CLK_FPLL_VREG_BOOST_7_STEP
  • CLK_FPLL_VREG_NO_VOLTAGE_BOOST
  • CLKLOCKX1_INPUT_FREQ
  • CLK_RULE_ALL
  • CLK_RULE_CLKNET_CLKSPINES
  • CLK_RULE_CLKNET_CLKSPINES_THRESHOLD
  • CLK_RULE_COMB_CLOCK
  • CLK_RULE_GATED_CLK_FANOUT
  • CLK_RULE_GATING_SCHEME
  • CLK_RULE_INPINS_CLKNET
  • CLK_RULE_INV_CLOCK
  • CLK_RULE_MIX_EDGES
  • CLKUSR
  • CLOCK_ANALYSIS_ONLY
  • CLOCK_DIVISOR
  • CLOCK_ENABLE_MULTICYCLE_HOLD
  • CLOCK_ENABLE_MULTICYCLE
  • CLOCK_ENABLE_ROUTING
  • CLOCK_ENABLE_SOURCE_MULTICYCLE_HOLD
  • CLOCK_ENABLE_SOURCE_MULTICYCLE
  • CLOCK_FREQUENCY
  • CLOCK_HOLD_UNCERTAINTY
  • CLOCK
  • CLOCK_MAX_ROUTING
  • CLOCK_REGION
  • CLOCK_SETTINGS
  • CLOCK_SETUP_UNCERTAINTY
  • CLOCK_SOURCE
  • CLOCK_SPINE
  • CLOCK_TO_OUTPUT_DELAY
  • CLOUD_NOTIFY_COMPILE_ID
  • CLOUD_NOTIFY_ENABLE
  • CLOUD_NOTIFY_ENABLE_LOGGING
  • CLOUD_NOTIFY_GROUP_ID
  • CLOUD_NOTIFY_LOGGING
  • CLOUD_NOTIFY_PROXY
  • CLOUD_NOTIFY_SEND_CRIT_WARNINGS
  • CLOUD_NOTIFY_SEND_ERRORS
  • CLOUD_NOTIFY_SEND_JSON_REPORTS
  • CLOUD_NOTIFY_SERVER
  • CLOUD_NOTIFY_TOKEN
  • COMMAND_MACRO_FILE
  • COMMAND_MACRO_MODE
  • COMPANION_REVISION_NAME
  • COMPARED_CLOCK
  • COMPATIBLE_PLACEMENT_AND_ROUTING
  • COMPATIBLE_PLACEMENT
  • COMPILATION_LEVEL
  • COMPILE_NEW_PROJECT
  • COMPILER_ACTION_POINTS
  • COMPILER_ASSIGNMENT
  • COMPILER_CONFIGURED
  • COMPILER_SETTINGS
  • COMPILER_SETTINGS_LIST
  • COMPILER_SIGNATURE_ID
  • COMPRESSION_MODE
  • CONBINATION10
  • CONBINATION11
  • CONBINATION1
  • CONBINATION2
  • CONBINATION3
  • CONBINATION4
  • CONBINATION5
  • CONBINATION6
  • CONBINATION7
  • CONBINATION8
  • CONBINATION9
  • CONFIG_DEVICE_JTAG_USER_CODE_DALI
  • CONFIG_DEVICE_JTAG_USER_CODE_FLEX6K
  • CONFIG_DEVICE_JTAG_USER_CODE
  • CONFIGURATION_CLOCK_DIVISOR
  • CONFIGURATION_CLOCK_FREQUENCY
  • CONFIGURATION_DEVICE_DALI
  • CONFIGURATION_DEVICE_FLEX6K
  • CONFIGURATION_DEVICE
  • CONFIGURATION_PINS
  • CONFIGURATION_SCHEME_DALI
  • CONFIGURATION_SCHEME_FLEX6K
  • CONFIGURATION_SCHEME
  • CONFIGURATION_VCCIO_LEVEL
  • CONNECT_BIDIR_PIN_FROM_SLD_INCR_NODE_ENTITY_PORT
  • CONNECT_BIDIR_PIN_FROM_SLD_NODE_ENTITY_PORT
  • CONNECT_FROM_SLD_INCR_NODE_ENTITY_PORT
  • CONNECT_FROM_SLD_NODE_ENTITY_PORT
  • CONNECT_PIN_FROM_SLD_INCR_NODE_ENTITY_PORT
  • CONNECT_PIN_FROM_SLD_NODE_ENTITY_PORT
  • CONNECT_PIN_TO_SLD_INCR_NODE_ENTITY_PORT
  • CONNECT_PIN_TO_SLD_NODE_ENTITY_PORT
  • CONNECT_SIGNALPROBE_PIN
  • CONNECT_TO
  • CONNECT_TO_SLD_INCR_NODE_ENTITY_PORT
  • CONNECT_TO_SLD_NODE_ENTITY_PORT
  • CONTAINS_FAMILY_SPECIFIC_DATA
  • CONVERT_ALOAD_TO_CLEAR_PRESET
  • CONVERT_PR_WARNINGS_TO_ERRORS
  • COPY_IF_NODE_IS_DUPLICATED
  • COPY_VARIABLE_TYPE_IN_PIN_PLANNER
  • CORE_INITIALIZATION_AND_UPDATE
  • CORE_INITIALIZATION
  • CORE
  • CORE_ONLY_PLACE_REGION
  • CORE_UPDATE
  • COVERAGE_COMPLETE_PANEL_ENABLED
  • COVERAGE
  • COVERAGE_MISSING_0_VALUE_PANEL_ENABLED
  • COVERAGE_MISSING_1_VALUE_PANEL_ENABLED
  • CPH9
  • CPP_FILE
  • CPP_INCLUDE_FILE
  • CPRI_12500
  • CPRI_E12HV
  • CPRI_E12LVIII
  • CPRI_E12LVII
  • CPRI_E12LV
  • CPRI_E24LVIII
  • CPRI_E24LVII
  • CPRI_E24LV
  • CPRI_E30LVIII
  • CPRI_E30LVII
  • CPRI_E30LV
  • CPRI_E48LVIII
  • CPRI_E48LVII
  • CPRI_E60LVIII
  • CPRI_E60LVII
  • CPRI_E6HV
  • CPRI_E6LVIII
  • CPRI_E6LVII
  • CPRI_E6LV
  • CPRI_E96LVIII
  • CPRI_E99LVIII
  • CPRI
  • CRC_ERROR_CHECKING
  • CRC_ERROR_CHECKING_YEAGER
  • CRC_ERROR_OPEN_DRAIN
  • CREATED_BY
  • CREATED_FROM
  • CREATE_PARTITION_BOUNDARY_PORTS
  • CREATE_SIGNALPROBE_PIN
  • CRITICAL_CHAIN_VIEWER
  • CROSS_BOUNDARY_OPTIMIZATIONS
  • CURRENT_STRENGTH
  • CURRENT_STRENGTH_NEW
  • CUSP_FILE
  • CUSTOM_BUILD_COMMAND_LINE
  • CUSTOM_CLOCK_TREE
  • CUT_OFF_CLEAR_AND_PRESET_PATHS
  • CUT_OFF_IO_PIN_FEEDBACK
  • CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS
  • CUT_OFF_READ_DURING_WRITE_PATH
  • CUT_OFF_READ_DURING_WRITE_PATHS
  • CVPCIE_CONFDONE_OPEN_DRAIN
  • CVPCIE_MODE
  • CVP_CONFDONE_OPEN_DRAIN
  • CVP_MODE
  • CVP_REVISION
  • CVWF
  • CYCLONE_CONFIGURATION_DEVICE
  • CYCLONE_CONFIGURATION_SCHEME
  • CYCLONEII_CONFIGURATION_SCHEME
  • CYCLONEIII_CONFIGURATION_DEVICE
  • CYCLONEIII_CONFIGURATION_SCHEME
  • CYCLONEII_M4K_COMPATIBILITY
  • CYCLONEII_OPTIMIZATION_TECHNIQUE
  • CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION
  • CYCLONEII_TERMINATION
  • CYCLONE_OPTIMIZATION_TECHNIQUE
  • D1_DELAY
  • D1_FINE_DELAY
  • D2_DELAY
  • D3_DELAY
  • D4_DELAY
  • D4_FINE_DELAY
  • D5_DELAY
  • D5_FINE_DELAY
  • D5_OCT_DELAY
  • D5_OE_DELAY
  • D6_DELAY
  • D6_FINE_DELAY
  • D6_OCT_DELAY
  • D6_OE_DELAY
  • D6_OE_FINE_DELAY
  • DA_CUSTOM_RULE_FILE
  • DANGEROUS_EXCEPTION_FOR_READ_ONLY_CONTACT_INFRASTRUCTURE_GROUP
  • DATA0_PIN
  • DATA0_RESERVED
  • DATA15_8_RESERVED
  • DATA1_RESERVED
  • DATA31_16_RESERVED
  • DATA7_1_RESERVED
  • DATA7_2_RESERVED
  • DATA7_5_RESERVED
  • DC_COUPLING_EXTERNAL_RESISTOR
  • DC_COUPLING_EXTERNAL_TERMINATION
  • DC_COUPLING_INTERNAL_100_OHMS
  • DC_CURRENT_FOR_ELECTROMIGRATION_CHECK
  • DCLK
  • DCLK_PIN
  • DCLK_RESERVED
  • DDIO_INPUT_REGISTER
  • DDIO_OUTPUT_REGISTER_DISTANCE
  • DDIO_OUTPUT_REGISTER
  • DEBUG_BOUNDARY
  • DEBUG_TRACE
  • DECREASE_INPUT_DELAY_TO_INPUT_REGISTER
  • DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
  • DECREASE_INPUT_DELAY_TO_OUTPUT_REGISTER
  • DEFAULT_DESIGN_ASSISTANT_SETTINGS
  • DEFAULT_DEVICE_OPTIONS
  • DEFAULT_EQUIVALENCE_CHECKER_SETTINGS
  • DEFAULT_HARDCOPY_SETTINGS
  • DEFAULT_HOLD_MULTICYCLE
  • DEFAULT
  • DEFAULT_LOGIC_OPTIONS
  • DEFAULT_NETLIST_VIEWER_SETTINGS
  • DEFAULT_PARAMETERS
  • DEFAULT_SDC_FILE
  • DEFAULT_TIMING_REQUIREMENTS
  • DEFAULT_VALUE
  • DELAY_MATCH_RELATED_CLOCKS
  • DELAY_SETTING_FROM_CORE_TO_CE_INPUT_REGISTER
  • DELAY_SETTING_FROM_CORE_TO_CE_IO_REGISTER
  • DELAY_SETTING_FROM_CORE_TO_CE_OE_REGISTER
  • DELAY_SETTING_FROM_CORE_TO_CE_OUTPUT_REGISTER
  • DELAY_SETTING_FROM_CORE_TO_OUTPUT_REGISTER
  • DELAY_SETTING_FROM_VIO_TO_CORE
  • DELAY_SETTING_TO_CORE_APEX20K
  • DELAY_SETTING_TO_CORE_DALI
  • DELAY_SETTING_TO_CORE_FLEX10K
  • DELAY_SETTING_TO_CORE_FLEX6K
  • DELAY_SETTING_TO_CORE_TO_OUTPUT_REGISTER
  • DELAY_SETTING_TO_CORE_TSUNAMI
  • DELAY_SETTING_TO_CORE_YEAGER
  • DELAY_SETTING_TO_INPUT_REGISTER
  • DELAY_SETTING_TO_OUTPUT_ENABLE
  • DELAY_SETTING_TO_OUTPUT
  • DELAY_SETTING_TO_ZBT
  • DEPENDENCY_FILE
  • DESIGN_ASISTANT_INCLUDE_IP_BLOCKS
  • DESIGN_ASSISTANT_ASSIGNMENT
  • DESIGN_ASSISTANT_INCLUDE_IP_BLOCKS
  • DESIGN_ASSISTANT_MAX_VIOLATIONS_PER_RULE
  • DESIGN_HASH
  • DESIGN_PARTITION
  • DEV_FAMILY_ACEX1K
  • DEV_FAMILY_APEX20KC
  • DEV_FAMILY_APEX20KE
  • DEV_FAMILY_APEX20K
  • DEV_FAMILY_APEXII
  • DEV_FAMILY_ARMSTRONG
  • DEV_FAMILY_ARRIAIIGZ
  • DEV_FAMILY_ARRIAVGZ
  • DEV_FAMILY_ARRIAV
  • DEV_FAMILY_ASC
  • DEV_FAMILY_AURORA
  • DEV_FAMILY_BEDROCK
  • DEV_FAMILY_BS
  • DEV_FAMILY_CUDA
  • DEV_FAMILY_CYCLONE10GX
  • DEV_FAMILY_CYCLONE10LP
  • DEV_FAMILY_CYCLONEII
  • DEV_FAMILY_CYCLONEIVE
  • DEV_FAMILY_CYCLONEV
  • DEV_FAMILY_DALI
  • DEV_FAMILY_EMBEDDED_PROCESSOR
  • DEV_FAMILY_EPC1
  • DEV_FAMILY_EPC2
  • DEV_FAMILY_EXCALIBUR_ARM
  • DEV_FAMILY_FALCONMESA_EMULATOR
  • DEV_FAMILY_FALCONMESA
  • DEV_FAMILY_FLASH_LOGIC
  • DEV_FAMILY_FLEX10KA
  • DEV_FAMILY_FLEX10KB
  • DEV_FAMILY_FLEX10KE
  • DEV_FAMILY_FLEX10K
  • DEV_FAMILY_FLEX6K
  • DEV_FAMILY_FLEX8000
  • DEV_FAMILY_FUSION
  • DEV_FAMILY_HCXIV
  • DEV_FAMILY_HCX
  • DEV_FAMILY_INTEL_CFI
  • DEV_FAMILY_MAX3000A
  • DEV_FAMILY_MAX7000AE
  • DEV_FAMILY_MAX7000A
  • DEV_FAMILY_MAX7000B
  • DEV_FAMILY_MAX7000S
  • DEV_FAMILY_MAX9000
  • DEV_FAMILY_MAXV
  • DEV_FAMILY_NADDER_EMULATOR
  • DEV_FAMILY_NADDER
  • DEV_FAMILY_NIGHTFURY
  • DEV_FAMILY_PGM_DUMMY_FAMILY
  • DEV_FAMILY_PGM_EOL_FAMILY
  • DEV_FAMILY_PIRANHA
  • DEV_FAMILY_SOC_HPS
  • DEV_FAMILY_STINGRAY
  • DEV_FAMILY_STRATIXHC
  • DEV_FAMILY_STRATIXIIGX
  • DEV_FAMILY_STRATIXIIGXLITE
  • DEV_FAMILY_STRATIXV
  • DEV_FAMILY_SYN
  • DEV_FAMILY_TARPON
  • DEV_FAMILY_TGX
  • DEV_FAMILY_TITAN
  • DEV_FAMILY_TORNADO
  • DEV_FAMILY_TSUNAMI
  • DEV_FAMILY_VERMEER
  • DEV_FAMILY_VIRTUAL_JTAG_TAP
  • DEV_FAMILY_YEAGER
  • DEV_FAMILY_ZIPPLEBACK
  • DEVICE_FILTER_PACKAGE
  • DEVICE_FILTER_PIN_COUNT
  • DEVICE_FILTER_SPEED_GRADE
  • DEVICE_FILTER_VOLTAGE
  • DEVICE_INITIALIZATION_CLOCK
  • DEVICE_IO_STANDARD_APEX20KE
  • DEVICE_IO_STANDARD_APEX20KF
  • DEVICE_IO_STANDARD_APEX20K
  • DEVICE_IO_STANDARD_DALI
  • DEVICE_IO_STANDARD_FLEX10K
  • DEVICE_IO_STANDARD_FLEX6K
  • DEVICE_IO_STANDARD
  • DEVICE_IO_STANDARD_MAX7000
  • DEVICE_IO_STANDARD_YEAGER
  • DEVICE
  • DEVICE_MIGRATION_LIST
  • DEVICE_TECHNOLOGY_MIGRATION_LIST
  • DEV_PART_GENERIC
  • DEV_PART_INVALID
  • DEV_PART_MAX
  • DFE_PI_BW_0P5GHZ
  • DFE_PI_BW_10GHZ
  • DFE_PI_BW_2P5GHZ
  • DFE_PI_BW_5GHZ
  • DIFFERENTIAL
  • DIRECT_FORMAT
  • DIRECT
  • DISABLE_CONF_DONE_AND_NSTATUS_ON_EPROM
  • DISABLE_CONF_DONE_AND_NSTATUS_PULLUPS_ON_CONFIG_DEVICE
  • DISABLE_CORE_CLK
  • DISABLE_DA_GX_RULE
  • DISABLE_DA_RULE
  • DISABLED
  • DISABLE_DSP_NEGATE_INFERENCING
  • DISABLE_EMBEDDED_TIMING_CONSTRAINT
  • DISABLE
  • DISABLE_MLAB_RAM_USE
  • DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE
  • DISABLE_OCP_HW_EVAL
  • DISABLE_PLL_COMPENSATION_DELAY_CHANGE_WARNING
  • DISABLE_REGION_HIERARCHY
  • DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES
  • DISABLE_REGISTER_POWERUP_INITIALIZATION
  • DISABLE_TRI
  • DISALLOW_GLOBAL_ASSIGNMENT_IN_QIP
  • DIV2
  • DIV4
  • DIVIDE_BASE_CLOCK_BY
  • DIVIDE_BASE_CLOCK_PERIOD_BY
  • DM_PIN
  • DO_COMBINED_ANALYSIS
  • DO_MIN_ANALYSIS
  • DO_MINMAX_ANALYSIS_USING_RISEFALL_DELAYS
  • DO_MIN_TIMING
  • DONE
  • DONT_AUTODISCOVER_CPP_FILES
  • DONT_CARE
  • DONT_CONVERT_TO_USER_FRIENDLY_STRING
  • DONT_COPY_TO_CREATED_COMPANION_REVISION
  • DONT_COPY_TO_NEW_FILE_FORMAT
  • DONT_COPY_TO_NEW_REVISION
  • DONT_MERGE_REGISTER
  • DONT_REUSE_REMOVED_ASSIGNMENT
  • DONT_TOUCH_USER_CELL
  • DO_POST_BUILD_COMMAND_LINE
  • DO_SYSTEM_FMAX
  • DOWN
  • DP_1620
  • DP_2700
  • DP_5400
  • DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1
  • DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1
  • DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1
  • DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1
  • DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1
  • DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1
  • DPRAM_DEEP_MODE_INPUT_EPXA4_10
  • DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10
  • DPRAM_DEEP_MODE_OUTPUT_EPXA4_10
  • DPRAM_DUAL_PORT_MODE_INPUT_EPXA1
  • DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10
  • DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1
  • DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10
  • DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1
  • DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10
  • DPRAM_INPUT_EPXA4_10
  • DPRAM_OTHER_SIGNALS_EPXA4_10
  • DPRAM_OUTPUT_EPXA4_10
  • DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10
  • DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10
  • DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10
  • DPRAM_WIDE_MODE_INPUT_EPXA4_10
  • DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10
  • DPRAM_WIDE_MODE_OUTPUT_EPXA4_10
  • DPRIO_CHANNEL_NUM
  • DPRIO_CRUCLK_NUM
  • DPRIO_INTERFACE_REG
  • DPRIO_NORMAL_STATUS
  • DPRIO_QUAD_NUM
  • DPRIO_QUAD_PLL_NUM
  • DPRIO_TX_PLL0_REFCLK_NUM
  • DPRIO_TX_PLL1_REFCLK_NUM
  • DPRIO_TX_PLL_NUM
  • DQ_GROUP
  • DQ_PIN
  • DQSB_DQS_PAIR
  • DQS_DELAY
  • DQS_ENABLE_DELAY_CHAIN
  • DQS_FREQUENCY
  • DQS_LOCAL_CLOCK_DELAY_CHAIN
  • DQSOUT_DELAY_CHAIN
  • DQS_SHIFT
  • DQS_SYSTEM_CLOCK
  • DRC_DEADLOCK_STATE_LIMIT
  • DRC_DETAIL_MESSAGE_LIMIT
  • DRC_FANOUT_EXCEEDING
  • DRC_GATED_CLOCK_FEED
  • DRC_MAX_TOP_FANOUT
  • DRC_REPORT_FANOUT_EXCEEDING
  • DRC_REPORT_MAX_TOP_FANOUT
  • DRC_REPORT_TOP_FANOUT
  • DRC_TOP_FANOUT
  • DRC_VIOLATION_MESSAGE_LIMIT
  • DSE_SEND_REPORT_PANEL
  • DSE_SERVER_SEND_REPORTS
  • DSE_SERVER_URL
  • DSE_SYNTH_EXTRA_EFFORT_MODE
  • DSE_WORKER_ID
  • DSM_DFT_OUT
  • DSM_LSB_OUT
  • DSM_MSB_OUT
  • DSP_BLOCK_BALANCING_IMPLEMENTATION
  • DSP_BLOCK_BALANCING
  • DSP_BLOCKS
  • DSPBUILDER_FILE
  • DSP_REGISTER_PACKING
  • DUAL_FAST_REGIONAL_CLOCK
  • DUAL_IMAGES
  • DUAL_PURPOSE_CLOCK_PIN_DELAY
  • DUAL_REGIONAL_CLOCK
  • DUPLICATE_ATOM
  • DUPLICATE_HIERARCHY_DEPTH
  • DUPLICATE_LOGIC_EXTRACTION
  • DUPLICATE_REGISTER_EXTRACTION
  • DUPLICATE_REGISTER
  • DUP_LOGIC_EXTRACTION
  • DUP_REG_EXTRACTION
  • DUTY_CYCLE
  • DYNAMIC_ATOM_CONNECTION
  • DYNAMIC_CTL
  • DYNAMIC_OCT_CONTROL_GROUP
  • EARLY_CLOCK_LATENCY
  • ECO_ALLOW_ROUTING_CHANGES
  • ECO_OPTIMIZE_TIMING
  • ECO_REGENERATE_REPORT
  • ECO_TIMING_DRIVEN_COMPILE
  • EDA_BOARD_BOUNDARY_SCAN_OPERATION
  • EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL
  • EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL
  • EDA_BOARD_DESIGN_SYMBOL_TOOL
  • EDA_BOARD_DESIGN_TIMING_TOOL
  • EDA_BOARD_DESIGN_TOOL
  • EDA_COPY_TO_SNAPSHOT
  • EDA_DATA_FORMAT
  • EDA_DESIGN_ENTRY_SYNTHESIS_TOOL
  • EDA_DESIGN_EXTRA_ALTERA_SIM_LIB
  • EDA_DESIGN_INSTANCE_NAME
  • EDA_ENABLE_GLITCH_FILTERING
  • EDA_ENABLE_IPUTF_MODE
  • EDA_ENABLE_OCV_TIMING_ANALYSIS
  • EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE
  • EDA_EXCALIBUR_SINGLE_SLICE
  • EDA_EXTRA_ELAB_OPTION
  • EDA_FLATTEN_BUSES
  • EDA_FORMAL_VERIFICATION_ALLOW_RETIMING
  • EDA_FORMAL_VERIFICATION_TOOL
  • EDA_FV_HIERARCHY
  • EDA_GENERATE_FUNCTIONAL_NETLIST
  • EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT
  • EDA_GENERATE_POWER_INPUT_FILE
  • EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT
  • EDA_GENERATE_SDF_FOR_POWER
  • EDA_GENERATE_SDF_OUTPUT_FILE
  • EDA_GENERATE_TIMING_CLOSURE_DATA
  • EDA_IBIS_EXTENDED_MODEL_SELECTOR
  • EDA_IBIS_MODEL_SELECTOR
  • EDA_IBIS_MUTUAL_COUPLING
  • EDA_IBIS_SPECIFICATION_VERSION
  • EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION
  • EDA_INPUT_DATA_FORMAT
  • EDA_INPUT_GND
  • EDA_INPUT_GND_NAME
  • EDA_INPUT_VCC
  • EDA_INPUT_VCC_NAME
  • EDA_IPFS_FILE
  • EDA_LAUNCH_CMD_LINE_TOOL
  • EDA_LAUNCH_TOOL
  • EDA_LMF_FILE
  • EDA_MAINTAIN_DESIGN_HIERARCHY
  • EDA_MAP_ILLEGAL_CHARACTERS
  • EDA_MAP_ILLEGAL
  • EDA_NATIVELINK_GENERATE_SCRIPT_ONLY
  • EDA_NATIVELINK_PORTABLE_FILE_PATHS
  • EDA_NATIVELINK_SIMULATION_SETUP_SCRIPT
  • EDA_NATIVELINK_SIMULATION_TEST_BENCH
  • EDA_NETLIST_TYPE
  • EDA_NETLIST_WRITER_OUTPUT_DIR
  • EDA_OCV_CORE_DERATING_FACTOR
  • EDA_OCV_IO_DERATING_FACTOR
  • EDA_OUTPUT_DATA_FORMAT
  • EDA_RESYNTHESIS_TOOL
  • EDA_RTL_SIM_MODE
  • EDA_RTL_SIMULATION_RUN_SCRIPT
  • EDA_RTL_TEST_BENCH_FILE_NAME
  • EDA_RTL_TEST_BENCH_NAME
  • EDA_RTL_TEST_BENCH_RUN_FOR
  • EDA_RUN_TOOL_AUTOMATICALLY
  • EDA_SDC_FILE_NAME
  • EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED
  • EDA_SHOW_LMF_MAPPING_MESSAGES
  • EDA_SHOW_LMF_MAPPING_MSGS
  • EDA_SIMULATION_RUN_SCRIPT
  • EDA_SIMULATION_TOOL
  • EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE
  • EDA_SIMULATION_VCD_OUTPUT_TCL_FILE
  • EDA_SIMULATION_VCD_OUTPUT_TCL_FILE_NAME
  • EDA_TEST_BENCH_DESIGN_INSTANCE_NAME
  • EDA_TEST_BENCH_ENABLE_STATUS
  • EDA_TEST_BENCH_ENTITY_MODULE_NAME
  • EDA_TEST_BENCH_EXTRA_ALTERA_SIM_LIB
  • EDA_TEST_BENCH_FILE
  • EDA_TEST_BENCH_FILE_NAME
  • EDA_TEST_BENCH_GATE_LEVEL_NETLIST_LIBRARY
  • EDA_TEST_BENCH_MODULE_NAME
  • EDA_TEST_BENCH_NAME
  • EDA_TEST_BENCH_RUN_FOR
  • EDA_TEST_BENCH_RUN_SIM_FOR
  • EDA_TEST_BENCH_SETTINGS
  • EDA_TIME_SCALE
  • EDA_TIMESCALE
  • EDA_TIMING_ANALYSIS_TOOL
  • EDA_TOOL_SETTINGS
  • EDA_TRUNCATE_HPATH
  • EDA_TRUNCATE_LONG_HIERARCHY_PATHS
  • EDA_USE_IBIS_RLC_TYPE
  • EDA_USE_LMF
  • EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY
  • EDA_USE_RISE_FALL_DELAYS
  • EDA_VHDL_ARCH_NAME
  • EDA_VHDL_LIBRARY
  • EDA_WAIT_FOR_GUI_TOOL_COMPLETION
  • EDA_WRITE_CONFIG
  • EDA_WRITE_DEVICE_CONTROL_PORTS
  • EDA_WRITE_NODES_FOR_POWER_ESTIMATION
  • EDA_WRITER_DONT_WRITE_TOP_ENTITY
  • EDIF_FILE
  • ELA_FILE
  • ELEMENT_INDEX
  • ELF_FILE
  • EMBEDDED_PROCESSOR
  • EMIF_SOC_PHYCLK_ADVANCE_MODELING
  • EMPTY
  • EMPTY_PLACE_REGION
  • EMU_REPLICATE_SIGNAL_PER_SECTOR
  • ENABLE_ACCELERATED_INCREMENTAL_COMPILE
  • ENABLE_ADVANCED_IO_DELAY_CHAIN_OPTIMIZATION
  • ENABLE_ADV_SEU_DETECTION
  • ENABLE_ALT2GXB_CONFIGURATION
  • ENABLE_APEX_FITTER_CHOICE
  • ENABLE_ASMI_FOR_FLASH_LOADER
  • ENABLE_ASM_OPTIONS_FILE
  • ENABLE_ATTEMPT_SIMILAR_PLACEMENT
  • ENABLE_AUTONOMOUS_PCIE_HIP
  • ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS
  • ENABLE_BENEFICIAL_SKEW_OPTIMIZATION
  • ENABLE_BOOT_SEL_PIN
  • ENABLE_BUS_HOLD_CIRCUITRY
  • ENABLE_BUS_HOLD
  • ENABLE_CHIP_WIDE_OE
  • ENABLE_CHIP_WIDE_RESET
  • ENABLE_CLOCK_LATENCY
  • ENABLE_COMPACT_REPORT_TABLE
  • ENABLE_CONFIGURATION_PINS
  • ENABLE_CORE_CLK
  • ENABLE_CRC_ERROR_PIN
  • ENABLE_CVPCIE_CONFDONE
  • ENABLE_CVP_CONFDONE
  • ENABLE_DA_RULE
  • ENABLE_DEVICE_WIDE_OE
  • ENABLE_DEVICE_WIDE_RESET
  • ENABLE_DISABLED_STRATIX_LVDS_MODES
  • ENABLED
  • ENABLE_DRC
  • ENABLE_DRC_SETTINGS
  • ENABLE_ED_CRC_CHECK
  • ENABLE_EXTRA_DQ_DELAY
  • ENABLE_FALLBACK_TO_EXTERNAL_FLASH
  • ENABLE_FORMAL_VERIFICATION
  • ENABLE_HOLD_BACK_OFF
  • ENABLE_HOLD_MULTICYCLE
  • ENABLE_HPS_INTERNAL_TIMING
  • ENABLE_INCREMENTAL_DESIGN
  • ENABLE_INCREMENTAL_REUSE
  • ENABLE_INCREMENTAL_SYNTHESIS
  • ENABLE_INIT_DONE_OUTPUT
  • ENABLE_INTERMEDIATE_SNAPSHOTS
  • ENABLE_IP_DEBUG
  • ENABLE_JTAG_BST_SUPPORT
  • ENABLE_JTAG_PIN_SHARING
  • ENABLE_LAB_SHARING_WITH_PARENT_PARTITION
  • ENABLE
  • ENABLE_LLIS
  • ENABLE_LOGIC_ANALYZER_INTERFACE
  • ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE
  • ENABLE_LOW_VOLT_MODE_FLEX10K
  • ENABLE_LOW_VOLT_MODE_FLEX6K
  • ENABLE_LOW_VOLT_MODE
  • ENABLE_M512
  • ENABLE_MERCURY_CDR
  • ENABLE_MIXED_PORT_RDW_OLD_DATA_FOR_RAM_WITH_TWO_CLOCKS
  • ENABLE_MULTICYCLE_HOLD
  • ENABLE_MULTICYCLE
  • ENABLE_MULTITAP
  • ENABLE_NCEO_OUTPUT
  • ENABLE_NCE_PIN
  • ENABLE_NCONFIG_FROM_CORE
  • ENABLE_NO_HIPI_INITIALIZATION_FLOW
  • ENABLE_OCT_DONE
  • ENABLE_OCTDONE
  • ENABLE_PHYSICAL_DSP_MERGING
  • ENABLE_PR_PINS
  • ENABLE_PR_POF_ID
  • ENABLE_RAPID_RECOMPILE
  • ENABLE_RECOVERY_REMOVAL_ANALYSIS
  • ENABLE_REDUCED_MEMORY_MODE
  • ENABLE_SIGNALTAP
  • ENABLE_SMART_VOLTAGE_ID
  • ENABLE_SOURCE_MULTICYCLE_HOLD
  • ENABLE_SOURCE_MULTICYCLE
  • ENABLE_SPI_MODE_CHECK
  • ENABLE_SRC_HOLD_MULTICYCLE
  • ENABLE_SRC_MULTICYCLE
  • ENABLE_STATE_MACHINE_INFERENCE
  • ENABLE_STRATIX_II_DPA_DEBUG
  • ENABLE_STRATIXII_DPA_DEBUG
  • ENABLE_STRATIX_II_LVDS_LOOPBACK
  • ENABLE_STRATIXII_LVDS_LOOPBACK
  • ENABLE_STRICT_PRESERVATION
  • ENABLE_SYNCH_INPUT_REGISTER_1S25
  • ENABLE_TRI
  • ENABLE_UNUSED_RX_CLOCK_WORKAROUND
  • ENABLE_VREFA_PIN
  • ENABLE_VREFB_PIN
  • ENCRYPTED_LUTMASK
  • ENCRYPT_PROGRAMMING_BITSTREAM
  • END_TIME
  • ENFORCE_CONFIGURATION_VCCIO
  • EN_SPI_IO_WEAK_PULLUP
  • ENTITY_REBINDING
  • EN_USER_IO_WEAK_PULLUP
  • EPC1
  • EPC2
  • EPROM_JTAG_CODE_APEX20K
  • EPROM_JTAG_CODE_DALI
  • EPROM_JTAG_CODE_FLEX10K
  • EPROM_JTAG_CODE_FLEX6K
  • EPROM_JTAG_CODE
  • EPROM_JTAG_CODE_YEAGER
  • EPROM_USE_CHECKSUM_AS_USERCODE
  • EQ_BW_1
  • EQ_BW_2
  • EQ_BW_3
  • EQ_BW_4
  • EQC_AUTO_BREAK_CONE
  • EQC_AUTO_COMP_LOOP_CUT
  • EQC_AUTO_INVERSION
  • EQC_AUTO_PORTSWAP
  • EQC_AUTO_TERMINATE
  • EQC_BBOX_MERGE
  • EQC_CONSTANT_DFF_DETECTION
  • EQC_DETECT_DONT_CARES
  • EQC_DFF_SS_EMULATION
  • EQC_DUPLICATE_DFF_DETECTION
  • EQC_ENUM_AUTO_BREAK_CONE
  • EQC_ENUM_AUTO_COMP_LOOP_CUT
  • EQC_ENUM_AUTO_INVERSION
  • EQC_ENUM_AUTO_PORTSWAP
  • EQC_ENUM_AUTO_TERMINATE
  • EQC_ENUM_BBOX_MERGE
  • EQC_ENUM_CONSTANT_DFF_DETECTION
  • EQC_ENUM_DETECT_DONT_CARES
  • EQC_ENUM_DFF_SS_EMULATION
  • EQC_ENUM_DUPLICATE_DFF_DETECTION
  • EQC_ENUM_IO_BUFFER_CONVERSION
  • EQC_ENUM_LVDS_MERGE
  • EQC_ENUM_MAC_REGISTER_UNPACK
  • EQC_ENUM_MANUAL_MAP_LIST
  • EQC_ENUM_MAX_BDD_NODES
  • EQC_ENUM_PARAMETER_CHECK
  • EQC_ENUM_POWER_UP_COMPARE
  • EQC_ENUM_RAM_REGISTER_UNPACK
  • EQC_ENUM_RAM_UNMERGING
  • EQC_ENUM_RENAMING_RULES
  • EQC_ENUM_RENAMING_RULES_LIST
  • EQC_ENUM_SET_PARTITION_BB_TO_VCC_GND
  • EQC_ENUM_SHOW_ALL_MAPPED_POINTS
  • EQC_ENUM_STRUCTURE_MATCHING
  • EQC_ENUM_SUB_CONE_REPORT
  • EQC_LVDS_MERGE
  • EQC_MAC_REGISTER_UNPACK
  • EQC_PARAMETER_CHECK
  • EQC_POWER_UP_COMPARE
  • EQC_RAM_REGISTER_UNPACK
  • EQC_RAM_UNMERGING
  • EQC_RENAMING_RULES
  • EQC_RENAMING_RULES_LIST
  • EQC_SET_PARTITION_BB_TO_VCC_GND
  • EQC_SHOW_ALL_MAPPED_POINTS
  • EQC_STRUCTURE_MATCHING
  • EQC_SUB_CONE_REPORT
  • EQUATION_FILE
  • EQUIVALENCE_CHECKER_ASSIGNMENT
  • EQZP_DIS_PEAKING
  • EQZP_EN_PEAKING
  • ERROR_CHECK_FREQUENCY_DIVISOR
  • ESTIMATE_POWER_CONSUMPTION
  • EXCALIBUR_ARM
  • EXCALIBUR_CONFIGURATION_DEVICE
  • EXCALIBUR_CONFIGURATION_SCHEME
  • EXC_BUSTRANS_SIM_FILE
  • EXCLUDE_FMAX_PATHS_GREATER_THAN
  • EXCLUDE_SLACK_PATHS_GREATER_THAN
  • EXCLUDE_TCO_PATHS_LESS_THAN
  • EXCLUDE_TH_PATHS_LESS_THAN
  • EXCLUDE_TPD_PATHS_LESS_THAN
  • EXCLUDE_TSU_PATHS_LESS_THAN
  • EXCLUSIVE_IO_GROUP
  • EXI9
  • EXPANDED
  • EXPORT_BLOCK_NAME_OBFUSCATION
  • EXPORT_PARTITION_SNAPSHOT_FINAL
  • EXPORT_PARTITION_SNAPSHOT_SYNTHESIZED
  • EXTENDS_TOP_BLOCK
  • EXTERNAL_FEEDBACK
  • EXTERNAL_FLASH_FALLBACK_ADDRESS
  • EXTERNAL_INPUT_DELAY
  • EXTERNAL
  • EXTERNAL_LVDS_RX_USES_DPA
  • EXTERNAL_OUTPUT_DELAY
  • EXTERNAL_PIN_CONNECTION
  • EXTERNAL_RESISTOR
  • EXTRACT_AND_OPTIMIZE_BUS_MUXES
  • EXTRACT_VERILOG_STATE_MACHINES
  • EXTRACT_VHDL_STATE_MACHINES
  • EXTRA_EFFORT
  • EYEQ_BW_1G_TO_2P5G
  • EYEQ_BW_2P5G_TO_7P5G
  • EYEQ_BW_GREATER_THAN_7P5G
  • EYEQ_BW_LESS_THAN_1G
  • F10K_ACEX1K_PCI_LOW_CAP
  • FALLBACK_TO_EXTERNAL_FLASH
  • FALL
  • FALSE
  • FAMILY
  • FANIN_PER_CELL_MAX7000
  • FAP_NAME
  • FAR_END
  • FAR_GLOBAL_CLOCK
  • FAR_REGIONAL_CLOCK
  • FAST_FIT_COMPILATION
  • FAST_FIT
  • FAST_INPUT_REGISTER
  • FAST_IO
  • FAST
  • FAST_OCT_REGISTER
  • FAST_OPENCL_COMPILE
  • FAST_OUTPUT_ENABLE_REGISTER
  • FAST_OUTPUT_REGISTER
  • FAST_PASSIVE_PARALLEL
  • FAST_POR_DELAY
  • FAST_PRESERVE
  • FAST_REGIONAL_CLOCK
  • FASTROW_INTERCONNECT
  • FAST_VIO
  • FBCLK_COUNTER_OUT
  • FFFFFFFF
  • FFFF
  • FILES
  • FILTER_PACKAGE
  • FILTER_PIN_COUNT
  • FILTER_SPEED_GRADE
  • FILTER_VOLTAGE
  • FINAL_PLACEMENT_OPTIMIZATION
  • FIR_POST_1T_NEG
  • FIR_POST_1T_POS
  • FIR_POST_2T_NEG
  • FIR_POST_2T_POS
  • FIR_PRE_1T_NEG
  • FIR_PRE_1T_POS
  • FIR_PRE_2T_NEG
  • FIR_PRE_2T_POS
  • FIT_ATTEMPTS_TO_SKIP
  • FIT_FAST_FORWARD
  • FIT_FINALIZE
  • FIT_INI_VARS
  • FIT_ONLY_ONE_ATTEMPT
  • FIT_PLACE
  • FIT_PLAN
  • FIT_ROUTE
  • FIT_SCRIPT_FILE
  • FIT_SEED
  • FIT_SMART_IO
  • FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND
  • FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION
  • FITTER_ASSIGNMENT
  • FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN
  • FITTER_EARLY_RETIMING
  • FITTER_EARLY_TIMING_ESTIMATE_MODE
  • FITTER_EFFORT
  • FITTER_OPTIMIZED
  • FITTER_PACK_AGGRESSIVE_ROUTABILITY
  • FITTER_PLL_SCAN_CHAIN_RECONFIG_FILE
  • FITTER_RESYNTHESIS
  • FITTER_TCL_CALLBACK_FILE
  • FITTER_TYPE
  • FITTER_WILDARDS
  • FITTER_WILDCARDS
  • FIT_WYSIWYG_PIA
  • FLASH_NCE_RESERVED
  • FLASH_PROGRAMMING_FILE_NAME
  • FLEX10KA
  • FLEX10KB
  • FLEX10K_CARRY_CHAIN_LENGTH
  • FLEX10K_CLIQUE_TYPE
  • FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE
  • FLEX10K_CONFIGURATION_DEVICE
  • FLEX10K_CONFIGURATION_SCHEME
  • FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
  • FLEX10K_DEVICE_IO_STANDARD
  • FLEX10KE
  • FLEX10K_ENABLE_LOCK_OUTPUT
  • FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE
  • FLEX10KE_PCI_LOW_CAP_ADJUST
  • FLEX10K_JTAG_USER_CODE
  • FLEX10K
  • FLEX10K_MAX_PERIPHERAL_OE
  • FLEX10K_OPTIMIZATION_TECHNIQUE
  • FLEX10K_TECHNOLOGY_MAPPER
  • FLEX6000
  • FLEX6K_CARRY_CHAIN_LENGTH
  • FLEX6K_CLIQUE_TYPE
  • FLEX6K_CONFIG_DEVICE_JTAG_USER_CODE
  • FLEX6K_CONFIGURATION_DEVICE
  • FLEX6K_CONFIGURATION_SCHEME
  • FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
  • FLEX6K_DEVICE_IO_STANDARD
  • FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE
  • FLEX6K_JTAG_USER_CODE
  • FLEX6K_LOCAL_ROUTING_DESTINATION
  • FLEX6K_LOCAL_ROUTING_SOURCE
  • FLEX6K_OPTIMIZATION_TECHNIQUE
  • FLEX6K_TECHNOLOGY_MAPPER
  • FLEX8000
  • FLEXIBLE_TIMING
  • FLOATING
  • FLOATING_REGION
  • FLOW_DISABLE_ASSEMBLER
  • FLOW_ENABLE_DESIGN_ASSISTANT
  • FLOW_ENABLE_EARLY_PLACE
  • FLOW_ENABLE_HC_COMPARE
  • FLOW_ENABLE_HCII_COMPARE
  • FLOW_ENABLE_HYPER_RETIMER_FAST_FORWARD
  • FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS
  • FLOW_ENABLE_PARALLEL_MODULES
  • FLOW_ENABLE_POWER_ANALYZER
  • FLOW_ENABLE_RTL_VIEWER
  • FLOW_ENABLE_TIMEQUEST_AFTER_EARLY_PLACE_STAGE
  • FLOW_ENABLE_TIMEQUEST_AFTER_PLAN_STAGE
  • FLOW_ENABLE_TIMING_ANALYZER_AFTER_EARLY_PLACE_STAGE
  • FLOW_ENABLE_TIMING_ANALYZER_AFTER_PLAN_STAGE
  • FLOW_ENABLE_TIMING_CONSTRAINT_CHECK
  • FLOW_HARDCOPY_DESIGN_READINESS_CHECK
  • FMAX_REQUIREMENT
  • FOCUS_ENTITY_NAME
  • FORCE_ALL_TILES_WITH_FAILING_TIMING_PATHS_TO_HIGH_SPEED
  • FORCE_ALL_USED_TILES_TO_HIGH_SPEED
  • FORCE_CONFIGURATION_VCCIO
  • FORCED_IF_ASYNCHRONOUS
  • FORCED
  • FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS
  • FORCE_FRACTURED_MODE_ALM_IMPLEMENTATION
  • FORCE_HYPER_REGISTER_FOR_CORE_PERIPHERY_TRANSFER
  • FORCE_HYPER_REGISTER_FOR_PERIPHERY_CORE_TRANSFER
  • FORCE_HYPER_REGISTER_FOR_UIB_ESRAM_CORE_REGISTER
  • FORCE_MERGE_PLL_FANOUTS
  • FORCE_MERGE_PLL
  • FORCE_NON_FRACTURED_MODE_ALM_IMPLEMENTATION
  • FORCE_POINT_TO_POINT
  • FORCE_RECOMPILE
  • FORCE_SLACK
  • FORCE_SSMCLK_TO_ISMCLK
  • FORCE_SYNCH_CLEAR
  • FORM_DDR_CLUSTERING_CLIQUE
  • FPLL
  • FPLL_VREG1_BOOST_1_STEP
  • FPLL_VREG1_BOOST_2_STEP
  • FPLL_VREG1_BOOST_3_STEP
  • FPLL_VREG1_BOOST_4_STEP
  • FPLL_VREG1_BOOST_5_STEP
  • FPLL_VREG1_BOOST_6_STEP
  • FPLL_VREG1_BOOST_7_STEP
  • FPLL_VREG1_NO_VOLTAGE_BOOST
  • FPLL_VREG_BOOST_1_STEP
  • FPLL_VREG_BOOST_2_STEP
  • FPLL_VREG_BOOST_3_STEP
  • FPLL_VREG_BOOST_4_STEP
  • FPLL_VREG_BOOST_5_STEP
  • FPLL_VREG_BOOST_6_STEP
  • FPLL_VREG_BOOST_7_STEP
  • FPLL_VREG_NO_VOLTAGE_BOOST
  • FRACTAL_SYNTHESIS
  • FREQ_100MHZ
  • FREQ_12_5MHZ
  • FREQ_20MHZ
  • FREQ_25MHZ
  • FREQ_40MHZ
  • FREQ_50MHZ
  • FSDA_LEVEL_AUTO
  • FSDA_LEVEL_C1
  • FSDA_LEVEL_C2
  • FSDA_LEVEL_U
  • FSM_CAT
  • FSM_RULE_DEADLOCK_STATE
  • FSM_RULE_NO_RESET_STATE
  • FSM_RULE_NO_SZER_ACLK_DOMAIN
  • FSM_RULE_UNREACHABLE_STATE
  • FSM_RULE_UNUSED_TRANSITION
  • FSYN_AND_ICP_REGTEST_MODE
  • FULL_BW
  • FULL_COMPILATION
  • FULL_INCREMENTAL_COMPILATION
  • FULL_INCREMENTAL_DESIGN
  • FULL
  • FULL_VPACK
  • FULL_VPR
  • FUNCTIONAL
  • FV_BLACKBOX
  • GBE_1250
  • GDF_FILE
  • GEN3_OFF
  • GEN3_ON
  • GEN4_OFF
  • GEN4_ON
  • GENERAL_POOL
  • GENERATE_CONFIG_HEXOUT_FILE
  • GENERATE_CONFIG_ISC_FILE
  • GENERATE_CONFIG_JAM_FILE
  • GENERATE_CONFIG_JBC_FILE_COMPRESSED
  • GENERATE_CONFIG_JBC_FILE
  • GENERATE_CONFIG_SVF_FILE
  • GENERATE_GXB_RECONFIG_MIF
  • GENERATE_GXB_RECONFIG_MIF_WITH_PLL
  • GENERATE_HEX_FILE
  • GENERATE_ISC_FILE
  • GENERATE_JAM_FILE
  • GENERATE_JBC_FILE_COMPRESSED
  • GENERATE_JBC_FILE
  • GENERATE_PMSF_FILES
  • GENERATE_PR_RBF_FILE
  • GENERATE_RBF_FILE
  • GENERATE_SVF_FILE
  • GENERATE_TTF_FILE
  • GENERATION_DIRECTORY
  • GENERIC_TRAIT
  • GIGE
  • GIVE_ERROR
  • GIVE_INFO
  • GIVE_WARNING
  • GLITCH_DETECTION
  • GLITCH_DETECTION_PULSE
  • GLITCH_INTERVAL
  • GLOBAL_CLOCK
  • GLOBAL
  • GLOBAL_PLACEMENT_EFFORT
  • GLOBAL_SIGNAL_CLKCTRL_LOCATION
  • GLOBAL_SIGNAL
  • GLOBAL_SKEW_BALANCED
  • GNDIO_CURRENT_1PT8V
  • GNDIO_CURRENT_2PT5V
  • GNDIO_CURRENT_GTL
  • GNDIO_CURRENT_GTL_PLUS
  • GNDIO_CURRENT_LVCMOS
  • GNDIO_CURRENT_LVTTL
  • GNDIO_CURRENT_PCI
  • GNDIO_CURRENT_SSTL2_CLASS1
  • GNDIO_CURRENT_SSTL2_CLASS2
  • GNDIO_CURRENT_SSTL3_CLASS1
  • GNDIO_CURRENT_SSTL3_CLASS2
  • GNU_ASM_COMMAND_LINE
  • GNU_CPP_COMMAND_LINE
  • GNU_CSP_ASM_COMMAND_LINE
  • GNU_CSP_CPP_COMMAND_LINE
  • GNU_CSP_LINK_COMMAND_LINE
  • GNU_LINK_COMMAND_LINE
  • GNUPRO_ARM_ASM_COMMAND_LINE
  • GNUPRO_ARM_CPP_COMMAND_LINE
  • GNUPRO_ARM_LINK_COMMAND_LINE
  • GNUPRO_MIPS_ASM_COMMAND_LINE
  • GNUPRO_MIPS_CPP_COMMAND_LINE
  • GNUPRO_MIPS_LINK_COMMAND_LINE
  • GNUPRO_NIOS_ASM_COMMAND_LINE
  • GNUPRO_NIOS_CPP_COMMAND_LINE
  • GNUPRO_NIOS_LINK_COMMAND_LINE
  • GPH9
  • GPLL_TO_LVDS_TX
  • GPON_1244
  • GPON_155
  • GPON_2488
  • GPON_622
  • GRAY
  • GROUNDED
  • GROUP_COMB_LOGIC_IN_CLOUD
  • GROUP_COMB_LOGIC_IN_CLOUD_TMV
  • GROUP_NODES
  • GROUP_NODES_TMV
  • GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME
  • GXB_0PPM_CLOCK_GROUP_DRIVER
  • GXB_0PPM_CLOCK_GROUP
  • GXB_0PPM_CORECLK
  • GXB_0PPM_CORE_CLOCK
  • GXB_CLOCK_GROUP_DRIVER
  • GXB_CLOCK_GROUP
  • GXB_IO_PIN_TERMINATION
  • GXB_RECONFIG_GROUP
  • GXB_RECONFIG_MIF
  • GXB_RECONFIG_MIF_PLL
  • GXB_REFCLK_COUPLING_TERMINATION_SETTING
  • GXB_REFCLK_PIN_TERMINATION
  • GXB_RESERVED_TRANSMIT_CHANNEL
  • GXB_TX_PLL_RECONFIG_GROUP
  • GXB_VCCA_VOLTAGE
  • GXB_VCCR_VCCT_VOLTAGE
  • H9K8
  • HALF_BW
  • HALF
  • HALF_MEGALAB_COLUMN
  • HALF_RESOLUTION
  • HALF_ROW
  • HARD_BLOCK_PARTITION
  • HARDCOPY_DEVICE_IDENTIFIER
  • HARDCOPY_EXTERNAL_CLOCK_JITTER
  • HARDCOPY_FLOW_AUTOMATION
  • HARDCOPYII_COMPANION_REVISION_NAME
  • HARDCOPYII_POWER_ON_EXTRA_DELAY
  • HARDCOPYII_RUN_COMPARISON_ON_EVERY_COMPILE
  • HARDCOPYII_SAVE_MIGRATION_INFO_DURING_COMPILATION
  • HARDCOPY_INDIVIDUAL_SETTINGS
  • HARDCOPY_INPUT_TRANSITION_CLOCK_PIN
  • HARDCOPY_INPUT_TRANSITION_DATA_PIN
  • HARDCOPY_NEW_PROJECT_PATH
  • HARD_POST_FIT
  • HCII_OUTPUT_DIR
  • HC_OUTPUT_DIR
  • HCPY_ALOAD_SIGNALS
  • HCPY_ASYN_RAM
  • HCPY_CAT
  • HCPY_EXCEED_RAM_USAGE
  • HCPY_EXCEED_USER_IO_USAGE
  • HCPY_EXT_CLK_JITTER_CHECK
  • HCPY_EXT_CLK_JITTER_EDGE
  • HCPY_EXT_CLK_JITTER
  • HCPY_ILLEGAL_HC_DEV_PKG
  • HCPY_INPUT_TRANS_CLK_PIN
  • HCPY_INPUT_TRANS_DATA_PIN
  • HCPY_PLL_MULTIPLE_CLK_NETWORK_TYPES
  • HCPY_TRANS_CONDITION_CLK_PIN
  • HCPY_TRANS_CONDITION_DATA_PIN
  • HCPY_TRANS_EDGE_CLK_PIN
  • HCPY_TRANS_EDGE_DATA_PIN
  • HCPY_VREF_PINS
  • HDL_INITIAL_FANOUT_LIMIT
  • HDL_INTERFACE_INSTANCE_ENTITY
  • HDL_INTERFACE_INSTANCE_NAME
  • HDL_INTERFACE_INSTANCE_PARAMETERS
  • HDL_INTERFACE_OUTPUT_PATH
  • HDL_MESSAGE_LEVEL
  • HDL_MESSAGE_OFF
  • HDL_MESSAGE_ON
  • HDL_SETTINGS
  • HDL_VERSION
  • HEIGHT
  • HEX_FILE_COUNT_UP_DOWN
  • HEX_FILE_COUNT_UP_OR_DOWN
  • HEX_FILE
  • HEX_FILE_START_ADDRESS
  • HEXOUT_FILE_COUNT_DIRECTION
  • HEXOUT_FILE
  • HEXOUT_FILE_START_ADDRESS
  • HEX_OUTPUT_FILE
  • HIDE_RCF_WARNINGS
  • HIERARCHICAL_COMPILE
  • HIERARCHICAL_PRPOF_ID_CHECK
  • HIERARCHY_BLACKBOX_FILE
  • HIGH_EFFORT
  • HIGH_EFFORT_ROUTE_INI
  • HIGH
  • HIGH_PACKING_ROUTABILITY_EFFORT
  • HIGH_PERF
  • HIGH_PERFORMANCE_EFFORT
  • HIGH_PERFORMANCE_EFFORT_WITH_MAXIMUM_PLACEMENT_EFFORT
  • HIGH_PLACEMENT_ROUTABILITY_EFFORT
  • HIGH_POWER_EFFORT
  • HIGH_ROUTABILITY_EFFORT
  • HIGH_VCM
  • HIGIG_4062
  • HIGIG_5000
  • HIGIG_6250
  • HIGIG_6562
  • HOLD_MULTICYCLE_DEFAULT
  • HOLD_MULTICYCLE
  • HOLD_RELATIONSHIP
  • HPS_AUTO_PARTITION
  • HPS_COLD_RESET_PIN_MODE
  • HPS_DAP_SPLIT_MODE
  • HPS_EARLY_IO_RELEASE
  • HPS_FIRST
  • HPS_INITIALIZATION
  • HPS_IO
  • HPS_ISW_DATA
  • HPS_ISW_EMIF
  • HPS_ISW_FILE
  • HPS_LOCATION
  • HPS_PARTITION
  • HPS_PINS
  • HPS_WARM_RESET_PIN_MODE
  • HSSI_A10_CDR_PLL_ANALOG_MODE
  • HSSI_A10_CDR_PLL_POWER_MODE
  • HSSI_A10_CDR_PLL_REQUIRES_GT_CAPABLE_CHANNEL
  • HSSI_A10_CDR_PLL_UC_RO_CAL
  • HSSI_A10_CMU_FPLL_ANALOG_MODE
  • HSSI_A10_CMU_FPLL_PLL_DPRIO_CLK_VREG_BOOST
  • HSSI_A10_CMU_FPLL_PLL_DPRIO_FPLL_VREG1_BOOST
  • HSSI_A10_CMU_FPLL_PLL_DPRIO_FPLL_VREG_BOOST
  • HSSI_A10_CMU_FPLL_PLL_DPRIO_STATUS_SELECT
  • HSSI_A10_CMU_FPLL_POWER_MODE
  • HSSI_A10_LC_PLL_ANALOG_MODE
  • HSSI_A10_LC_PLL_POWER_MODE
  • HSSI_A10_PM_UC_CLKDIV_SEL
  • HSSI_A10_PM_UC_CLKSEL_CORE
  • HSSI_A10_PM_UC_CLKSEL_OSC
  • HSSI_A10_REFCLK_TERM_TRISTATE
  • HSSI_A10_RX_ADAPT_DFE_CONTROL_SEL
  • HSSI_A10_RX_ADAPT_DFE_SEL
  • HSSI_A10_RX_ADAPT_VGA_SEL
  • HSSI_A10_RX_ADAPT_VREF_SEL
  • HSSI_A10_RX_ADP_CTLE_ACGAIN_4S
  • HSSI_A10_RX_ADP_CTLE_EQZ_1S_SEL
  • HSSI_A10_RX_ADP_DFE_FLTAP_POSITION
  • HSSI_A10_RX_ADP_DFE_FXTAP10
  • HSSI_A10_RX_ADP_DFE_FXTAP10_SGN
  • HSSI_A10_RX_ADP_DFE_FXTAP11
  • HSSI_A10_RX_ADP_DFE_FXTAP11_SGN
  • HSSI_A10_RX_ADP_DFE_FXTAP1
  • HSSI_A10_RX_ADP_DFE_FXTAP2
  • HSSI_A10_RX_ADP_DFE_FXTAP2_SGN
  • HSSI_A10_RX_ADP_DFE_FXTAP3
  • HSSI_A10_RX_ADP_DFE_FXTAP3_SGN
  • HSSI_A10_RX_ADP_DFE_FXTAP4
  • HSSI_A10_RX_ADP_DFE_FXTAP4_SGN
  • HSSI_A10_RX_ADP_DFE_FXTAP5
  • HSSI_A10_RX_ADP_DFE_FXTAP5_SGN
  • HSSI_A10_RX_ADP_DFE_FXTAP6
  • HSSI_A10_RX_ADP_DFE_FXTAP6_SGN
  • HSSI_A10_RX_ADP_DFE_FXTAP7
  • HSSI_A10_RX_ADP_DFE_FXTAP7_SGN
  • HSSI_A10_RX_ADP_DFE_FXTAP8
  • HSSI_A10_RX_ADP_DFE_FXTAP8_SGN
  • HSSI_A10_RX_ADP_DFE_FXTAP9
  • HSSI_A10_RX_ADP_DFE_FXTAP9_SGN
  • HSSI_A10_RX_ADP_LFEQ_FB_SEL
  • HSSI_A10_RX_ADP_ONETIME_DFE
  • HSSI_A10_RX_ADP_VGA_SEL
  • HSSI_A10_RX_ADP_VREF_SEL
  • HSSI_A10_RX_BYPASS_EQZ_STAGES_234
  • HSSI_A10_RX_EQ_BW_SEL
  • HSSI_A10_RX_EQ_DC_GAIN_TRIM
  • HSSI_A10_RX_INPUT_VCM_SEL
  • HSSI_A10_RX_LINK
  • HSSI_A10_RX_OFFSET_CANCELLATION_CTRL
  • HSSI_A10_RX_ONE_STAGE_ENABLE
  • HSSI_A10_RX_POWER_MODE
  • HSSI_A10_RX_QPI_ENABLE
  • HSSI_A10_RX_RX_SEL_BIAS_SOURCE
  • HSSI_A10_RX_SD_OUTPUT_OFF
  • HSSI_A10_RX_SD_OUTPUT_ON
  • HSSI_A10_RX_SD_THRESHOLD
  • HSSI_A10_RX_TERM_SEL
  • HSSI_A10_RX_TERM_TRI_ENABLE
  • HSSI_A10_RX_UC_RX_DFE_CAL
  • HSSI_A10_RX_VCCELA_SUPPLY_VOLTAGE
  • HSSI_A10_RX_VCM_CURRENT_ADD
  • HSSI_A10_RX_VCM_SEL
  • HSSI_A10_RX_XRX_PATH_ANALOG_MODE
  • HSSI_A10_TX_COMPENSATION_EN
  • HSSI_A10_TX_DCD_DETECTION_EN
  • HSSI_A10_TX_DPRIO_CGB_VREG_BOOST
  • HSSI_A10_TX_LINK
  • HSSI_A10_TX_LOW_POWER_EN
  • HSSI_A10_TX_POWER_MODE
  • HSSI_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP
  • HSSI_A10_TX_PRE_EMP_SIGN_2ND_POST_TAP
  • HSSI_A10_TX_PRE_EMP_SIGN_PRE_TAP_1T
  • HSSI_A10_TX_PRE_EMP_SIGN_PRE_TAP_2T
  • HSSI_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP
  • HSSI_A10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP
  • HSSI_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T
  • HSSI_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T
  • HSSI_A10_TX_RES_CAL_LOCAL
  • HSSI_A10_TX_RX_DET
  • HSSI_A10_TX_RX_DET_OUTPUT_SEL
  • HSSI_A10_TX_RX_DET_PDB
  • HSSI_A10_TX_SLEW_RATE_CTRL
  • HSSI_A10_TX_TERM_CODE
  • HSSI_A10_TX_TERM_SEL
  • HSSI_A10_TX_UC_DCD_CAL
  • HSSI_A10_TX_UC_GEN3
  • HSSI_A10_TX_UC_GEN4
  • HSSI_A10_TX_UC_SKEW_CAL
  • HSSI_A10_TX_UC_TXVOD_CAL_CONT
  • HSSI_A10_TX_UC_TXVOD_CAL
  • HSSI_A10_TX_UC_VCC_SETTING
  • HSSI_A10_TX_USER_FIR_COEFF_CTRL_SEL
  • HSSI_A10_TX_VOD_OUTPUT_SWING_CTRL
  • HSSI_A10_TX_XTX_PATH_ANALOG_MODE
  • HSSI_ADCE_RGEN_MODE
  • HSSI_ANALOG_SETTINGS_PROTOCOL
  • HSSI_C10_CDR_PLL_ANALOG_MODE
  • HSSI_C10_CDR_PLL_POWER_MODE
  • HSSI_C10_CDR_PLL_REQUIRES_GT_CAPABLE_CHANNEL
  • HSSI_C10_CDR_PLL_UC_RO_CAL
  • HSSI_C10_CMU_FPLL_ANALOG_MODE
  • HSSI_C10_CMU_FPLL_PLL_DPRIO_CLK_VREG_BOOST
  • HSSI_C10_CMU_FPLL_PLL_DPRIO_FPLL_VREG1_BOOST
  • HSSI_C10_CMU_FPLL_PLL_DPRIO_FPLL_VREG_BOOST
  • HSSI_C10_CMU_FPLL_PLL_DPRIO_STATUS_SELECT
  • HSSI_C10_CMU_FPLL_POWER_MODE
  • HSSI_C10_LC_PLL_ANALOG_MODE
  • HSSI_C10_LC_PLL_POWER_MODE
  • HSSI_C10_PM_UC_CLKDIV_SEL
  • HSSI_C10_PM_UC_CLKSEL_CORE
  • HSSI_C10_PM_UC_CLKSEL_OSC
  • HSSI_C10_REFCLK_TERM_TRISTATE
  • HSSI_C10_RX_ADAPT_DFE_CONTROL_SEL
  • HSSI_C10_RX_ADAPT_DFE_SEL
  • HSSI_C10_RX_ADAPT_VGA_SEL
  • HSSI_C10_RX_ADAPT_VREF_SEL
  • HSSI_C10_RX_ADP_CTLE_ACGAIN_4S
  • HSSI_C10_RX_ADP_CTLE_EQZ_1S_SEL
  • HSSI_C10_RX_ADP_DFE_FLTAP_POSITION
  • HSSI_C10_RX_ADP_DFE_FXTAP10
  • HSSI_C10_RX_ADP_DFE_FXTAP10_SGN
  • HSSI_C10_RX_ADP_DFE_FXTAP11
  • HSSI_C10_RX_ADP_DFE_FXTAP11_SGN
  • HSSI_C10_RX_ADP_DFE_FXTAP1
  • HSSI_C10_RX_ADP_DFE_FXTAP2
  • HSSI_C10_RX_ADP_DFE_FXTAP2_SGN
  • HSSI_C10_RX_ADP_DFE_FXTAP3
  • HSSI_C10_RX_ADP_DFE_FXTAP3_SGN
  • HSSI_C10_RX_ADP_DFE_FXTAP4
  • HSSI_C10_RX_ADP_DFE_FXTAP4_SGN
  • HSSI_C10_RX_ADP_DFE_FXTAP5
  • HSSI_C10_RX_ADP_DFE_FXTAP5_SGN
  • HSSI_C10_RX_ADP_DFE_FXTAP6
  • HSSI_C10_RX_ADP_DFE_FXTAP6_SGN
  • HSSI_C10_RX_ADP_DFE_FXTAP7
  • HSSI_C10_RX_ADP_DFE_FXTAP7_SGN
  • HSSI_C10_RX_ADP_DFE_FXTAP8
  • HSSI_C10_RX_ADP_DFE_FXTAP8_SGN
  • HSSI_C10_RX_ADP_DFE_FXTAP9
  • HSSI_C10_RX_ADP_DFE_FXTAP9_SGN
  • HSSI_C10_RX_ADP_LFEQ_FB_SEL
  • HSSI_C10_RX_ADP_ONETIME_DFE
  • HSSI_C10_RX_ADP_VGA_SEL
  • HSSI_C10_RX_ADP_VREF_SEL
  • HSSI_C10_RX_BYPASS_EQZ_STAGES_234
  • HSSI_C10_RX_EQ_BW_SEL
  • HSSI_C10_RX_EQ_DC_GAIN_TRIM
  • HSSI_C10_RX_INPUT_VCM_SEL
  • HSSI_C10_RX_LINK
  • HSSI_C10_RX_OFFSET_CANCELLATION_CTRL
  • HSSI_C10_RX_ONE_STAGE_ENABLE
  • HSSI_C10_RX_POWER_MODE
  • HSSI_C10_RX_QPI_ENABLE
  • HSSI_C10_RX_RX_SEL_BIAS_SOURCE
  • HSSI_C10_RX_SD_OUTPUT_OFF
  • HSSI_C10_RX_SD_OUTPUT_ON
  • HSSI_C10_RX_SD_THRESHOLD
  • HSSI_C10_RX_TERM_SEL
  • HSSI_C10_RX_TERM_TRI_ENABLE
  • HSSI_C10_RX_UC_RX_DFE_CAL
  • HSSI_C10_RX_VCCELA_SUPPLY_VOLTAGE
  • HSSI_C10_RX_VCM_CURRENT_ADD
  • HSSI_C10_RX_VCM_SEL
  • HSSI_C10_RX_XRX_PATH_ANALOG_MODE
  • HSSI_C10_TX_COMPENSATION_EN
  • HSSI_C10_TX_DCD_DETECTION_EN
  • HSSI_C10_TX_DPRIO_CGB_VREG_BOOST
  • HSSI_C10_TX_LINK
  • HSSI_C10_TX_LOW_POWER_EN
  • HSSI_C10_TX_POWER_MODE
  • HSSI_C10_TX_PRE_EMP_SIGN_1ST_POST_TAP
  • HSSI_C10_TX_PRE_EMP_SIGN_2ND_POST_TAP
  • HSSI_C10_TX_PRE_EMP_SIGN_PRE_TAP_1T
  • HSSI_C10_TX_PRE_EMP_SIGN_PRE_TAP_2T
  • HSSI_C10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP
  • HSSI_C10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP
  • HSSI_C10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T
  • HSSI_C10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T
  • HSSI_C10_TX_RES_CAL_LOCAL
  • HSSI_C10_TX_RX_DET
  • HSSI_C10_TX_RX_DET_OUTPUT_SEL
  • HSSI_C10_TX_RX_DET_PDB
  • HSSI_C10_TX_SLEW_RATE_CTRL
  • HSSI_C10_TX_TERM_CODE
  • HSSI_C10_TX_TERM_SEL
  • HSSI_C10_TX_UC_DCD_CAL
  • HSSI_C10_TX_UC_GEN3
  • HSSI_C10_TX_UC_GEN4
  • HSSI_C10_TX_UC_SKEW_CAL
  • HSSI_C10_TX_UC_TXVOD_CAL_CONT
  • HSSI_C10_TX_UC_TXVOD_CAL
  • HSSI_C10_TX_UC_VCC_SETTING
  • HSSI_C10_TX_USER_FIR_COEFF_CTRL_SEL
  • HSSI_C10_TX_VOD_OUTPUT_SWING_CTRL
  • HSSI_C10_TX_XTX_PATH_ANALOG_MODE
  • HSSI_CLOCK_TOPOLOGY
  • HSSI_FAST_LOCK_MODE
  • HSSI_GT_FORCE_VCO_CONST
  • HSSI_GT_RX_CTLE
  • HSSI_GT_RX_RX_DC_GAIN
  • HSSI_GT_RX_VCM_SEL
  • HSSI_GT_TERMINATION
  • HSSI_GT_TX_COMMON_MODE_DRIVER_SEL
  • HSSI_GT_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP
  • HSSI_GT_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP
  • HSSI_GT_TX_SIG_INV_PRE_TAP
  • HSSI_GT_TX_VOD_SWITCHING_CTRL_MAIN_TAP
  • HSSI_ODI_EYE_MONITOR_BW_SEL
  • HSSI_PARAMETER
  • HSSI_REFCLK_TERMINATION
  • HSSI_RX_ACGAIN_A
  • HSSI_RX_ACGAIN_V
  • HSSI_RX_ADCE_HSF_HFBW
  • HSSI_RX_ADCE_RGEN_BW
  • HSSI_RX_BYPASS_EQZ_STAGES_234
  • HSSI_RX_CT_EQUALIZER_SETTING
  • HSSI_RX_DFE_PI_BW
  • HSSI_RX_ENABLE_RX_GAINCTRL_PCIEMODE
  • HSSI_RX_EQ_BW_SEL
  • HSSI_RX_INPUT_VCM_SEL
  • HSSI_RX_PDB_SD
  • HSSI_RX_PMOS_GAIN_PEAK
  • HSSI_RX_QPI_ENABLE
  • HSSI_RX_RX_DC_GAIN
  • HSSI_RX_RX_SEL_BIAS_SOURCE
  • HSSI_RX_SD_OFF
  • HSSI_RX_SD_ON
  • HSSI_RX_SD_THRESHOLD
  • HSSI_RX_SEL_HALF_BW
  • HSSI_RX_VCCELA_SUPPLY_VOLTAGE
  • HSSI_RX_VCM_CURRENT_ADD
  • HSSI_RX_VCM_SEL
  • HSSI_S10_REFCLK_TERM_TRISTATE
  • HSSI_TERMINATION
  • HSSI_TX_COMMON_MODE_DRIVER_SEL
  • HSSI_TX_DRIVER_RESOLUTION_CTRL
  • HSSI_TX_FIR_COEFF_CTRL_SEL
  • HSSI_TX_LOCAL_IB_CTL
  • HSSI_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP
  • HSSI_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP
  • HSSI_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP_USER
  • HSSI_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP
  • HSSI_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_USER
  • HSSI_TX_QPI_EN
  • HSSI_TX_RX_DET
  • HSSI_TX_RX_DET_OUTPUT_SEL
  • HSSI_TX_RX_DET_PDB
  • HSSI_TX_SIG_INV_2ND_TAP
  • HSSI_TX_SIG_INV_PRE_TAP
  • HSSI_TX_SLEW_RATE_CTRL
  • HSSI_TX_SWING_BOOST
  • HSSI_TX_VCM_CTRL_SEL
  • HSSI_TX_VCM_CURRENT_ADDL
  • HSSI_TX_VOD_BOOST
  • HSSI_TX_VOD_SWITCHING_CTRL_MAIN_TAP
  • HSSI_VCCEH_VOLTAGE
  • HSSI_VCCER_VCCET_VOLTAGE
  • HTML_FILE
  • HTML_REPORT_FILE
  • HUB_AUTO_INSERT
  • HUB_ENTITY_NAME
  • HUB_INSTANCE_NAME
  • HUB_SOURCE_FILE
  • HYBRID_FLOW_NEW_EXTRACTOR
  • HYBRID
  • HYPER_AWARE_OPTIMIZE_REGISTER_CHAINS
  • HYPER_AWARE_OPTIMIZE_SHORT_PATHS
  • HYPER_AWARE_OPTIMIZE_TIMING
  • HYPER_AWARE_REGISTER_PLACEMENT
  • HYPER_AWARE_SET_REGISTER_BYPASS
  • HYPER_AWARE_SET_REGISTER_INITIAL_STATE
  • HYPER_EARLY_RETIMER
  • HYPER_REGISTER_DELAY_CHAIN
  • HYPER_REGISTER
  • HYPER_RETIMER_ADD_PIPELINING_GROUP
  • HYPER_RETIMER_ADD_PIPELINING
  • HYPER_RETIMER_ENABLE_ADD_PIPELINING
  • HYPER_RETIMER_FALSE_PATH_RESTRICTION
  • HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING
  • HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX
  • HYPER_RETIMER_FAST_FORWARD_AGGRESSIVE_EXPLORATION
  • HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR
  • HYPER_RETIMER_FAST_FORWARD_CUT_ALL_CLOCK_TRANSFERS
  • HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS
  • HYPER_RETIMER_FAST_FORWARD_EMULATE_ADD_PIPELINING
  • HYPER_RETIMER_FAST_FORWARD_EMULATE_AGGRESSIVE_EXPLORATION
  • HYPER_RETIMER_FAST_FORWARD_EMULATE_ASYNCH_CLEAR
  • HYPER_RETIMER_FAST_FORWARD_EMULATE_USER_PRESERVE_RESTRICTION
  • HYPER_RETIMER_FAST_FORWARD
  • HYPER_RETIMER_FAST_FORWARD_OFF_DESCRIPTION
  • HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS
  • HYPER_RETIMER_FAST_FORWARD_TARGET_MAX_PERFORMANCE
  • HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION
  • HYPER_RETIMER
  • HYPER_RETIMER_REGISTERS_REMOVED
  • IB_22OHM
  • IB_29OHM
  • IB_42OHM
  • IB_49OHM
  • IEEE_10G_BASE_CR_10312
  • IEEE_10G_KR_10312
  • IEEE_40G_BASE_KR_10312
  • IGNORE_CARRY_BUFFERS
  • IGNORE_CARRY
  • IGNORE_CASCADE_BUFFERS
  • IGNORE_CASCADE
  • IGNORE_CLOCK_SETTINGS
  • IGNORE_DUPLICATE_DESIGN_ENTITY
  • IGNORE_GLOBAL_BUFFERS
  • IGNORE_GLOBAL
  • IGNORE_HSSI_COLUMN_POWER_FOR_BTI_MITIGATION
  • IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS
  • IGNORE_LCELL_BUFFERS
  • IGNORE_LCELL
  • IGNORE_LCELL_MAX7000
  • IGNORE_MAX_FANOUT_ASSIGNMENTS
  • IGNORE_MODE_FOR_MERGE
  • IGNORE_PARTITIONS
  • IGNORE_ROW_GLOBAL_BUFFERS
  • IGNORE_ROW_GLOBAL
  • IGNORE_SOFT_BUFFERS
  • IGNORE_SOFT
  • IGNORE_SOFT_MAX7000
  • IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF
  • IGNORE_TRANSLATE_OFF
  • IGNORE_VERILOG_INITIAL_CONSTRUCTS
  • IGNORE_VREF_RESTRICTION
  • IMMEDIATE_ASSERTION_FAIL_ACTION
  • IMMEDIATE_ASSERTION_FAIL_MESSAGE
  • IMMEDIATE_ASSERTION
  • IMMEDIATE_ASSERTION_PASS_MESSAGE
  • IMMEDIATE_ASSERTION_STATE
  • IMMEDIATE_ASSERTION_TEST_CONDITION
  • IMPLEMENT_AS_CLOCK_ENABLE
  • IMPLEMENT_AS_LCELL
  • IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL
  • IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE
  • IMPLEMENTS_FREE_RUNNING_CLOCK
  • IMPORT_BASED_POST_FIT
  • IMPORT_BLOCK
  • IMPORTED
  • IMPORT
  • INCLUDED_IN_OLD_CHIP_SECTION
  • INCLUDED_IN_OLD_PROJECT_INFO_SECTION
  • INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS
  • INCLUDE_FILE
  • INCLUDE_IN_ALL_TB2
  • INCLUDE_IN_COMPILER_REPORT
  • INCLUDE_IN_FITTER_TB2
  • INCLUDE_IN_POWER_TB2
  • INCLUDE_IN_SIMULATOR_REPORT
  • INCLUDE_IN_SYNTHESIS_REPORT
  • INCLUDE_IN_SYNTHESIS_TB2
  • INCLUDE_IN_TIMING_TB2
  • INCLUDE_PATHS_GREATER_THAN_TCO
  • INCLUDE_PATHS_GREATER_THAN_TH
  • INCLUDE_PATHS_GREATER_THAN_TPD
  • INCLUDE_PATHS_GREATER_THAN_TSU
  • INCLUDE_PATHS_LESS_THAN_FMAX
  • INCLUDE_PATHS_LESS_THAN_SLACK
  • INCLUDE_PIN_DELAYS_IN_CALCULATIONS
  • INC_PLACE_PREF_LOCATION
  • INC_PLC_MODE
  • INCREASE_DELAY_TO_OUTPUT_ENABLE_PIN
  • INCREASE_DELAY_TO_OUTPUT_PIN
  • INCREASE_INPUT_CLOCK_ENABLE_DELAY
  • INCREASE_INPUT_DELAY_TO_CE_IO_REGISTER
  • INCREASE_OUTPUT_CLOCK_ENABLE_DELAY
  • INCREASE_OUTPUT_ENABLE_CLOCK_ENABLE_DELAY
  • INCREASE_OUTPUT_ENABLE_CLOCK_ENABLE_DELAYR
  • INCREASE_TZX_DELAY_TO_OUTPUT_PIN
  • INCREMENTAL_COMPILATION_EXPORT_FILE
  • INCREMENTAL_COMPILATION_EXPORT_FLATTEN
  • INCREMENTAL_COMPILATION_EXPORT_NETLIST_TYPE
  • INCREMENTAL_COMPILATION_EXPORT_PARTITION_NAME
  • INCREMENTAL_COMPILATION_EXPORT_POST_FIT
  • INCREMENTAL_COMPILATION_EXPORT_POST_SYNTH
  • INCREMENTAL_COMPILATION_EXPORT_ROUTING
  • INCREMENTAL_COMPILATION
  • INCREMENTAL_INPUT_VECTOR_FILE
  • INCREMENTAL_SYNTHESIS_FULL
  • INCREMENTAL_SYNTHESIS
  • INCREMENTAL_SYNTHESIS_PARTITION
  • INCREMENTAL_SYNTHESIS_TOP
  • INCREMENTAL_TIME_INPUT
  • INCREMENTAL_VECTOR_INPUT_SOURCE
  • INCR_SIGNALTAP_PARTITION
  • INCR_TAP
  • INDIRECT_PORT_ASSIGNMENT
  • INERTIAL
  • INFER_RAMS_FROM_RAW_LOGIC
  • INIT_CLKUSR
  • INIT_DCLK
  • INIT_DONE_OPEN_DRAIN
  • INIT_DONE_OUTPUT
  • INITIALIZATION_CLOCK
  • INITIAL_PLACEMENT_CONFIGURATION
  • INIT_INTOSC
  • INI_VARS
  • INNER_NUM
  • INPUT_DELAY_CHAIN
  • INPUT_DELAY
  • INPUT_EDGE
  • INPUT
  • INPUT_MAX_DELAY
  • INPUT_MIN_DELAY
  • INPUT_OCT_VALUE
  • INPUT_ONLY
  • INPUT_PERSONA
  • INPUT_REFERENCE
  • INPUT_REGISTER
  • INPUT_TERMINATION
  • INPUT_TRANSITION_TIME
  • INSERT_ADDITIONAL_LOGIC_CELL
  • INSERT_BOUNDARY_WIRE_LUTS
  • INSTANT_ON
  • INTERFACE
  • INTERFACE_ROLE
  • INTERFACES
  • INTERFACE_TYPE
  • INTERLAKEN_11100
  • INTERLAKEN_12500
  • INTERLAKEN_3125
  • INTERLAKEN_6375
  • INTERLAKEN
  • INTERNAL_CONFIGURATION
  • INTERNAL_FLASH_UPDATE_MODE
  • INTERNAL
  • INTERNAL_OSCILLATOR_DIVIDE_DOWN
  • INTERNAL_SCRUBBING
  • INTERNAL_VREF_MODE
  • INVALID_DESIGN_SOURCE
  • INVERT_BASE_CLOCK
  • INVERTED_CLOCK
  • IO_12_LANE_INPUT_DATA_DELAY_CHAIN
  • IO_12_LANE_INPUT_DATA_DELAY
  • IO_12_LANE_INPUT_STROBE_DELAY_CHAIN
  • IO_12_LANE_INPUT_STROBE_DELAY
  • IOBANK
  • IOBANK_VCCIO
  • IO_MAXIMUM_TOGGLE_RATE
  • IO_PARTITION_PLACEMENT
  • IO_PATHS_AND_MINIMUM_TPD_PATHS
  • IO_PLACEMENT_OPTIMIZATION
  • IOPLL
  • IO_SSO_CHECKING
  • IO_STANDARD
  • IP_ADVISOR_FILE
  • IPA_FILE
  • IP_COMPONENT_AUTHOR
  • IP_COMPONENT_DESCRIPTION
  • IP_COMPONENT_DISPLAY_NAME
  • IP_COMPONENT_DOCUMENTATION_LINK
  • IP_COMPONENT_GROUP
  • IP_COMPONENT_INTERNAL
  • IP_COMPONENT_NAME
  • IP_COMPONENT_PARAMETER
  • IP_COMPONENT_REPORT_HIERARCHY
  • IP_COMPONENT_SETTING
  • IP_COMPONENT_VERSION
  • IP_DEBUG_VISIBLE
  • IP_FILE
  • IP_GENERATED_DEVICE_FAMILY
  • IP_QSYS_MODE
  • IP_SEARCH_PATHS
  • IP_SHOW_ANALYSIS_MESSAGES
  • IP_SHOW_ELABORATION_MESSAGES
  • IP_TARGETED_DEVICE_FAMILY
  • IP_TARGETED_PART_TRAIT
  • IP_TOOL_ENV
  • IP_TOOL_HIERARCHY_LEVELS
  • IP_TOOL_NAME
  • IP_TOOL_VENDOR_NAME
  • IP_TOOL_VERSION_CREATED
  • IP_TOOL_VERSION
  • IP_TOP_LEVEL_COMPONENT_NAME
  • IP_TOP_LEVEL_ENTITY_NAME
  • IPX_FILE
  • ISC_FILE
  • IS_DEBUG
  • IS_FREEFORM
  • ISL82XX
  • ISP_CLAMP_STATE_DEFAULT
  • ISP_CLAMP_STATE
  • JAM_FILE
  • JBC_FILE
  • JESD204_A_B_12500
  • JESD204_A_B_6375
  • JOHNSON
  • JTAG_BST_SUPPORT
  • JTAG_BST_SUPPORT_MAX7000
  • JTAG_PIN_SHARING
  • JTAG_USER_CODE_DALI
  • JTAG_USER_CODE_FLEX6K
  • JTAG_USER_CODE
  • K0H9
  • KEEP_LCELL_FOLLOWING_PLL
  • KEEP_LUT_SYN_ONLY
  • KXL9
  • LARGE
  • LARGE_PERIPHERY_CLOCK
  • LAST_QUARTUS_VERSION
  • LATE_CLOCK_LATENCY
  • LCELL_AS_VIO
  • LCELL_INSERTION
  • LCELL_PERIPHERY_ROUTER
  • LEVEL1
  • LEVEL2
  • LEVEL3
  • LIBRARY
  • LIBRARY_SEARCH_ORDER
  • LICENSE_FILE
  • LIMIT_AHDL_INTEGERS_TO_32_BITS
  • LINEAR_FORMAT
  • LL_AUTO_SIZE
  • LL_COLOR
  • LL_CORE_ONLY
  • LL_ENABLED
  • LL_EXCLUDE
  • LL_FSDA_LEVEL
  • LL_FSDA_ROUTING_INTERFACE
  • LL_HEIGHT
  • LL_HORIZONTAL_FLIP
  • LL_IGNORE_IO_BANK_FSDA_CONSTRAINT
  • LL_IGNORE_IO_BANK_SECURITY_CONSTRAINT
  • LL_IGNORE_IO_PIN_FSDA_CONSTRAINT
  • LL_IGNORE_IO_PIN_SECURITY_CONSTRAINT
  • LL_IMPORT_FILE
  • LL_MEMBER_EXCEPTIONS
  • LL_MEMBER_OF_FSDA_ROUTING_INTERFACE
  • LL_MEMBER_OF
  • LL_MEMBER_OF_SECURITY_ROUTING_INTERFACE
  • LL_MEMBER_OPTION
  • LL_MEMBER_RESOURCE_EXCLUDE
  • LL_MEMBER_STATE
  • LL_NODE_LOCATION
  • LL_OLD_BEHAVIOR
  • LL_ORIGIN
  • LL_OUTPUT_SIGNAL_FSDA_LEVEL
  • LL_PARENT
  • LL_PATH_EXCLUDE
  • LL_PATH_INCLUDE
  • LL_PRIORITY
  • LL_PR_REGION
  • LL_RCF_IMPORT_FILE
  • LL_RECT
  • LL_REGION_SECURITY_LEVEL
  • LL_RESERVED_IS_LIMITED
  • LL_RESERVED
  • LL_RESERVED_MEMBERS_OF_IMMEDIATE_PARENT_REGION_HIERARCHY_ONLY
  • LL_RESERVE
  • LL_ROOT_REGION
  • LL_ROUGH
  • LL_ROUTING_REGION_EXPANSION_SIZE
  • LL_ROUTING_REGION
  • LL_SECURITY_ROUTING_INTERFACE
  • LL_SIGNAL_SECURITY_LEVEL
  • LL_SOFT
  • LL_SOURCE_PARTITION_HIERARCHY
  • LL_SOURCE_PARTITION
  • LL_SOURCE_REGION
  • LL_STATE
  • LL_WIDTH
  • LMF_FILE
  • LOCAL
  • LOCAL_LINE_DELAY_CHAIN
  • LOCATION
  • LOCATION_PIN_ASSIGNMENT
  • LOCKED
  • LOGIC_ANALYZER_INTERFACE_FILE
  • LOGIC_ELEMENTS
  • LOGIC
  • LOGICLOCK_ASSIGNMENT
  • LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT
  • LOGICLOCK_INCREMENTAL_COMPILE_FILE
  • LOGICLOCK_REGION
  • LOGIC_MINIMIZATION_SCRIPT
  • LOW_CAP_ADJUST_FLEX10KE
  • LOW_POWER
  • LOW_VCM
  • LTM4677
  • LUTRAM_INSTANCES_FOR_ASIC_PROTOTYPING
  • LVDS_CLOCK_DATA_DESKEW_ADJUST
  • LVDS_DESKEW
  • LVDS_DIRECT_LOOPBACK_MODE
  • LVDS_FIXED_CLOCK_DATA_PHASE
  • LVDS
  • LVDS_RX_REGISTER
  • M10K
  • M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY
  • M144K
  • M144K_USE_DCD
  • M20K
  • M512
  • MACRO_HEAD
  • MACRO_MEMBER
  • MACRO_TIMING
  • MAP_FILE
  • MAPPER_SYNTHESIS_ASSIGNMENT
  • MASK
  • MASK_REVISION
  • MATCH_PLL_COMPENSATION_CLOCK
  • MAX10FPGA_CONFIGURATION_SCHEME
  • MAX3000A
  • MAX7000AE
  • MAX7000A
  • MAX7000B
  • MAX7000B_VCCIO_IOBANK1
  • MAX7000B_VCCIO_IOBANK2
  • MAX7000_DEVICE_IO_STANDARD
  • MAX7000_ENABLE_JTAG_BST_SUPPORT
  • MAX7000_FANIN_PER_CELL
  • MAX7000_IGNORE_LCELL_BUFFERS
  • MAX7000_IGNORE_SOFT_BUFFERS
  • MAX7000_INDIVIDUAL_TURBO_BIT
  • MAX7000_JTAG_USER_CODE
  • MAX7000_OPTIMIZATION_TECHNIQUE
  • MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH
  • MAX7000S_JTAG_USER_CODE
  • MAX7000S
  • MAX7000_TECHNOLOGY_MAPPER
  • MAX7000_USE_CHECKSUM_AS_USERCODE
  • MAX7K_CLIQUE_TYPE
  • MAX9000
  • MAX_AUTO_GLOBAL_REGISTER_CONTROLS
  • MAX_BALANCING_DSP_BLOCKS
  • MAX_CLOCK_ARRIVAL_SKEW
  • MAX_CLOCKS_ALLOWED
  • MAX_CONSECUTIVE_OUTPUTS_FOR_ELECTROMIGRATION
  • MAX_CONSECUTIVE_VIO_OUTPUTS_FOR_ELECTROMIGRATION
  • MAX_CORE_JUNCTION_TEMP
  • MAX_CORE_SUPPLY_VOLTAGE
  • MAX_CURRENT_FOR_ELECTROMIGRATION
  • MAX_CURRENT_FOR_VIO_ELECTROMIGRATION
  • MAX_DATA_ARRIVAL_SKEW
  • MAX_DELAY_FOR_CORE_PERIPHERY_TRANSFER
  • MAX_DELAY_FOR_PERIPHERY_CORE_TRANSFER
  • MAX_DELAY
  • MAX_FANOUT
  • MAX_GLOBAL_CLOCKS_ALLOWED
  • MAX_IGNORED_ASGN_MSG
  • MAXII_CARRY_CHAIN_LENGTH
  • MAXII_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
  • MAXII_OPTIMIZATION_TECHNIQUE
  • MAXIMUM_EFFORT
  • MAXIMUM
  • MAX_LABS
  • MAX_LARGE_PERIPHERY_CLOCKS_ALLOWED
  • MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS
  • MAX_PERIPHERY_CLOCKS_ALLOWED
  • MAXPLUSII
  • MAX_PROCESSORS_USED_FOR_MULTITHREADING
  • MAX_RAM_BLOCKS_M4K
  • MAX_RAM_BLOCKS_M512
  • MAX_RAM_BLOCKS_MRAM
  • MAX_REGIONAL_CLOCKS_ALLOWED
  • MAX_SCC_SIZE
  • MAX_WIRES_FOR_CORE_PERIPHERY_ROUTER
  • MAX_WIRES_FOR_CORE_PERIPHERY_TRANSFER
  • MAX_WIRES_FOR_PERIPHERY_CORE_ROUTER
  • MAX_WIRES_FOR_PERIPHERY_CORE_TRANSFER
  • MEDIUM
  • MEGAFUNCTION_GENERATED_TRI
  • MEGALAB_COLUMN
  • MEGALAB
  • MEGARAM
  • MEMBER_OF
  • MEM_INTERFACE_DELAY_CHAIN_CONFIG
  • MEMORY_INTERFACE_DATA_PIN_GROUP
  • MERCURY_CARRY_CHAIN_LENGTH
  • MERCURY_CLIQUE_TYPE
  • MERCURY_CONFIG_DEVICE_JTAG_USER_CODE
  • MERCURY_CONFIGURATION_DEVICE
  • MERCURY_CONFIGURATION_SCHEME
  • MERCURY_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
  • MERCURY_DEVICE_IO_STANDARD
  • MERCURY_FITTER_TYPE
  • MERCURY_JTAG_USER_CODE
  • MERCURY_OPTIMIZATION_TECHNIQUE
  • MERCURY_TECHNOLOGY_MAPPER
  • MERGE_EQUIVALENT_BIDIRS
  • MERGE_EQUIVALENT_INPUTS
  • MERGE_HEX_FILE
  • MERGE_TX_PLL_DRIVEN_BY_REGISTERS_WITH_SAME_CLEAR
  • MESSAGE_DISABLE
  • MESSAGE_ENABLE
  • MESSAGE_SUPPRESSION_RULE_FILE
  • MFCU
  • MID_POWER
  • MIF_FILE
  • MIGRATION_ASSIGNMENT
  • MIGRATION_AUTO_PACKED_REGISTERS
  • MIGRATION_AUTO_PORT_SWAP
  • MIGRATION_CONSTRAIN_CORE_RESOURCES
  • MIGRATION_DEVICES
  • MIGRATION_DIFFERENT_SOURCE_FILE
  • MIGRATION_ONLY
  • MIGRATION_PORT_SWAPPING
  • MIGRATION_RAM_INFORMATION
  • MIGRATION_RAM_PACKING_INFORMATION
  • MIGRATION_REGISTER_PACKING
  • MILLIVOLTS
  • MIN_CORE_JUNCTION_TEMP
  • MIN_CORE_SUPPLY_VOLTAGE
  • MIN_DELAY_FOR_CORE_PERIPHERY_TRANSFER
  • MIN_DELAY_FOR_PERIPHERY_CORE_TRANSFER
  • MIN_DELAY
  • MINIMAL_BITS
  • MINIMIZE_AREA
  • MINIMIZE_AREA_WITH_CHAINS
  • MINIMIZE_POWER_ONLY
  • MINIMUM_DELAY_REQUIREMENT
  • MINIMUM
  • MINIMUM_SEU_INTERVAL
  • MINIMUM_TPD_REQUIREMENT
  • MINIMUM_WIDTH_CLOCK_ENABLE
  • MINIMUM_WIDTH_SLOAD_SCLEAR
  • MIN_MTBF_REQUIREMENT
  • MIN_TCO_REQUIREMENT
  • MIN_TPD_REQUIREMENT
  • MINUS_DELTA10
  • MINUS_DELTA11
  • MINUS_DELTA12
  • MINUS_DELTA13
  • MINUS_DELTA14
  • MINUS_DELTA15
  • MINUS_DELTA1
  • MINUS_DELTA2
  • MINUS_DELTA3
  • MINUS_DELTA4
  • MINUS_DELTA5
  • MINUS_DELTA6
  • MINUS_DELTA7
  • MINUS_DELTA8
  • MINUS_DELTA9
  • MIN_WIRES_FOR_CORE_PERIPHERY_TRANSFER
  • MIN_WIRES_FOR_PERIPHERY_CORE_TRANSFER
  • MISC_FILE
  • MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE
  • MLAB
  • MLAB_TIMING_CONSTRAINTS_IN_FEED_THROUGH_DONT_CARE_MODE
  • MODE_0
  • MODE_10
  • MODE_11
  • MODE_12
  • MODE_13
  • MODE_14
  • MODE_15
  • MODE_1
  • MODE_2
  • MODE_3
  • MODE_4
  • MODE_5
  • MODE_6
  • MODE_7
  • MODE_8
  • MODE_9
  • MODE_DEFAULT
  • MODEL_1
  • MODEL_2
  • MODEL_3
  • MODULE_BLOATING_FACTOR
  • MOVE_TO_TOP_IO
  • MP2_EXPORT_FILE
  • MULTICYCLE_HOLD
  • MULTICYCLE
  • MULTIPLY_BASE_CLOCK_BY
  • MULTIPLY_BASE_CLOCK_PERIOD_BY
  • MULTITAP_FILE
  • MUX_RESTRUCTURE
  • MUX_USE_ROUTING_ASSIGNMENT
  • NCEO_OPEN_DRAIN
  • NCEO_RESERVED_CYCLONEII
  • NCEO_RESERVED
  • NCE_PIN
  • NDQS_LOCAL_CLOCK_DELAY_CHAIN
  • NEAR_END
  • NEAR_GLOBAL_CLOCK
  • NEAR_REGIONAL_CLOCK
  • NEGATIVE_180
  • NEGATIVE_90
  • NEGATIVE_EDGE
  • NETLIST_ONLY
  • NETLIST_VIEWER_ASSIGNMENT
  • NETO_ASSIGNMENT
  • NEVER_ALLOW
  • NEVER
  • NEVER_REGENERATE_IP
  • NEVER_REGENERATE_IP_SIM
  • NEW_EXTRACTOR
  • NO_AUTO_INST_DISCOVERY
  • NO_BACK_ANNOTATION
  • NO_BYTE_ENABLE
  • NO_DC_GAIN
  • NO_GLOBAL_ROUTE
  • NOMINAL_CORE_SUPPLY_VOLTAGE
  • NONDEFAULT_LIBS
  • NONE
  • NON_LOCAL
  • NON_QPI_MODE
  • NON_S1_MODE
  • NONSYNCHSTRUCT_CAT
  • NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE
  • NONSYNCHSTRUCT_RULE_COMBLOOP
  • NONSYNCHSTRUCT_RULE_DELAY_CHAIN
  • NONSYNCHSTRUCT_RULE_DLATCH
  • NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN
  • NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED
  • NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR
  • NONSYNCHSTRUCT_RULE_REG_LOOP
  • NONSYNCHSTRUCT_RULE_RIPPLE_CLK
  • NONSYNCHSTRUCT_RULE_SRLATCH
  • NORMAL_COMPILATION
  • NORMAL_LCELL_INSERT
  • NORMAL
  • NO_SDC_PROMOTION
  • NOT_A_CLOCK
  • NOT_BOOST
  • NOT_CLOCK
  • NOT_GATE_PUSH_BACK
  • NO_TO_OPTION_REQUIRED
  • NOT_USED
  • NO_VOLTAGE_BOOST
  • NTFQ_MSG_ACF_ASSIGNMENTS_CHANGED
  • NUMBER_OF_DESTINATION_TO_REPORT
  • NUMBER_OF_EXAMPLE_NODES_REPORTED
  • NUMBER_OF_INVERTED_REGISTERS_REPORTED
  • NUMBER_OF_PATHS_TO_REPORT
  • NUMBER_OF_PROTECTED_REGISTERS_REPORTED
  • NUMBER_OF_REMOVED_REGISTERS_REPORTED
  • NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT
  • NUMBER_OF_SWEPT_NODES_REPORTED
  • NUMBER_OF_SYNTHESIS_MIGRATION_ROWS
  • NUM_PARALLEL_PROCESSORS
  • NWS_NRS_NCS_CS_RESERVED
  • OBJECT_FILE
  • OBSAI_1536
  • OBSAI_3072
  • OBSAI_6144
  • OBSAI_768
  • OBSERVABLE
  • OCP_AUTO_PARTITION
  • OCP_FILE
  • OCP_HW_EVAL
  • OCP_PARTITION
  • OCP_TIMEOUT_PARTITION
  • OCT_100_OHMS
  • OCT_120_OHMS
  • OCT_150_OHMS
  • OCT_AND_IMPEDANCE_MATCHING_CYCLONEII
  • OCT_AND_IMPEDANCE_MATCHING
  • OCT_AND_IMPEDANCE_MATCHING_STRATIXII
  • OCT_CONTROL_BLOCK
  • OCT_REGISTER
  • OE_DELAY_CHAIN
  • OE_DELAY
  • OE_OPTION
  • OFFSET_FROM_BASE_CLOCK
  • OFFSET_MAIN
  • OFFSET_PO1
  • OFFSET_PRE
  • ON_CHIP_BITSTREAM_DECOMPRESSION
  • ONE_HOT
  • OPTIMISTIC
  • OPTIMIZATION_MODE
  • OPTIMIZATION_TECHNIQUE_APEX20K
  • OPTIMIZATION_TECHNIQUE_ARMSTRONG
  • OPTIMIZATION_TECHNIQUE_CYCLONEII
  • OPTIMIZATION_TECHNIQUE_CYCLONE
  • OPTIMIZATION_TECHNIQUE_DALI
  • OPTIMIZATION_TECHNIQUE_FLEX10K
  • OPTIMIZATION_TECHNIQUE_FLEX6K
  • OPTIMIZATION_TECHNIQUE
  • OPTIMIZATION_TECHNIQUE_MAX7000
  • OPTIMIZATION_TECHNIQUE_TSUNAMI
  • OPTIMIZATION_TECHNIQUE_YEAGER
  • OPTIMIZED_EFFORT
  • OPTIMIZE_FAST_CORNER_TIMING
  • OPTIMIZE_FOR_METASTABILITY
  • OPTIMIZE_HOLD_TIMING
  • OPTIMIZE_INTERNAL_TIMING
  • OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING
  • OPTIMIZE_IO_TIMING
  • OPTIMIZE_MULTI_CORNER_TIMING
  • OPTIMIZE_NETLIST_FOR_ROUTABILITY
  • OPTIMIZE_PERSONA_ROUTABILITY
  • OPTIMIZE_POWER_DURING_FITTING
  • OPTIMIZE_POWER_DURING_SYNTHESIS
  • OPTIMIZE_SIGNAL_INTEGRITY
  • OPTIMIZE_SSN
  • OPTIMIZE_TIMING
  • OPTIONS_FOR_ENTITIES_ONLY
  • OPTIONS_FOR_INDIVIDUAL_NODES_ONLY
  • OPTIONS_FOR_NODES_AND_ENTITIES
  • ORIGINAL_INTERFACE_PORT_NAME
  • ORIGINAL_QUARTUS_VERSION
  • ORIGINATING_COMPANION_REVISION
  • OSC_CLK_1_100MHZ
  • OSC_CLK_1_125MHZ
  • OSC_CLK_1_25MHZ
  • OTHER_APF_RESERVED
  • OTHER
  • OTP_AUTO_PARTITION
  • OTP_PARTITION
  • OUTPUT_BUFFER_DELAY_CONTROL
  • OUTPUT_BUFFER_DELAY
  • OUTPUT_DELAY_CHAIN
  • OUTPUT_DELAY
  • OUTPUT_ENABLE_DELAY
  • OUTPUT_ENABLE_GROUP
  • OUTPUT_ENABLE_REGISTER_DUPLICATION
  • OUTPUT_ENABLE_REGISTER
  • OUTPUT_ENABLE_ROUTING
  • OUTPUT_FILE_NAME
  • OUTPUT_IO_TIMING_ENDPOINT
  • OUTPUT_IO_TIMING_FAR_END_VMEAS
  • OUTPUT_IO_TIMING_NEAR_END_VMEAS
  • OUTPUT
  • OUTPUT_MAX_DELAY
  • OUTPUT_MIN_DELAY
  • OUTPUT_OCT_VALUE
  • OUTPUT_PIN_C_FAR
  • OUTPUT_PIN_C_NEAR
  • OUTPUT_PIN_C_PER_LENGTH
  • OUTPUT_PIN_LENGTH
  • OUTPUT_PIN_LOAD
  • OUTPUT_PIN_L_PER_LENGTH
  • OUTPUT_PIN_R_FAR_HIGH
  • OUTPUT_PIN_R_FAR_LOW
  • OUTPUT_PIN_R_FAR_SERIES
  • OUTPUT_PIN_R_NEAR_HIGH
  • OUTPUT_PIN_R_NEAR_LOW
  • OUTPUT_PIN_R_NEAR_SERIES
  • OUTPUT_PIN_V_TERMINATION
  • OUTPUT_REGISTER
  • OUTPUT_TERMINATION
  • OUTPUT_TYPE
  • OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS
  • OWNED_BY_UPPER_PARTITION
  • P0H9
  • P0L9
  • PACKAGE_SKEW_COMPENSATION
  • PACK_ALL_IO_REGISTERS
  • PAD_TO_CORE_DELAY
  • PAD_TO_DDIO_REGISTER_DELAY
  • PAD_TO_INPUT_REGISTER_DELAY
  • PARALLEL_50_OHMS_WITH_CALIBRATION
  • PARALLEL_EXPANDER_CHAIN_LENGTH
  • PARALLEL
  • PARALLEL_SYNTHESIS
  • PARAMETER_ARRAY
  • PARAMETER_BOOL
  • PARAMETER_CHAR
  • PARAMETER_ENUM
  • PARAMETER
  • PARAMETER_PHYSICAL
  • PARAMETER_SIGNED_BIN
  • PARAMETER_SIGNED_DEC
  • PARAMETER_SIGNED_FLOAT
  • PARAMETER_SIGNED_HEX
  • PARAMETER_SIGNED_OCT
  • PARAMETERS
  • PARAMETER_STRING
  • PARAMETER_UNKNOWN
  • PARAMETER_UNSIGNED_BIN
  • PARAMETER_UNSIGNED_DEC
  • PARAMETER_UNSIGNED_FLOAT
  • PARAMETER_UNSIGNED_HEX
  • PARAMETER_UNSIGNED_OCT
  • PARAMETER_UNSIZED_BIT_LITERAL
  • PARTIAL_RECONFIGURATION_PARTITION
  • PARTIAL_SRAM_OBJECT_FILE
  • PARTITION_ALWAYS_USE_QXP_NETLIST
  • PARTITION_ASD_REGION_ID
  • PARTITION_ASD_REGION
  • PARTITION_BACK_ANNOTATION
  • PARTITION_COLOR
  • PARTITION_COLOUR
  • PARTITION_ENABLE_STRICT_PRESERVATION
  • PARTITION_EXTRACT_HARD_BLOCK_NODES
  • PARTITION_FITTER_PRESERVATION_LEVEL
  • PARTITION_HIERARCHY
  • PARTITION_IGNORE_SOURCE_FILE_CHANGES
  • PARTITION_IMPORT_ASSIGNMENTS
  • PARTITION_IMPORT_EXISTING_ASSIGNMENTS
  • PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS
  • PARTITION_IMPORT_FILE
  • PARTITION_IMPORT_NEW_ASSIGNMENTS
  • PARTITION_IMPORT_PIN_ASSIGNMENTS
  • PARTITION_IMPORT_PROMOTE_ASSIGNMENTS
  • PARTITION_LAST_IMPORTED_FILE
  • PARTITION
  • PARTITION_NETLIST_TYPE
  • PARTITION_ONLY
  • PARTITION_PRESERVE_HIGH_SPEED_TILES
  • PARTITION_SOURCE
  • PARTITION_TYPE
  • PASSIVE_PARALLEL_ASYNCHRONOUS
  • PASSIVE_PARALLEL_SYNCHRONOUS
  • PASSIVE_PARALLEL_X16
  • PASSIVE_PARALLEL_X32
  • PASSIVE_PARALLEL_X8
  • PASSIVE_PROGRAMMING_FILE_NAME
  • PASSIVE_RESISTOR
  • PASSIVE_SERIAL_ASYNCHRONOUS
  • PASSIVE_SERIAL
  • PBIP_FILE
  • PCB_LAYERS
  • PCIE_CABLE
  • PCIE_GEN1_3P5DB
  • PCIE_GEN1
  • PCIE_GEN2_3P5DB
  • PCIE_GEN2_6DB
  • PCIE_GEN2
  • PCIE_GEN3
  • PCIE_PRE_EMPH_GEN1
  • PCIE_PRE_EMPH_GEN2_3_5DB_DEEMPH
  • PCIE_PRE_EMPH_GEN2_6DB_DEEMPH
  • PCIE_PRE_EMPH_GEN2_LOW_MARGIN
  • PCIE_PRE_EMPH_GEN2_LOW_SWING
  • PCIE_VOD_GEN1
  • PCIE_VOD_GEN2_3_5DB_DEEMPH
  • PCIE_VOD_GEN2_6DB_DEEMPH
  • PCIE_VOD_GEN2_LOW_MARGIN
  • PCIE_VOD_GEN2_LOW_SWING
  • PCI_IO
  • PDC_FILE
  • PERIPHERAL
  • PERIPHERY_CLOCK
  • PERIPHERY_REUSE_CORE
  • PERIPHERY_SEED
  • PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION
  • PERIPH_FITTER_SCRIPT
  • PERIPH_REPORT_SCRIPT
  • PERSONA_FILE
  • PESSIMISTIC
  • PEXP_LENGTH
  • PEXP_LENGTH_MAX7000
  • PHASE_FROM_BASE_CLOCK
  • PHASE_OF_0_DEGREES
  • PHASE_OF_72_DEGREES
  • PHASE_OF_90_DEGREES
  • PHYSICAL_SHIFT_REGISTER_INFERENCE
  • PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING_DISABLE_DESTINATION_CHECK
  • PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING
  • PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING_REG_REACH
  • PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA
  • PHYSICAL_SYNTHESIS_COMBO_LOGIC
  • PHYSICAL_SYNTHESIS_EFFORT
  • PHYSICAL_SYNTHESIS
  • PHYSICAL_SYNTHESIS_LOG_FILE
  • PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA
  • PHYSICAL_SYNTHESIS_PIPELINE
  • PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION
  • PHYSICAL_SYNTHESIS_REGISTER_RETIMING
  • PIN_CONNECT_FROM_NODE
  • PIN_FILE
  • PIN_PLANNER_DISPLAY_ASSIGNMENT_VALUE_FROM_POSITIVE_PIN_TO_NEGATIVE_PIN
  • PIN_PLANNER_FILE
  • PIN_PLANNER_GROUP_EXCEPTION
  • PIN_PLANNER_GROUP_MEMBER
  • PIN_PLANNER_GROUP_SETTINGS
  • PLACEMENT_AND_ROUTING_AND_HIGH_SPEED_TILE
  • PLACEMENT_AND_ROUTING_AND_HIGH_SPEED_TILES
  • PLACEMENT_AND_ROUTING_AND_TILE
  • PLACEMENT_AND_ROUTING
  • PLACEMENT_EFFORT_MULTIPLIER
  • PLACEMENT
  • PLACE_REGION
  • PLD_TO_STRIPE_INTERRUPTS_EPXA4_10
  • PLL_APLLY_PFD_ISSUE_WORKAROUND
  • PLL_AUTO_RESET
  • PLL_BANDWIDTH_PRESET
  • PLL_C_COUNTER_DELAY_CHAIN
  • PLL_CHANNEL_SPACING
  • PLL_COMPENSATE
  • PLL_COMPENSATION_MODE
  • PLL_DISABLE_COUNTER_SETTINGS_OPTIMIZATION
  • PLL_ENFORCE_USER_PHASE_SHIFT
  • PLL_EXTERNAL_FEEDBACK_BOARD_DELAY
  • PLL_FEEDBACK_CLOCK_SIGNAL
  • PLL_FORCE_OUTPUT_COUNTER_HARDCOPY_REPLAY
  • PLL_FORCE_OUTPUT_COUNTER
  • PLL_IGNORE_MIGRATION_DEVICES
  • PLL_LOCK_10K
  • PLL_LOCK
  • PLL_LVDS_DELAY_CHAIN
  • PLL_OPTIMIZE_PHASE_SHIFT_FOR_TIMING
  • PLL_OUTPUT_CLOCK_FREQUENCY
  • PLL_PFD_CLOCK_FREQUENCY
  • PLL_PHASE_RECONFIG_COUNTER_REMAP_LCELL
  • PLL_PRE_C_COUNTER_DELAY_CHAIN
  • PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL
  • PLL_TYPE
  • PLL_VCO_CLOCK_FREQUENCY
  • PLUS_DELTA10
  • PLUS_DELTA11
  • PLUS_DELTA12
  • PLUS_DELTA13
  • PLUS_DELTA14
  • PLUS_DELTA15
  • PLUS_DELTA1
  • PLUS_DELTA2
  • PLUS_DELTA3
  • PLUS_DELTA4
  • PLUS_DELTA5
  • PLUS_DELTA6
  • PLUS_DELTA7
  • PLUS_DELTA8
  • PLUS_DELTA9
  • PMBUS_MASTER
  • PMBUS_SLAVE
  • POF_VERIFY_PROTECT
  • POR_SCHEME
  • POSITIVE_180
  • POSITIVE_90
  • POSITIVE_EDGE
  • POST_BUILD_COMMAND_LINE
  • POST_CONFIG
  • POST_FIT_CONNECT_FROM_SLD_NODE_ENTITY_PORT
  • POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT
  • POST_FIT
  • POST_FIT_WITH_ROUTING
  • POST_FLOW_SCRIPT_FILE
  • POST_MAPPING_RESYNTHESIS
  • POST_MODULE_SCRIPT_FILE
  • POST_SYNTH
  • POWER_APPLY_THERMAL_MARGIN
  • POWER_AUTO_COMPUTE_TJ
  • POWER_BOARD_TEMPERATURE
  • POWER_BOARD_THERMAL_MODEL
  • POWER_COOLING_FOR_MAX_TJ
  • POWER_DEFAULT_INPUT_IO_TOGGLE_RATE
  • POWER_DEFAULT_TOGGLE_RATE
  • POWER_ESTIMATION_ASSIGNMENT
  • POWER_ESTIMATION_END_TIME
  • POWER_ESTIMATION_START_TIME
  • POWER_GLITCH_FACTOR
  • POWER_HPS_DYNAMIC_POWER_DUAL
  • POWER_HPS_DYNAMIC_POWER_SINGLE
  • POWER_HPS_ENABLE
  • POWER_HPS_JUNCTION_TEMPERATURE
  • POWER_HPS_PROC_FREQ
  • POWER_HPS_STATIC_POWER
  • POWER_HPS_TOTAL_POWER
  • POWER_HSSI_LEFT
  • POWER_HSSI
  • POWER_HSSI_RIGHT
  • POWER_HSSI_VCCHIP_LEFT
  • POWER_HSSI_VCCHIP_RIGHT
  • POWER_INPUT_FILE
  • POWER_INPUT_FILE_NAME
  • POWER_INPUT_FILE_SETTINGS
  • POWER_INPUT_FILE_TYPE
  • POWER
  • POWER_MAX_TJ_VALUE
  • POWER_OCS_VALUE
  • POWER_OJB_VALUE
  • POWER_OJC_VALUE
  • POWER_OSA_VALUE
  • POWER_OUTPUT_SAF_NAME
  • POWER_PRESET_COOLING_SOLUTION
  • POWER_READ_INPUT_FILE
  • POWER_REPORT_POWER_DISSIPATION
  • POWER_REPORT_SIGNAL_ACTIVITY
  • POWER_STATIC_PROBABILITY
  • POWER_STATIC_TOGGLE_RATE
  • POWER_TJ_VALUE
  • POWER_TOGGLE_RATE
  • POWER_TOGGLE_RATE_PERCENTAGE
  • POWER_UP_HIGH
  • POWER_UP_LEVEL
  • POWER_USE_CUSTOM_COOLING_SOLUTION
  • POWER_USE_DEVICE_CHARACTERISTICS
  • POWER_USE_INPUT_FILES
  • POWER_USE_PVA
  • POWER_USE_TA_VALUE
  • POWER_USE_VOLTAGE
  • POWER_VCCA_FPLL_USER_VOLTAGE
  • POWER_VCCA_GTBR_USER_VOLTAGE
  • POWER_VCCA_GTB_USER_VOLTAGE
  • POWER_VCCA_GXBL_USER_OPTION
  • POWER_VCCA_GXBL_USER_VOLTAGE
  • POWER_VCCA_GXBR_USER_OPTION
  • POWER_VCCA_GXBR_USER_VOLTAGE
  • POWER_VCCA_GXB_USER_OPTION
  • POWER_VCCA_GXB_USER_VOLTAGE
  • POWER_VCCA_L_USER_OPTION
  • POWER_VCCA_L_USER_VOLTAGE
  • POWER_VCCA_PLL_USER_VOLTAGE
  • POWER_VCCA_R_USER_OPTION
  • POWER_VCCA_R_USER_VOLTAGE
  • POWER_VCCA_USER_VOLTAGE
  • POWER_VCCAUX_SHARED_USER_VOLTAGE
  • POWER_VCCAUX_USER_OPTION
  • POWER_VCCAUX_USER_VOLTAGE
  • POWER_VCCBAT_USER_VOLTAGE
  • POWER_VCCCB_USER_OPTION
  • POWER_VCCCB_USER_VOLTAGE
  • POWER_VCCD_FPLL_USER_VOLTAGE
  • POWER_VCCD_PLL_USER_VOLTAGE
  • POWER_VCCD_USER_VOLTAGE
  • POWER_VCCE_GXBL_USER_VOLTAGE
  • POWER_VCCE_GXBR_USER_VOLTAGE
  • POWER_VCCE_GXB_USER_VOLTAGE
  • POWER_VCCEH_GXBL_USER_VOLTAGE
  • POWER_VCCEH_GXBR_USER_VOLTAGE
  • POWER_VCCEH_GXB_USER_VOLTAGE
  • POWER_VCCERAM_USER_VOLTAGE
  • POWER_VCCE_USER_VOLTAGE
  • POWER_VCCH_GTBR_USER_VOLTAGE
  • POWER_VCCH_GTB_USER_VOLTAGE
  • POWER_VCCH_GXBL_USER_OPTION
  • POWER_VCCH_GXBL_USER_VOLTAGE
  • POWER_VCCH_GXBR_USER_OPTION
  • POWER_VCCH_GXBR_USER_VOLTAGE
  • POWER_VCCH_GXB_USER_OPTION
  • POWER_VCCH_GXB_USER_VOLTAGE
  • POWER_VCCHIP_L_USER_VOLTAGE
  • POWER_VCCHIP_R_USER_VOLTAGE
  • POWER_VCCHIP_USER_VOLTAGE
  • POWER_VCCH_L_USER_VOLTAGE
  • POWER_VCC_HPS_USER_VOLTAGE
  • POWER_VCCH_R_USER_VOLTAGE
  • POWER_VCCHSSI_L_USER_VOLTAGE
  • POWER_VCCHSSI_R_USER_VOLTAGE
  • POWER_VCCINT_USER_VOLTAGE
  • POWER_VCCIO_HPS_USER_VOLTAGE
  • POWER_VCCIOREF_HPS_USER_VOLTAGE
  • POWER_VCCIO_USER_OPTION
  • POWER_VCCIO_USER_VOLTAGE
  • POWER_VCCL_GTBL_USER_VOLTAGE
  • POWER_VCCL_GTBR_USER_VOLTAGE
  • POWER_VCCL_GTB_USER_VOLTAGE
  • POWER_VCCL_GXBL_USER_VOLTAGE
  • POWER_VCCL_GXBR_USER_VOLTAGE
  • POWER_VCCL_GXB_USER_OPTION
  • POWER_VCCL_GXB_USER_VOLTAGE
  • POWER_VCCL_HPS_USER_VOLTAGE
  • POWER_VCCL_USER_VOLTAGE
  • POWER_VCCPD_USER_OPTION
  • POWER_VCCPD_USER_VOLTAGE
  • POWER_VCCPGM_USER_VOLTAGE
  • POWER_VCCPLL_HPS_USER_VOLTAGE
  • POWER_VCCPT_USER_VOLTAGE
  • POWER_VCCP_USER_VOLTAGE
  • POWER_VCCR_GTBL_USER_VOLTAGE
  • POWER_VCCR_GTBR_USER_VOLTAGE
  • POWER_VCCR_GTB_USER_VOLTAGE
  • POWER_VCCR_GXBL_USER_OPTION
  • POWER_VCCR_GXBL_USER_VOLTAGE
  • POWER_VCCR_GXBR_USER_OPTION
  • POWER_VCCR_GXBR_USER_VOLTAGE
  • POWER_VCCR_GXB_USER_OPTION
  • POWER_VCCR_GXB_USER_VOLTAGE
  • POWER_VCCR_L_USER_VOLTAGE
  • POWER_VCCR_R_USER_VOLTAGE
  • POWER_VCCRSTCLK_HPS_USER_VOLTAGE
  • POWER_VCCR_USER_VOLTAGE
  • POWER_VCCT_GTBL_USER_VOLTAGE
  • POWER_VCCT_GTBR_USER_VOLTAGE
  • POWER_VCCT_GTB_USER_VOLTAGE
  • POWER_VCCT_GXBL_USER_OPTION
  • POWER_VCCT_GXBL_USER_VOLTAGE
  • POWER_VCCT_GXBR_USER_OPTION
  • POWER_VCCT_GXBR_USER_VOLTAGE
  • POWER_VCCT_GXB_USER_OPTION
  • POWER_VCCT_GXB_USER_VOLTAGE
  • POWER_VCCT_L_USER_VOLTAGE
  • POWER_VCCT_R_USER_VOLTAGE
  • POWER_VCCT_USER_VOLTAGE
  • POWER_VCC_USER_VOLTAGE
  • POWER_VCD_FILE_END_TIME
  • POWER_VCD_FILE_START_TIME
  • POWER_VCD_FILTER_GLITCHES
  • POWER_WILDCARDS
  • PPF_FILE
  • PPLQ_GROUP_EXCEPTION
  • PPLQ_GROUP
  • PPLQ_GROUP_MEMBER
  • PR_ALLOW_GLOBAL_LIMS
  • PR_BASE
  • PR_BASE_MSF
  • PR_BASE_SOF
  • PR_DONE_OPEN_DRAIN
  • PRE_CONFIG
  • PRE_FLOW_SCRIPT_FILE
  • PRE_MAPPING_RESYNTHESIS
  • PR_ERROR_OPEN_DRAIN
  • PRESERVED_HANGING_NODES
  • PRESERVE_FANOUT_FREE_NODE
  • PRESERVE_FANOUT_FREE_WYSIWYG
  • PRESERVE_HIERARCHICAL_BOUNDARY
  • PRESERVE
  • PRESERVE_PLL_COUNTER_ORDER
  • PRESERVE_PORT_NAME
  • PRESERVE_REGISTER
  • PRESERVE_REGISTER_SYN_ONLY
  • PRESERVE_SYNONYMS
  • PRESERVE_UNUSED_XCVR_CHANNEL
  • PR_IMPL
  • PRINT_DEBUG_MSG_AND_EXIT
  • PRIORITY_SEU_AREA
  • PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10
  • PROCESSOR
  • PRODUCT_TERM
  • PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES
  • PROGRAMMABLE_POWER_TECHNOLOGY_SETTING
  • PROGRAMMABLE_PREEMPHASIS
  • PROGRAMMABLE_VOD
  • PROGRAMMER_ASSIGNMENT
  • PROGRAMMER_OBJECT_FILE
  • PROGRAMMING_BITSTREAM_ENCRYPTION_KEY_SELECT
  • PROGRAMMING_BITSTREAM_ENCRYPTION_UPDATE_RATIO
  • PROGRAMMING_FILE_TYPE
  • PROGRAMMING_MODE_APEX20KF
  • PROGRAMMING_MODE_APEX20K
  • PROGRAMMING_MODE_ARMSTRONG
  • PROGRAMMING_MODE_CUDA
  • PROGRAMMING_MODE_CYCLONEII
  • PROGRAMMING_MODE_DALI
  • PROGRAMMING_MODE_EXCALIBUR
  • PROGRAMMING_MODE_FLEX10K
  • PROGRAMMING_MODE_FLEX6K
  • PROGRAMMING_MODE
  • PROGRAMMING_MODE_TITAN
  • PROGRAMMING_MODE_TORNADO
  • PROGRAMMING_MODE_YEAGER
  • PROGRAMMING_MODE_ZIPPLEBACK
  • PROJECT_ASSIGNMENT
  • PROJECT_CREATION_TIME_DATE
  • PROJECT_INFO
  • PROJECT_IP_GEN_PARALLEL_ENABLED
  • PROJECT_IP_GEN_SIM_FILESETS_WITH_SYNTHESIS
  • PROJECT_IP_REGENERATION_POLICY
  • PROJECT_IP_SEARCH_PATHS
  • PROJECT_IP_SIM_REGENERATION_POLICY
  • PROJECT_MIGRATION_TIMESTAMP
  • PROJECT_OUTPUT_DIRECTORY
  • PROJECT_SHOW_ENTITY_NAME
  • PROJECT_SOURCE_FILE
  • PROJECT_THUNDER_BAY
  • PROJECT_USE_SIMPLIFIED_NAMES
  • PRO_ONLY
  • PROPAGATE_CONSTANTS_ON_INPUTS
  • PROPAGATE_INVERSIONS_ON_INPUTS
  • PR_PARTITION
  • PR_PINS_OPEN_DRAIN
  • PRPOF_ID_CHECK
  • PRPOF_ID
  • PRPOF_ID_VALUE
  • PR_READY_OPEN_DRAIN
  • PR_SECURITY_VALIDATION
  • PR_SKIP_BASE_CHECK
  • PR_SYN
  • PULL_DN
  • PULLDOWN_DRIVE_STRENGTH_BITS
  • PULL_DOWN
  • PULL_RESISTOR
  • PULLUP_DRIVE_STRENGTH_BITS
  • PULL_UP
  • PULL_UP_TO_VCCELA
  • PULSE_WIDTH_0
  • PULSE_WIDTH_1
  • PULSE_WIDTH_2_LARGE
  • PULSE_WIDTH_2
  • PULSE_WIDTH_NONE
  • PWRMGT_ADV_CLOCK_DATA_FALL_TIME
  • PWRMGT_ADV_CLOCK_DATA_RISE_TIME
  • PWRMGT_ADV_DATA_HOLD_TIME
  • PWRMGT_ADV_DATA_SETUP_TIME
  • PWRMGT_ADV_FPGA_RELEASE_DELAY
  • PWRMGT_ADV_INITIAL_DELAY
  • PWRMGT_ADV_VOLTAGE_STABLE_DELAY
  • PWRMGT_ADV_VOUT_READING_ERR_MARGIN
  • PWRMGT_BUS_SPEED_MODE
  • PWRMGT_DEVICE_ADDRESS_IN_PMBUS_SLAVE_MODE
  • PWRMGT_DIRECT_FORMAT_COEFFICIENT_B
  • PWRMGT_DIRECT_FORMAT_COEFFICIENT_M
  • PWRMGT_DIRECT_FORMAT_COEFFICIENT_R
  • PWRMGT_LINEAR_FORMAT_N
  • PWRMGT_PAGE_COMMAND_ENABLE
  • PWRMGT_SLAVE_DEVICE0_ADDRESS
  • PWRMGT_SLAVE_DEVICE1_ADDRESS
  • PWRMGT_SLAVE_DEVICE2_ADDRESS
  • PWRMGT_SLAVE_DEVICE3_ADDRESS
  • PWRMGT_SLAVE_DEVICE4_ADDRESS
  • PWRMGT_SLAVE_DEVICE5_ADDRESS
  • PWRMGT_SLAVE_DEVICE6_ADDRESS
  • PWRMGT_SLAVE_DEVICE7_ADDRESS
  • PWRMGT_SLAVE_DEVICE_TYPE
  • PWRMGT_TABLE_VERSION
  • PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT
  • PWRMGT_VOLTAGE_OUTPUT_FORMAT
  • QAR_FILE
  • QARLOG_FILE
  • QDB_FILE
  • QDB_FILE_PARTITION
  • QDB_PATH
  • QDFS_USE_CHERRY
  • QDR_D_PIN_GROUP
  • QHD_MODE
  • QIC_EXPORT_FILE
  • QIC_EXPORT_FLATTEN
  • QIC_EXPORT_NETLIST_TYPE
  • QIC_EXPORT_PARTITION_NAME
  • QIC_EXPORT_ROUTING
  • QIC_USE_BINARY_DATABASES
  • QID_ASSIGNMENT
  • QII_AUTO_PACKED_REGISTERS
  • QIP_FILE
  • QKY_FILE
  • QPI_MODE
  • QSGMII_5000
  • QSYS_FILE
  • QUARTUS_ACF_FILE
  • QUARTUS_COMPILER_SETTINGS_FILE
  • QUARTUS_ENTITY_SETTINGS_FILE
  • QUARTUS_GUI_SIGNATURE_ID
  • QUARTUSII
  • QUARTUS_PROJECT_FILE
  • QUARTUS_PROJECT_SETTINGS_FILE
  • QUARTUS_PTF_FILE
  • QUARTUS_SBD_FILE
  • QUARTUS_SIMULATOR_SETTINGS_FILE
  • QUARTUS_SOFTWARE_SETTINGS_FILE
  • QUARTUS_STANDARD_DELAY_FILE
  • QUARTUS_WORKSPACE_FILE
  • QVAR_FILE
  • QXP_FILE
  • R_ADAPT_DFE_CONTROL_SEL_0
  • R_ADAPT_DFE_CONTROL_SEL_1
  • R_ADAPT_DFE_CONTROL_SEL_2
  • R_ADAPT_DFE_CONTROL_SEL_3
  • R_ADAPT_DFE_SEL_0
  • R_ADAPT_DFE_SEL_1
  • R_ADAPT_VGA_SEL_0
  • R_ADAPT_VGA_SEL_1
  • R_ADAPT_VREF_SEL_0
  • R_ADAPT_VREF_SEL_1
  • R_ADAPT_VREF_SEL_2
  • R_ADAPT_VREF_SEL_3
  • RADP_CTLE_ACGAIN_4S_0
  • RADP_CTLE_ACGAIN_4S_10
  • RADP_CTLE_ACGAIN_4S_11
  • RADP_CTLE_ACGAIN_4S_12
  • RADP_CTLE_ACGAIN_4S_13
  • RADP_CTLE_ACGAIN_4S_14
  • RADP_CTLE_ACGAIN_4S_15
  • RADP_CTLE_ACGAIN_4S_16
  • RADP_CTLE_ACGAIN_4S_17
  • RADP_CTLE_ACGAIN_4S_18
  • RADP_CTLE_ACGAIN_4S_19
  • RADP_CTLE_ACGAIN_4S_1
  • RADP_CTLE_ACGAIN_4S_20
  • RADP_CTLE_ACGAIN_4S_21
  • RADP_CTLE_ACGAIN_4S_22
  • RADP_CTLE_ACGAIN_4S_23
  • RADP_CTLE_ACGAIN_4S_24
  • RADP_CTLE_ACGAIN_4S_25
  • RADP_CTLE_ACGAIN_4S_26
  • RADP_CTLE_ACGAIN_4S_27
  • RADP_CTLE_ACGAIN_4S_28
  • RADP_CTLE_ACGAIN_4S_2
  • RADP_CTLE_ACGAIN_4S_3
  • RADP_CTLE_ACGAIN_4S_4
  • RADP_CTLE_ACGAIN_4S_5
  • RADP_CTLE_ACGAIN_4S_6
  • RADP_CTLE_ACGAIN_4S_7
  • RADP_CTLE_ACGAIN_4S_8
  • RADP_CTLE_ACGAIN_4S_9
  • RADP_CTLE_EQZ_1S_SEL_0
  • RADP_CTLE_EQZ_1S_SEL_10
  • RADP_CTLE_EQZ_1S_SEL_11
  • RADP_CTLE_EQZ_1S_SEL_12
  • RADP_CTLE_EQZ_1S_SEL_13
  • RADP_CTLE_EQZ_1S_SEL_14
  • RADP_CTLE_EQZ_1S_SEL_15
  • RADP_CTLE_EQZ_1S_SEL_1
  • RADP_CTLE_EQZ_1S_SEL_2
  • RADP_CTLE_EQZ_1S_SEL_3
  • RADP_CTLE_EQZ_1S_SEL_4
  • RADP_CTLE_EQZ_1S_SEL_5
  • RADP_CTLE_EQZ_1S_SEL_6
  • RADP_CTLE_EQZ_1S_SEL_7
  • RADP_CTLE_EQZ_1S_SEL_8
  • RADP_CTLE_EQZ_1S_SEL_9
  • RADP_DFE_FLTAP_POSITION_0
  • RADP_DFE_FLTAP_POSITION_10
  • RADP_DFE_FLTAP_POSITION_11
  • RADP_DFE_FLTAP_POSITION_12
  • RADP_DFE_FLTAP_POSITION_13
  • RADP_DFE_FLTAP_POSITION_14
  • RADP_DFE_FLTAP_POSITION_15
  • RADP_DFE_FLTAP_POSITION_16
  • RADP_DFE_FLTAP_POSITION_17
  • RADP_DFE_FLTAP_POSITION_18
  • RADP_DFE_FLTAP_POSITION_19
  • RADP_DFE_FLTAP_POSITION_1
  • RADP_DFE_FLTAP_POSITION_20
  • RADP_DFE_FLTAP_POSITION_21
  • RADP_DFE_FLTAP_POSITION_22
  • RADP_DFE_FLTAP_POSITION_23
  • RADP_DFE_FLTAP_POSITION_24
  • RADP_DFE_FLTAP_POSITION_25
  • RADP_DFE_FLTAP_POSITION_26
  • RADP_DFE_FLTAP_POSITION_27
  • RADP_DFE_FLTAP_POSITION_28
  • RADP_DFE_FLTAP_POSITION_29
  • RADP_DFE_FLTAP_POSITION_2
  • RADP_DFE_FLTAP_POSITION_30
  • RADP_DFE_FLTAP_POSITION_31
  • RADP_DFE_FLTAP_POSITION_32
  • RADP_DFE_FLTAP_POSITION_33
  • RADP_DFE_FLTAP_POSITION_34
  • RADP_DFE_FLTAP_POSITION_35
  • RADP_DFE_FLTAP_POSITION_36
  • RADP_DFE_FLTAP_POSITION_37
  • RADP_DFE_FLTAP_POSITION_38
  • RADP_DFE_FLTAP_POSITION_39
  • RADP_DFE_FLTAP_POSITION_3
  • RADP_DFE_FLTAP_POSITION_40
  • RADP_DFE_FLTAP_POSITION_41
  • RADP_DFE_FLTAP_POSITION_42
  • RADP_DFE_FLTAP_POSITION_43
  • RADP_DFE_FLTAP_POSITION_44
  • RADP_DFE_FLTAP_POSITION_45
  • RADP_DFE_FLTAP_POSITION_46
  • RADP_DFE_FLTAP_POSITION_47
  • RADP_DFE_FLTAP_POSITION_48
  • RADP_DFE_FLTAP_POSITION_49
  • RADP_DFE_FLTAP_POSITION_4
  • RADP_DFE_FLTAP_POSITION_50
  • RADP_DFE_FLTAP_POSITION_51
  • RADP_DFE_FLTAP_POSITION_52
  • RADP_DFE_FLTAP_POSITION_53
  • RADP_DFE_FLTAP_POSITION_54
  • RADP_DFE_FLTAP_POSITION_55
  • RADP_DFE_FLTAP_POSITION_5
  • RADP_DFE_FLTAP_POSITION_6
  • RADP_DFE_FLTAP_POSITION_7
  • RADP_DFE_FLTAP_POSITION_8
  • RADP_DFE_FLTAP_POSITION_9
  • RADP_DFE_FXTAP10_0
  • RADP_DFE_FXTAP10_10
  • RADP_DFE_FXTAP10_11
  • RADP_DFE_FXTAP10_12
  • RADP_DFE_FXTAP10_13
  • RADP_DFE_FXTAP10_14
  • RADP_DFE_FXTAP10_15
  • RADP_DFE_FXTAP10_16
  • RADP_DFE_FXTAP10_17
  • RADP_DFE_FXTAP10_18
  • RADP_DFE_FXTAP10_19
  • RADP_DFE_FXTAP10_1
  • RADP_DFE_FXTAP10_20
  • RADP_DFE_FXTAP10_21
  • RADP_DFE_FXTAP10_22
  • RADP_DFE_FXTAP10_23
  • RADP_DFE_FXTAP10_24
  • RADP_DFE_FXTAP10_25
  • RADP_DFE_FXTAP10_26
  • RADP_DFE_FXTAP10_27
  • RADP_DFE_FXTAP10_28
  • RADP_DFE_FXTAP10_29
  • RADP_DFE_FXTAP10_2
  • RADP_DFE_FXTAP10_30
  • RADP_DFE_FXTAP10_31
  • RADP_DFE_FXTAP10_32
  • RADP_DFE_FXTAP10_33
  • RADP_DFE_FXTAP10_34
  • RADP_DFE_FXTAP10_35
  • RADP_DFE_FXTAP10_36
  • RADP_DFE_FXTAP10_37
  • RADP_DFE_FXTAP10_38
  • RADP_DFE_FXTAP10_39
  • RADP_DFE_FXTAP10_3
  • RADP_DFE_FXTAP10_40
  • RADP_DFE_FXTAP10_41
  • RADP_DFE_FXTAP10_42
  • RADP_DFE_FXTAP10_43
  • RADP_DFE_FXTAP10_44
  • RADP_DFE_FXTAP10_45
  • RADP_DFE_FXTAP10_46
  • RADP_DFE_FXTAP10_47
  • RADP_DFE_FXTAP10_48
  • RADP_DFE_FXTAP10_49
  • RADP_DFE_FXTAP10_4
  • RADP_DFE_FXTAP10_50
  • RADP_DFE_FXTAP10_51
  • RADP_DFE_FXTAP10_52
  • RADP_DFE_FXTAP10_53
  • RADP_DFE_FXTAP10_54
  • RADP_DFE_FXTAP10_55
  • RADP_DFE_FXTAP10_56
  • RADP_DFE_FXTAP10_57
  • RADP_DFE_FXTAP10_58
  • RADP_DFE_FXTAP10_59
  • RADP_DFE_FXTAP10_5
  • RADP_DFE_FXTAP10_60
  • RADP_DFE_FXTAP10_61
  • RADP_DFE_FXTAP10_62
  • RADP_DFE_FXTAP10_63
  • RADP_DFE_FXTAP10_6
  • RADP_DFE_FXTAP10_7
  • RADP_DFE_FXTAP10_8
  • RADP_DFE_FXTAP10_9
  • RADP_DFE_FXTAP1_0
  • RADP_DFE_FXTAP10_SGN_0
  • RADP_DFE_FXTAP10_SGN_1
  • RADP_DFE_FXTAP1_100
  • RADP_DFE_FXTAP1_101
  • RADP_DFE_FXTAP1_102
  • RADP_DFE_FXTAP1_103
  • RADP_DFE_FXTAP1_104
  • RADP_DFE_FXTAP1_105
  • RADP_DFE_FXTAP1_106
  • RADP_DFE_FXTAP1_107
  • RADP_DFE_FXTAP1_108
  • RADP_DFE_FXTAP1_109
  • RADP_DFE_FXTAP1_10
  • RADP_DFE_FXTAP11_0
  • RADP_DFE_FXTAP1_110
  • RADP_DFE_FXTAP11_10
  • RADP_DFE_FXTAP1_111
  • RADP_DFE_FXTAP11_11
  • RADP_DFE_FXTAP1_112
  • RADP_DFE_FXTAP11_12
  • RADP_DFE_FXTAP1_113
  • RADP_DFE_FXTAP11_13
  • RADP_DFE_FXTAP1_114
  • RADP_DFE_FXTAP11_14
  • RADP_DFE_FXTAP1_115
  • RADP_DFE_FXTAP11_15
  • RADP_DFE_FXTAP1_116
  • RADP_DFE_FXTAP11_16
  • RADP_DFE_FXTAP1_117
  • RADP_DFE_FXTAP11_17
  • RADP_DFE_FXTAP1_118
  • RADP_DFE_FXTAP11_18
  • RADP_DFE_FXTAP1_119
  • RADP_DFE_FXTAP11_19
  • RADP_DFE_FXTAP1_11
  • RADP_DFE_FXTAP11_1
  • RADP_DFE_FXTAP1_120
  • RADP_DFE_FXTAP11_20
  • RADP_DFE_FXTAP1_121
  • RADP_DFE_FXTAP11_21
  • RADP_DFE_FXTAP1_122
  • RADP_DFE_FXTAP11_22
  • RADP_DFE_FXTAP1_123
  • RADP_DFE_FXTAP11_23
  • RADP_DFE_FXTAP1_124
  • RADP_DFE_FXTAP11_24
  • RADP_DFE_FXTAP1_125
  • RADP_DFE_FXTAP11_25
  • RADP_DFE_FXTAP1_126
  • RADP_DFE_FXTAP11_26
  • RADP_DFE_FXTAP1_127
  • RADP_DFE_FXTAP11_27
  • RADP_DFE_FXTAP11_28
  • RADP_DFE_FXTAP11_29
  • RADP_DFE_FXTAP1_12
  • RADP_DFE_FXTAP11_2
  • RADP_DFE_FXTAP11_30
  • RADP_DFE_FXTAP11_31
  • RADP_DFE_FXTAP11_32
  • RADP_DFE_FXTAP11_33
  • RADP_DFE_FXTAP11_34
  • RADP_DFE_FXTAP11_35
  • RADP_DFE_FXTAP11_36
  • RADP_DFE_FXTAP11_37
  • RADP_DFE_FXTAP11_38
  • RADP_DFE_FXTAP11_39
  • RADP_DFE_FXTAP1_13
  • RADP_DFE_FXTAP11_3
  • RADP_DFE_FXTAP11_40
  • RADP_DFE_FXTAP11_41
  • RADP_DFE_FXTAP11_42
  • RADP_DFE_FXTAP11_43
  • RADP_DFE_FXTAP11_44
  • RADP_DFE_FXTAP11_45
  • RADP_DFE_FXTAP11_46
  • RADP_DFE_FXTAP11_47
  • RADP_DFE_FXTAP11_48
  • RADP_DFE_FXTAP11_49
  • RADP_DFE_FXTAP1_14
  • RADP_DFE_FXTAP11_4
  • RADP_DFE_FXTAP11_50
  • RADP_DFE_FXTAP11_51
  • RADP_DFE_FXTAP11_52
  • RADP_DFE_FXTAP11_53
  • RADP_DFE_FXTAP11_54
  • RADP_DFE_FXTAP11_55
  • RADP_DFE_FXTAP11_56
  • RADP_DFE_FXTAP11_57
  • RADP_DFE_FXTAP11_58
  • RADP_DFE_FXTAP11_59
  • RADP_DFE_FXTAP1_15
  • RADP_DFE_FXTAP11_5
  • RADP_DFE_FXTAP11_60
  • RADP_DFE_FXTAP11_61
  • RADP_DFE_FXTAP11_62
  • RADP_DFE_FXTAP11_63
  • RADP_DFE_FXTAP1_16
  • RADP_DFE_FXTAP11_6
  • RADP_DFE_FXTAP1_17
  • RADP_DFE_FXTAP11_7
  • RADP_DFE_FXTAP1_18
  • RADP_DFE_FXTAP11_8
  • RADP_DFE_FXTAP1_19
  • RADP_DFE_FXTAP11_9
  • RADP_DFE_FXTAP1_1
  • RADP_DFE_FXTAP11_SGN_0
  • RADP_DFE_FXTAP11_SGN_1
  • RADP_DFE_FXTAP1_20
  • RADP_DFE_FXTAP1_21
  • RADP_DFE_FXTAP1_22
  • RADP_DFE_FXTAP1_23
  • RADP_DFE_FXTAP1_24
  • RADP_DFE_FXTAP1_25
  • RADP_DFE_FXTAP1_26
  • RADP_DFE_FXTAP1_27
  • RADP_DFE_FXTAP1_28
  • RADP_DFE_FXTAP1_29
  • RADP_DFE_FXTAP1_2
  • RADP_DFE_FXTAP1_30
  • RADP_DFE_FXTAP1_31
  • RADP_DFE_FXTAP1_32
  • RADP_DFE_FXTAP1_33
  • RADP_DFE_FXTAP1_34
  • RADP_DFE_FXTAP1_35
  • RADP_DFE_FXTAP1_36
  • RADP_DFE_FXTAP1_37
  • RADP_DFE_FXTAP1_38
  • RADP_DFE_FXTAP1_39
  • RADP_DFE_FXTAP1_3
  • RADP_DFE_FXTAP1_40
  • RADP_DFE_FXTAP1_41
  • RADP_DFE_FXTAP1_42
  • RADP_DFE_FXTAP1_43
  • RADP_DFE_FXTAP1_44
  • RADP_DFE_FXTAP1_45
  • RADP_DFE_FXTAP1_46
  • RADP_DFE_FXTAP1_47
  • RADP_DFE_FXTAP1_48
  • RADP_DFE_FXTAP1_49
  • RADP_DFE_FXTAP1_4
  • RADP_DFE_FXTAP1_50
  • RADP_DFE_FXTAP1_51
  • RADP_DFE_FXTAP1_52
  • RADP_DFE_FXTAP1_53
  • RADP_DFE_FXTAP1_54
  • RADP_DFE_FXTAP1_55
  • RADP_DFE_FXTAP1_56
  • RADP_DFE_FXTAP1_57
  • RADP_DFE_FXTAP1_58
  • RADP_DFE_FXTAP1_59
  • RADP_DFE_FXTAP1_5
  • RADP_DFE_FXTAP1_60
  • RADP_DFE_FXTAP1_61
  • RADP_DFE_FXTAP1_62
  • RADP_DFE_FXTAP1_63
  • RADP_DFE_FXTAP1_64
  • RADP_DFE_FXTAP1_65
  • RADP_DFE_FXTAP1_66
  • RADP_DFE_FXTAP1_67
  • RADP_DFE_FXTAP1_68
  • RADP_DFE_FXTAP1_69
  • RADP_DFE_FXTAP1_6
  • RADP_DFE_FXTAP1_70
  • RADP_DFE_FXTAP1_71
  • RADP_DFE_FXTAP1_72
  • RADP_DFE_FXTAP1_73
  • RADP_DFE_FXTAP1_74
  • RADP_DFE_FXTAP1_75
  • RADP_DFE_FXTAP1_76
  • RADP_DFE_FXTAP1_77
  • RADP_DFE_FXTAP1_78
  • RADP_DFE_FXTAP1_79
  • RADP_DFE_FXTAP1_7
  • RADP_DFE_FXTAP1_80
  • RADP_DFE_FXTAP1_81
  • RADP_DFE_FXTAP1_82
  • RADP_DFE_FXTAP1_83
  • RADP_DFE_FXTAP1_84
  • RADP_DFE_FXTAP1_85
  • RADP_DFE_FXTAP1_86
  • RADP_DFE_FXTAP1_87
  • RADP_DFE_FXTAP1_88
  • RADP_DFE_FXTAP1_89
  • RADP_DFE_FXTAP1_8
  • RADP_DFE_FXTAP1_90
  • RADP_DFE_FXTAP1_91
  • RADP_DFE_FXTAP1_92
  • RADP_DFE_FXTAP1_93
  • RADP_DFE_FXTAP1_94
  • RADP_DFE_FXTAP1_95
  • RADP_DFE_FXTAP1_96
  • RADP_DFE_FXTAP1_97
  • RADP_DFE_FXTAP1_98
  • RADP_DFE_FXTAP1_99
  • RADP_DFE_FXTAP1_9
  • RADP_DFE_FXTAP2_0
  • RADP_DFE_FXTAP2_100
  • RADP_DFE_FXTAP2_101
  • RADP_DFE_FXTAP2_102
  • RADP_DFE_FXTAP2_103
  • RADP_DFE_FXTAP2_104
  • RADP_DFE_FXTAP2_105
  • RADP_DFE_FXTAP2_106
  • RADP_DFE_FXTAP2_107
  • RADP_DFE_FXTAP2_108
  • RADP_DFE_FXTAP2_109
  • RADP_DFE_FXTAP2_10
  • RADP_DFE_FXTAP2_110
  • RADP_DFE_FXTAP2_111
  • RADP_DFE_FXTAP2_112
  • RADP_DFE_FXTAP2_113
  • RADP_DFE_FXTAP2_114
  • RADP_DFE_FXTAP2_115
  • RADP_DFE_FXTAP2_116
  • RADP_DFE_FXTAP2_117
  • RADP_DFE_FXTAP2_118
  • RADP_DFE_FXTAP2_119
  • RADP_DFE_FXTAP2_11
  • RADP_DFE_FXTAP2_120
  • RADP_DFE_FXTAP2_121
  • RADP_DFE_FXTAP2_122
  • RADP_DFE_FXTAP2_123
  • RADP_DFE_FXTAP2_124
  • RADP_DFE_FXTAP2_125
  • RADP_DFE_FXTAP2_126
  • RADP_DFE_FXTAP2_127
  • RADP_DFE_FXTAP2_12
  • RADP_DFE_FXTAP2_13
  • RADP_DFE_FXTAP2_14
  • RADP_DFE_FXTAP2_15
  • RADP_DFE_FXTAP2_16
  • RADP_DFE_FXTAP2_17
  • RADP_DFE_FXTAP2_18
  • RADP_DFE_FXTAP2_19
  • RADP_DFE_FXTAP2_1
  • RADP_DFE_FXTAP2_20
  • RADP_DFE_FXTAP2_21
  • RADP_DFE_FXTAP2_22
  • RADP_DFE_FXTAP2_23
  • RADP_DFE_FXTAP2_24
  • RADP_DFE_FXTAP2_25
  • RADP_DFE_FXTAP2_26
  • RADP_DFE_FXTAP2_27
  • RADP_DFE_FXTAP2_28
  • RADP_DFE_FXTAP2_29
  • RADP_DFE_FXTAP2_2
  • RADP_DFE_FXTAP2_30
  • RADP_DFE_FXTAP2_31
  • RADP_DFE_FXTAP2_32
  • RADP_DFE_FXTAP2_33
  • RADP_DFE_FXTAP2_34
  • RADP_DFE_FXTAP2_35
  • RADP_DFE_FXTAP2_36
  • RADP_DFE_FXTAP2_37
  • RADP_DFE_FXTAP2_38
  • RADP_DFE_FXTAP2_39
  • RADP_DFE_FXTAP2_3
  • RADP_DFE_FXTAP2_40
  • RADP_DFE_FXTAP2_41
  • RADP_DFE_FXTAP2_42
  • RADP_DFE_FXTAP2_43
  • RADP_DFE_FXTAP2_44
  • RADP_DFE_FXTAP2_45
  • RADP_DFE_FXTAP2_46
  • RADP_DFE_FXTAP2_47
  • RADP_DFE_FXTAP2_48
  • RADP_DFE_FXTAP2_49
  • RADP_DFE_FXTAP2_4
  • RADP_DFE_FXTAP2_50
  • RADP_DFE_FXTAP2_51
  • RADP_DFE_FXTAP2_52
  • RADP_DFE_FXTAP2_53
  • RADP_DFE_FXTAP2_54
  • RADP_DFE_FXTAP2_55
  • RADP_DFE_FXTAP2_56
  • RADP_DFE_FXTAP2_57
  • RADP_DFE_FXTAP2_58
  • RADP_DFE_FXTAP2_59
  • RADP_DFE_FXTAP2_5
  • RADP_DFE_FXTAP2_60
  • RADP_DFE_FXTAP2_61
  • RADP_DFE_FXTAP2_62
  • RADP_DFE_FXTAP2_63
  • RADP_DFE_FXTAP2_64
  • RADP_DFE_FXTAP2_65
  • RADP_DFE_FXTAP2_66
  • RADP_DFE_FXTAP2_67
  • RADP_DFE_FXTAP2_68
  • RADP_DFE_FXTAP2_69
  • RADP_DFE_FXTAP2_6
  • RADP_DFE_FXTAP2_70
  • RADP_DFE_FXTAP2_71
  • RADP_DFE_FXTAP2_72
  • RADP_DFE_FXTAP2_73
  • RADP_DFE_FXTAP2_74
  • RADP_DFE_FXTAP2_75
  • RADP_DFE_FXTAP2_76
  • RADP_DFE_FXTAP2_77
  • RADP_DFE_FXTAP2_78
  • RADP_DFE_FXTAP2_79
  • RADP_DFE_FXTAP2_7
  • RADP_DFE_FXTAP2_80
  • RADP_DFE_FXTAP2_81
  • RADP_DFE_FXTAP2_82
  • RADP_DFE_FXTAP2_83
  • RADP_DFE_FXTAP2_84
  • RADP_DFE_FXTAP2_85
  • RADP_DFE_FXTAP2_86
  • RADP_DFE_FXTAP2_87
  • RADP_DFE_FXTAP2_88
  • RADP_DFE_FXTAP2_89
  • RADP_DFE_FXTAP2_8
  • RADP_DFE_FXTAP2_90
  • RADP_DFE_FXTAP2_91
  • RADP_DFE_FXTAP2_92
  • RADP_DFE_FXTAP2_93
  • RADP_DFE_FXTAP2_94
  • RADP_DFE_FXTAP2_95
  • RADP_DFE_FXTAP2_96
  • RADP_DFE_FXTAP2_97
  • RADP_DFE_FXTAP2_98
  • RADP_DFE_FXTAP2_99
  • RADP_DFE_FXTAP2_9
  • RADP_DFE_FXTAP2_SGN_0
  • RADP_DFE_FXTAP2_SGN_1
  • RADP_DFE_FXTAP3_0
  • RADP_DFE_FXTAP3_100
  • RADP_DFE_FXTAP3_101
  • RADP_DFE_FXTAP3_102
  • RADP_DFE_FXTAP3_103
  • RADP_DFE_FXTAP3_104
  • RADP_DFE_FXTAP3_105
  • RADP_DFE_FXTAP3_106
  • RADP_DFE_FXTAP3_107
  • RADP_DFE_FXTAP3_108
  • RADP_DFE_FXTAP3_109
  • RADP_DFE_FXTAP3_10
  • RADP_DFE_FXTAP3_110
  • RADP_DFE_FXTAP3_111
  • RADP_DFE_FXTAP3_112
  • RADP_DFE_FXTAP3_113
  • RADP_DFE_FXTAP3_114
  • RADP_DFE_FXTAP3_115
  • RADP_DFE_FXTAP3_116
  • RADP_DFE_FXTAP3_117
  • RADP_DFE_FXTAP3_118
  • RADP_DFE_FXTAP3_119
  • RADP_DFE_FXTAP3_11
  • RADP_DFE_FXTAP3_120
  • RADP_DFE_FXTAP3_121
  • RADP_DFE_FXTAP3_122
  • RADP_DFE_FXTAP3_123
  • RADP_DFE_FXTAP3_124
  • RADP_DFE_FXTAP3_125
  • RADP_DFE_FXTAP3_126
  • RADP_DFE_FXTAP3_127
  • RADP_DFE_FXTAP3_12
  • RADP_DFE_FXTAP3_13
  • RADP_DFE_FXTAP3_14
  • RADP_DFE_FXTAP3_15
  • RADP_DFE_FXTAP3_16
  • RADP_DFE_FXTAP3_17
  • RADP_DFE_FXTAP3_18
  • RADP_DFE_FXTAP3_19
  • RADP_DFE_FXTAP3_1
  • RADP_DFE_FXTAP3_20
  • RADP_DFE_FXTAP3_21
  • RADP_DFE_FXTAP3_22
  • RADP_DFE_FXTAP3_23
  • RADP_DFE_FXTAP3_24
  • RADP_DFE_FXTAP3_25
  • RADP_DFE_FXTAP3_26
  • RADP_DFE_FXTAP3_27
  • RADP_DFE_FXTAP3_28
  • RADP_DFE_FXTAP3_29
  • RADP_DFE_FXTAP3_2
  • RADP_DFE_FXTAP3_30
  • RADP_DFE_FXTAP3_31
  • RADP_DFE_FXTAP3_32
  • RADP_DFE_FXTAP3_33
  • RADP_DFE_FXTAP3_34
  • RADP_DFE_FXTAP3_35
  • RADP_DFE_FXTAP3_36
  • RADP_DFE_FXTAP3_37
  • RADP_DFE_FXTAP3_38
  • RADP_DFE_FXTAP3_39
  • RADP_DFE_FXTAP3_3
  • RADP_DFE_FXTAP3_40
  • RADP_DFE_FXTAP3_41
  • RADP_DFE_FXTAP3_42
  • RADP_DFE_FXTAP3_43
  • RADP_DFE_FXTAP3_44
  • RADP_DFE_FXTAP3_45
  • RADP_DFE_FXTAP3_46
  • RADP_DFE_FXTAP3_47
  • RADP_DFE_FXTAP3_48
  • RADP_DFE_FXTAP3_49
  • RADP_DFE_FXTAP3_4
  • RADP_DFE_FXTAP3_50
  • RADP_DFE_FXTAP3_51
  • RADP_DFE_FXTAP3_52
  • RADP_DFE_FXTAP3_53
  • RADP_DFE_FXTAP3_54
  • RADP_DFE_FXTAP3_55
  • RADP_DFE_FXTAP3_56
  • RADP_DFE_FXTAP3_57
  • RADP_DFE_FXTAP3_58
  • RADP_DFE_FXTAP3_59
  • RADP_DFE_FXTAP3_5
  • RADP_DFE_FXTAP3_60
  • RADP_DFE_FXTAP3_61
  • RADP_DFE_FXTAP3_62
  • RADP_DFE_FXTAP3_63
  • RADP_DFE_FXTAP3_64
  • RADP_DFE_FXTAP3_65
  • RADP_DFE_FXTAP3_66
  • RADP_DFE_FXTAP3_67
  • RADP_DFE_FXTAP3_68
  • RADP_DFE_FXTAP3_69
  • RADP_DFE_FXTAP3_6
  • RADP_DFE_FXTAP3_70
  • RADP_DFE_FXTAP3_71
  • RADP_DFE_FXTAP3_72
  • RADP_DFE_FXTAP3_73
  • RADP_DFE_FXTAP3_74
  • RADP_DFE_FXTAP3_75
  • RADP_DFE_FXTAP3_76
  • RADP_DFE_FXTAP3_77
  • RADP_DFE_FXTAP3_78
  • RADP_DFE_FXTAP3_79
  • RADP_DFE_FXTAP3_7
  • RADP_DFE_FXTAP3_80
  • RADP_DFE_FXTAP3_81
  • RADP_DFE_FXTAP3_82
  • RADP_DFE_FXTAP3_83
  • RADP_DFE_FXTAP3_84
  • RADP_DFE_FXTAP3_85
  • RADP_DFE_FXTAP3_86
  • RADP_DFE_FXTAP3_87
  • RADP_DFE_FXTAP3_88
  • RADP_DFE_FXTAP3_89
  • RADP_DFE_FXTAP3_8
  • RADP_DFE_FXTAP3_90
  • RADP_DFE_FXTAP3_91
  • RADP_DFE_FXTAP3_92
  • RADP_DFE_FXTAP3_93
  • RADP_DFE_FXTAP3_94
  • RADP_DFE_FXTAP3_95
  • RADP_DFE_FXTAP3_96
  • RADP_DFE_FXTAP3_97
  • RADP_DFE_FXTAP3_98
  • RADP_DFE_FXTAP3_99
  • RADP_DFE_FXTAP3_9
  • RADP_DFE_FXTAP3_SGN_0
  • RADP_DFE_FXTAP3_SGN_1
  • RADP_DFE_FXTAP4_0
  • RADP_DFE_FXTAP4_10
  • RADP_DFE_FXTAP4_11
  • RADP_DFE_FXTAP4_12
  • RADP_DFE_FXTAP4_13
  • RADP_DFE_FXTAP4_14
  • RADP_DFE_FXTAP4_15
  • RADP_DFE_FXTAP4_16
  • RADP_DFE_FXTAP4_17
  • RADP_DFE_FXTAP4_18
  • RADP_DFE_FXTAP4_19
  • RADP_DFE_FXTAP4_1
  • RADP_DFE_FXTAP4_20
  • RADP_DFE_FXTAP4_21
  • RADP_DFE_FXTAP4_22
  • RADP_DFE_FXTAP4_23
  • RADP_DFE_FXTAP4_24
  • RADP_DFE_FXTAP4_25
  • RADP_DFE_FXTAP4_26
  • RADP_DFE_FXTAP4_27
  • RADP_DFE_FXTAP4_28
  • RADP_DFE_FXTAP4_29
  • RADP_DFE_FXTAP4_2
  • RADP_DFE_FXTAP4_30
  • RADP_DFE_FXTAP4_31
  • RADP_DFE_FXTAP4_32
  • RADP_DFE_FXTAP4_33
  • RADP_DFE_FXTAP4_34
  • RADP_DFE_FXTAP4_35
  • RADP_DFE_FXTAP4_36
  • RADP_DFE_FXTAP4_37
  • RADP_DFE_FXTAP4_38
  • RADP_DFE_FXTAP4_39
  • RADP_DFE_FXTAP4_3
  • RADP_DFE_FXTAP4_40
  • RADP_DFE_FXTAP4_41
  • RADP_DFE_FXTAP4_42
  • RADP_DFE_FXTAP4_43
  • RADP_DFE_FXTAP4_44
  • RADP_DFE_FXTAP4_45
  • RADP_DFE_FXTAP4_46
  • RADP_DFE_FXTAP4_47
  • RADP_DFE_FXTAP4_48
  • RADP_DFE_FXTAP4_49
  • RADP_DFE_FXTAP4_4
  • RADP_DFE_FXTAP4_50
  • RADP_DFE_FXTAP4_51
  • RADP_DFE_FXTAP4_52
  • RADP_DFE_FXTAP4_53
  • RADP_DFE_FXTAP4_54
  • RADP_DFE_FXTAP4_55
  • RADP_DFE_FXTAP4_56
  • RADP_DFE_FXTAP4_57
  • RADP_DFE_FXTAP4_58
  • RADP_DFE_FXTAP4_59
  • RADP_DFE_FXTAP4_5
  • RADP_DFE_FXTAP4_60
  • RADP_DFE_FXTAP4_61
  • RADP_DFE_FXTAP4_62
  • RADP_DFE_FXTAP4_63
  • RADP_DFE_FXTAP4_6
  • RADP_DFE_FXTAP4_7
  • RADP_DFE_FXTAP4_8
  • RADP_DFE_FXTAP4_9
  • RADP_DFE_FXTAP4_SGN_0
  • RADP_DFE_FXTAP4_SGN_1
  • RADP_DFE_FXTAP5_0
  • RADP_DFE_FXTAP5_10
  • RADP_DFE_FXTAP5_11
  • RADP_DFE_FXTAP5_12
  • RADP_DFE_FXTAP5_13
  • RADP_DFE_FXTAP5_14
  • RADP_DFE_FXTAP5_15
  • RADP_DFE_FXTAP5_16
  • RADP_DFE_FXTAP5_17
  • RADP_DFE_FXTAP5_18
  • RADP_DFE_FXTAP5_19
  • RADP_DFE_FXTAP5_1
  • RADP_DFE_FXTAP5_20
  • RADP_DFE_FXTAP5_21
  • RADP_DFE_FXTAP5_22
  • RADP_DFE_FXTAP5_23
  • RADP_DFE_FXTAP5_24
  • RADP_DFE_FXTAP5_25
  • RADP_DFE_FXTAP5_26
  • RADP_DFE_FXTAP5_27
  • RADP_DFE_FXTAP5_28
  • RADP_DFE_FXTAP5_29
  • RADP_DFE_FXTAP5_2
  • RADP_DFE_FXTAP5_30
  • RADP_DFE_FXTAP5_31
  • RADP_DFE_FXTAP5_32
  • RADP_DFE_FXTAP5_33
  • RADP_DFE_FXTAP5_34
  • RADP_DFE_FXTAP5_35
  • RADP_DFE_FXTAP5_36
  • RADP_DFE_FXTAP5_37
  • RADP_DFE_FXTAP5_38
  • RADP_DFE_FXTAP5_39
  • RADP_DFE_FXTAP5_3
  • RADP_DFE_FXTAP5_40
  • RADP_DFE_FXTAP5_41
  • RADP_DFE_FXTAP5_42
  • RADP_DFE_FXTAP5_43
  • RADP_DFE_FXTAP5_44
  • RADP_DFE_FXTAP5_45
  • RADP_DFE_FXTAP5_46
  • RADP_DFE_FXTAP5_47
  • RADP_DFE_FXTAP5_48
  • RADP_DFE_FXTAP5_49
  • RADP_DFE_FXTAP5_4
  • RADP_DFE_FXTAP5_50
  • RADP_DFE_FXTAP5_51
  • RADP_DFE_FXTAP5_52
  • RADP_DFE_FXTAP5_53
  • RADP_DFE_FXTAP5_54
  • RADP_DFE_FXTAP5_55
  • RADP_DFE_FXTAP5_56
  • RADP_DFE_FXTAP5_57
  • RADP_DFE_FXTAP5_58
  • RADP_DFE_FXTAP5_59
  • RADP_DFE_FXTAP5_5
  • RADP_DFE_FXTAP5_60
  • RADP_DFE_FXTAP5_61
  • RADP_DFE_FXTAP5_62
  • RADP_DFE_FXTAP5_63
  • RADP_DFE_FXTAP5_6
  • RADP_DFE_FXTAP5_7
  • RADP_DFE_FXTAP5_8
  • RADP_DFE_FXTAP5_9
  • RADP_DFE_FXTAP5_SGN_0
  • RADP_DFE_FXTAP5_SGN_1
  • RADP_DFE_FXTAP6_0
  • RADP_DFE_FXTAP6_10
  • RADP_DFE_FXTAP6_11
  • RADP_DFE_FXTAP6_12
  • RADP_DFE_FXTAP6_13
  • RADP_DFE_FXTAP6_14
  • RADP_DFE_FXTAP6_15
  • RADP_DFE_FXTAP6_16
  • RADP_DFE_FXTAP6_17
  • RADP_DFE_FXTAP6_18
  • RADP_DFE_FXTAP6_19
  • RADP_DFE_FXTAP6_1
  • RADP_DFE_FXTAP6_20
  • RADP_DFE_FXTAP6_21
  • RADP_DFE_FXTAP6_22
  • RADP_DFE_FXTAP6_23
  • RADP_DFE_FXTAP6_24
  • RADP_DFE_FXTAP6_25
  • RADP_DFE_FXTAP6_26
  • RADP_DFE_FXTAP6_27
  • RADP_DFE_FXTAP6_28
  • RADP_DFE_FXTAP6_29
  • RADP_DFE_FXTAP6_2
  • RADP_DFE_FXTAP6_30
  • RADP_DFE_FXTAP6_31
  • RADP_DFE_FXTAP6_3
  • RADP_DFE_FXTAP6_4
  • RADP_DFE_FXTAP6_5
  • RADP_DFE_FXTAP6_6
  • RADP_DFE_FXTAP6_7
  • RADP_DFE_FXTAP6_8
  • RADP_DFE_FXTAP6_9
  • RADP_DFE_FXTAP6_SGN_0
  • RADP_DFE_FXTAP6_SGN_1
  • RADP_DFE_FXTAP7_0
  • RADP_DFE_FXTAP7_10
  • RADP_DFE_FXTAP7_11
  • RADP_DFE_FXTAP7_12
  • RADP_DFE_FXTAP7_13
  • RADP_DFE_FXTAP7_14
  • RADP_DFE_FXTAP7_15
  • RADP_DFE_FXTAP7_16
  • RADP_DFE_FXTAP7_17
  • RADP_DFE_FXTAP7_18
  • RADP_DFE_FXTAP7_19
  • RADP_DFE_FXTAP7_1
  • RADP_DFE_FXTAP7_20
  • RADP_DFE_FXTAP7_21
  • RADP_DFE_FXTAP7_22
  • RADP_DFE_FXTAP7_23
  • RADP_DFE_FXTAP7_24
  • RADP_DFE_FXTAP7_25
  • RADP_DFE_FXTAP7_26
  • RADP_DFE_FXTAP7_27
  • RADP_DFE_FXTAP7_28
  • RADP_DFE_FXTAP7_29
  • RADP_DFE_FXTAP7_2
  • RADP_DFE_FXTAP7_30
  • RADP_DFE_FXTAP7_31
  • RADP_DFE_FXTAP7_3
  • RADP_DFE_FXTAP7_4
  • RADP_DFE_FXTAP7_5
  • RADP_DFE_FXTAP7_6
  • RADP_DFE_FXTAP7_7
  • RADP_DFE_FXTAP7_8
  • RADP_DFE_FXTAP7_9
  • RADP_DFE_FXTAP7_SGN_0
  • RADP_DFE_FXTAP7_SGN_1
  • RADP_DFE_FXTAP8_0
  • RADP_DFE_FXTAP8_10
  • RADP_DFE_FXTAP8_11
  • RADP_DFE_FXTAP8_12
  • RADP_DFE_FXTAP8_13
  • RADP_DFE_FXTAP8_14
  • RADP_DFE_FXTAP8_15
  • RADP_DFE_FXTAP8_16
  • RADP_DFE_FXTAP8_17
  • RADP_DFE_FXTAP8_18
  • RADP_DFE_FXTAP8_19
  • RADP_DFE_FXTAP8_1
  • RADP_DFE_FXTAP8_20
  • RADP_DFE_FXTAP8_21
  • RADP_DFE_FXTAP8_22
  • RADP_DFE_FXTAP8_23
  • RADP_DFE_FXTAP8_24
  • RADP_DFE_FXTAP8_25
  • RADP_DFE_FXTAP8_26
  • RADP_DFE_FXTAP8_27
  • RADP_DFE_FXTAP8_28
  • RADP_DFE_FXTAP8_29
  • RADP_DFE_FXTAP8_2
  • RADP_DFE_FXTAP8_30
  • RADP_DFE_FXTAP8_31
  • RADP_DFE_FXTAP8_32
  • RADP_DFE_FXTAP8_33
  • RADP_DFE_FXTAP8_34
  • RADP_DFE_FXTAP8_35
  • RADP_DFE_FXTAP8_36
  • RADP_DFE_FXTAP8_37
  • RADP_DFE_FXTAP8_38
  • RADP_DFE_FXTAP8_39
  • RADP_DFE_FXTAP8_3
  • RADP_DFE_FXTAP8_40
  • RADP_DFE_FXTAP8_41
  • RADP_DFE_FXTAP8_42
  • RADP_DFE_FXTAP8_43
  • RADP_DFE_FXTAP8_44
  • RADP_DFE_FXTAP8_45
  • RADP_DFE_FXTAP8_46
  • RADP_DFE_FXTAP8_47
  • RADP_DFE_FXTAP8_48
  • RADP_DFE_FXTAP8_49
  • RADP_DFE_FXTAP8_4
  • RADP_DFE_FXTAP8_50
  • RADP_DFE_FXTAP8_51
  • RADP_DFE_FXTAP8_52
  • RADP_DFE_FXTAP8_53
  • RADP_DFE_FXTAP8_54
  • RADP_DFE_FXTAP8_55
  • RADP_DFE_FXTAP8_56
  • RADP_DFE_FXTAP8_57
  • RADP_DFE_FXTAP8_58
  • RADP_DFE_FXTAP8_59
  • RADP_DFE_FXTAP8_5
  • RADP_DFE_FXTAP8_60
  • RADP_DFE_FXTAP8_61
  • RADP_DFE_FXTAP8_62
  • RADP_DFE_FXTAP8_63
  • RADP_DFE_FXTAP8_6
  • RADP_DFE_FXTAP8_7
  • RADP_DFE_FXTAP8_8
  • RADP_DFE_FXTAP8_9
  • RADP_DFE_FXTAP8_SGN_0
  • RADP_DFE_FXTAP8_SGN_1
  • RADP_DFE_FXTAP9_0
  • RADP_DFE_FXTAP9_10
  • RADP_DFE_FXTAP9_11
  • RADP_DFE_FXTAP9_12
  • RADP_DFE_FXTAP9_13
  • RADP_DFE_FXTAP9_14
  • RADP_DFE_FXTAP9_15
  • RADP_DFE_FXTAP9_16
  • RADP_DFE_FXTAP9_17
  • RADP_DFE_FXTAP9_18
  • RADP_DFE_FXTAP9_19
  • RADP_DFE_FXTAP9_1
  • RADP_DFE_FXTAP9_20
  • RADP_DFE_FXTAP9_21
  • RADP_DFE_FXTAP9_22
  • RADP_DFE_FXTAP9_23
  • RADP_DFE_FXTAP9_24
  • RADP_DFE_FXTAP9_25
  • RADP_DFE_FXTAP9_26
  • RADP_DFE_FXTAP9_27
  • RADP_DFE_FXTAP9_28
  • RADP_DFE_FXTAP9_29
  • RADP_DFE_FXTAP9_2
  • RADP_DFE_FXTAP9_30
  • RADP_DFE_FXTAP9_31
  • RADP_DFE_FXTAP9_32
  • RADP_DFE_FXTAP9_33
  • RADP_DFE_FXTAP9_34
  • RADP_DFE_FXTAP9_35
  • RADP_DFE_FXTAP9_36
  • RADP_DFE_FXTAP9_37
  • RADP_DFE_FXTAP9_38
  • RADP_DFE_FXTAP9_39
  • RADP_DFE_FXTAP9_3
  • RADP_DFE_FXTAP9_40
  • RADP_DFE_FXTAP9_41
  • RADP_DFE_FXTAP9_42
  • RADP_DFE_FXTAP9_43
  • RADP_DFE_FXTAP9_44
  • RADP_DFE_FXTAP9_45
  • RADP_DFE_FXTAP9_46
  • RADP_DFE_FXTAP9_47
  • RADP_DFE_FXTAP9_48
  • RADP_DFE_FXTAP9_49
  • RADP_DFE_FXTAP9_4
  • RADP_DFE_FXTAP9_50
  • RADP_DFE_FXTAP9_51
  • RADP_DFE_FXTAP9_52
  • RADP_DFE_FXTAP9_53
  • RADP_DFE_FXTAP9_54
  • RADP_DFE_FXTAP9_55
  • RADP_DFE_FXTAP9_56
  • RADP_DFE_FXTAP9_57
  • RADP_DFE_FXTAP9_58
  • RADP_DFE_FXTAP9_59
  • RADP_DFE_FXTAP9_5
  • RADP_DFE_FXTAP9_60
  • RADP_DFE_FXTAP9_61
  • RADP_DFE_FXTAP9_62
  • RADP_DFE_FXTAP9_63
  • RADP_DFE_FXTAP9_6
  • RADP_DFE_FXTAP9_7
  • RADP_DFE_FXTAP9_8
  • RADP_DFE_FXTAP9_9
  • RADP_DFE_FXTAP9_SGN_0
  • RADP_DFE_FXTAP9_SGN_1
  • RADP_LFEQ_FB_SEL_0
  • RADP_LFEQ_FB_SEL_1
  • RADP_LFEQ_FB_SEL_2
  • RADP_LFEQ_FB_SEL_3
  • RADP_LFEQ_FB_SEL_4
  • RADP_LFEQ_FB_SEL_5
  • RADP_LFEQ_FB_SEL_6
  • RADP_LFEQ_FB_SEL_7
  • RADP_ONETIME_DFE_0
  • RADP_ONETIME_DFE_1
  • RADP_VGA_SEL_0
  • RADP_VGA_SEL_1
  • RADP_VGA_SEL_2
  • RADP_VGA_SEL_3
  • RADP_VGA_SEL_4
  • RADP_VGA_SEL_5
  • RADP_VGA_SEL_6
  • RADP_VGA_SEL_7
  • RADP_VREF_SEL_0
  • RADP_VREF_SEL_10
  • RADP_VREF_SEL_11
  • RADP_VREF_SEL_12
  • RADP_VREF_SEL_13
  • RADP_VREF_SEL_14
  • RADP_VREF_SEL_15
  • RADP_VREF_SEL_16
  • RADP_VREF_SEL_17
  • RADP_VREF_SEL_18
  • RADP_VREF_SEL_19
  • RADP_VREF_SEL_1
  • RADP_VREF_SEL_20
  • RADP_VREF_SEL_21
  • RADP_VREF_SEL_22
  • RADP_VREF_SEL_23
  • RADP_VREF_SEL_24
  • RADP_VREF_SEL_25
  • RADP_VREF_SEL_26
  • RADP_VREF_SEL_27
  • RADP_VREF_SEL_28
  • RADP_VREF_SEL_29
  • RADP_VREF_SEL_2
  • RADP_VREF_SEL_30
  • RADP_VREF_SEL_31
  • RADP_VREF_SEL_3
  • RADP_VREF_SEL_4
  • RADP_VREF_SEL_5
  • RADP_VREF_SEL_6
  • RADP_VREF_SEL_7
  • RADP_VREF_SEL_8
  • RADP_VREF_SEL_9
  • RAM_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY
  • RAM_CTL
  • RAM_REGISTER_DUPLICATION
  • RAMSTYLE_ATTRIBUTE
  • RAM_USE_DCD
  • RANDOM
  • RANDOM_PIN
  • RANDOM_PIN_SEED
  • RAPID_RECOMPILE_ASSIGNMENT_CHECKING
  • RAPID_RECOMPILE_MODE
  • RAPID_RECOMPILE_SYNTHESIS_MODE
  • RAW_BINARY_FILE
  • RBCGEN_CRITICAL_WARNING_TO_ERROR
  • RBF_FILE_GENERATION_FOR_SUPR
  • RDYNBUSY_RESERVED
  • READ
  • READ_OR_WRITE_IN_BYTE_ADDRESS
  • REALISTIC
  • RECOMMENDED
  • RECOMPILE_QUESTION
  • RECONFIGURABLE
  • RECONFIGURABLE_REVISION
  • REFCLK_COUNTER_OUT
  • REFCLK_COUPLING_OCT
  • REGENERATE_IP_IF_HDL_QSYS_MISMATCH
  • REGIONAL_CLOCK
  • REGION_NAME
  • REGISTER_LOCATION_TYPE
  • REGISTER_PACKING_ARMSTRONG
  • REGISTER_PACKING
  • REGISTER_PACKING_TSUNAMI
  • REGISTERS_ONLY
  • RELATIVE_NEUTRON_FLUX
  • RELEASE_CLEARS_BEFORE_TRI
  • RELEASE_CLEARS_BEFORE_TRI_STATES
  • REMOTE
  • REMOVE_DUPLICATE_LOGIC
  • REMOVE_DUPLICATE_REGISTERS
  • REMOVE_FANOUT_FREE_REGISTERS
  • REMOVE
  • REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS
  • REMOVE_REDUNDANT_LOGIC_CELLS
  • REMOVE_REDUNDANT_USER_CELLS
  • REPLACE_CONFLICTING
  • REPORT_AS_DQS
  • REPORT_CONNECTIVITY_CHECKS
  • REPORT_DELAY
  • REPORT_IO_PATHS_SEPARATELY
  • REPORT_PARAMETER_SETTINGS
  • REPORT_PARAMETER_SETTINGS_PRO
  • REPORT_PR_INITIAL_VALUES_AS_ERROR
  • REPORT_SOURCE_ASSIGNMENTS
  • REPORT_SOURCE_ASSIGNMENTS_PRO
  • REQUIRED_DUTY_CYCLE
  • REQUIRED_FMAX
  • RESERVE_ALL_UNUSED_PINS
  • RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND
  • RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP
  • RESERVE_ASDO_AFTER_CONFIGURATION
  • RESERVE_AVST_CLK_AFTER_CONFIGURATION
  • RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION
  • RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION
  • RESERVE_AVST_VALID_AFTER_CONFIGURATION
  • RESERVED1
  • RESERVED2
  • RESERVED3
  • RESERVED_ALL_UNUSED_PINS
  • RESERVED_ALL_UNUSED_PINS_NO_OUTPUT_GND
  • RESERVE_DATA0_AFTER_CONFIGURATION
  • RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION
  • RESERVE_DATA1_AFTER_CONFIGURATION
  • RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION
  • RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION
  • RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION
  • RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION
  • RESERVE_DCLK_AFTER_CONFIGURATION
  • RESERVED_CORE
  • RESERVED
  • RESERVED_PIN
  • RESERVE_FLASH_NCE_AFTER_CONFIGURATION
  • RESERVE_FLEXIBLE_CLOCK_NETWORK
  • RESERVE_NCEO_AFTER_CONFIGURATION
  • RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION
  • RESERVE_OTHER_APF_PINS_AFTER_CONFIGURATION
  • RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION
  • RESERVE_PIN
  • RESERVE_PLACE_REGION
  • RESERVE_PR_PINS
  • RESERVE_RDYNBUSY_AFTER_CONFIGURATION
  • RESERVE_ROUTE_REGION
  • RESERVE_ROUTING_OUTPUT_FLEXIBILITY
  • RESERVE_SDO_AFTER_CONFIGURATION
  • RESET_CAT
  • RESET_RULE_ALL
  • RESET_RULE_COMB_ASYNCH_RESET
  • RESET_RULE_IMSYNCH_ASYNCH_DOMAIN
  • RESET_RULE_IMSYNCH_EXRESET
  • RESET_RULE_INPINS_RESETNET
  • RESET_RULE_REG_ASNYCH
  • RESET_RULE_UNSYNCH_ASYNCH_DOMAIN
  • RESET_RULE_UNSYNCH_EXRESET
  • RESOLVE_FILENAME
  • RESOURCE_ALLOCATION
  • RESYNTHESIS_EXTRA_DEBUGGING_INFORMATION
  • RESYNTHESIS_OPTIMIZATION_EFFORT
  • RESYNTHESIS_PHYSICAL_SYNTHESIS
  • RESYNTHESIS_RETIMING
  • RETAIN_COMB_LOGIC_OUTSIDE_CLOUD
  • RETIMER_ASSIGNMENT
  • RETIMER_FAST_FORWARD_ASSIGNMENT
  • REVISION_BASED_FILE_NAME
  • REVISION_CONTROL_DIR
  • REVISION_CONTROL_SYSTEM
  • REVISION_CONTROL_TCL
  • REVISION_CONTROL_TCL_SCRIPT
  • REVISION_TYPE
  • R_EXT0
  • RISE
  • ROOT
  • ROUTER_CLOCKING_TOPOLOGY_ANALYSIS
  • ROUTER_EFFORT_MULTIPLIER
  • ROUTE_REGION
  • ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION
  • ROUTER_REGISTER_DUPLICATION
  • ROUTER_TIMING_OPTIMIZATION_LEVEL
  • ROUTING_BACK_ANNOTATE
  • ROUTING_BACK_ANNOTATION_FILE
  • ROUTING_BACK_ANNOTATION_MODE
  • ROW_GLOBAL
  • ROW_GLOBAL_SIGNAL
  • R_R1
  • R_R2
  • RR_HYBRID
  • RTERM_CODE0
  • RTERM_CODE10
  • RTERM_CODE11
  • RTERM_CODE12
  • RTERM_CODE13
  • RTERM_CODE14
  • RTERM_CODE15
  • RTERM_CODE1
  • RTERM_CODE2
  • RTERM_CODE3
  • RTERM_CODE4
  • RTERM_CODE5
  • RTERM_CODE6
  • RTERM_CODE7
  • RTERM_CODE8
  • RTERM_CODE9
  • RTLV_GROUP_COMB_LOGIC_IN_CLOUD
  • RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV
  • RTLV_GROUP_RELATED_NODES
  • RTLV_GROUP_RELATED_NODES_TMV
  • RTLV_PRESERVED_HANGING_NODES
  • RTLV_REMOVE_FANOUT_FREE_REGISTERS
  • RTLV_RETAIN_COMB_LOGIC_OUTSIDE_CLOUD
  • RTLV_SIMPLIFIED_LOGIC
  • RUN_ALL_TIMING_ANALYSES
  • RUN_CLOCK_TAN
  • RUN_COMPARISON_ON_EVERY_COMPILE
  • RUN_DRC_DURING_COMPILATION
  • RUN_FITTER_IN_SIGNALPROBE_MODE
  • RUN_FULL_COMPILE_ON_DEVICE_CHANGE
  • RUN_P2P_TAN
  • RUN_TAN
  • RUN_TIMING_ANALYSES
  • RUN_TIMING_ANALYSES_ONLY_FOR_TIMING_ASSIGNMENTS
  • RX_DET_OFF
  • RX_DET_ON
  • RX_DET_PCIE_OUT
  • RX_DET_QPI_OUT
  • RZQ_GROUP
  • S0H9
  • S1_MODE
  • SAFE_STATE_MACHINE
  • SAME_AS_MULTICYCLE
  • SAMPLE_AND_SUSTAIN
  • SAP_NAME
  • SATA1_I
  • SATA1_M
  • SATA1_X
  • SATA2_I
  • SATA2_M
  • SATA2_X
  • SAVE_DISK_SPACE
  • SAVE_INTERMEDIATE_FITTING_RESULTS
  • SAVE_MIGRATION_INFO_DURING_COMPILATION
  • SBI_FILE
  • SCE_PIN
  • SDC_ENTITY_FILE
  • SDC_ENTITY_HELPER_FILE
  • SDC_FILE
  • SDC_STATEMENT
  • SDC_UNIQUIFIED_STATEMENT
  • SDF_OUTPUT_FILE
  • SDI_1485_HD
  • SDI_270_SD
  • SDI_2970_3G
  • SDLV_0
  • SDLV_10
  • SDLV_11
  • SDLV_12
  • SDLV_13
  • SDLV_14
  • SDLV_15
  • SDLV_1
  • SDLV_2
  • SDLV_3
  • SDLV_4
  • SDLV_5
  • SDLV_6
  • SDLV_7
  • SDLV_8
  • SDLV_9
  • SDM_DIRECT_TO_FACTORY_IMAGE
  • SDM_PCIE_CALIB_START
  • SDM_PINS
  • SDO_PIN
  • SDO_RESERVED
  • SEARCH_PATH
  • SECTION_COLUMN
  • SECTION
  • SECURITY_BIT
  • SEED
  • SELECTED_EDGE
  • SEQUENTIAL
  • SERIAL_BITSTREAM_FILE
  • SERIAL_LITE_III_16400
  • SERIAL_LITE_III_17400
  • SERIAL_VECTOR_FILE
  • SERIES_25_OHMS
  • SERIES_25_OHMS_WITH_CALIBRATION
  • SERIES_25_OHMS_WITHOUT_CALIBRATION
  • SERIES_50_OHMS
  • SERIES_50_OHMS_WITH_CALIBRATION
  • SERIES_50_OHMS_WITHOUT_CALIBRATION
  • SERIES
  • SET_PULSE_WIDTH
  • SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED
  • SETUP_HOLD_DETECTION
  • SETUP_HOLD_TIME_VIOLATION_DETECTION
  • SETUP_RELATIONSHIP
  • SEU_FIT_REPORT
  • SFCU
  • SFI_S_6250
  • SFIS
  • SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL
  • SHOW_ALL_TAN_PANELS
  • SHOW_PARAMETER_SETTINGS_TABLES_IN_SYNTHESIS_REPORT
  • SHOW_REGISTRATION_MESSAGE
  • SHOW_TIMING_MODEL_CHANGE_MESSAGE
  • SIGNAL_INTEGRITY_ASSIGNMENT
  • SIGNAL_INTEGRITY_WILDCARDS
  • SIGNALPROBE_ALLOW_OVERUSE
  • SIGNALPROBE_ASSIGNMENT
  • SIGNALPROBE_CLOCK
  • SIGNALPROBE_DURING_NORMAL_COMPILATION
  • SIGNAL_PROBE_ENABLE
  • SIGNALPROBE_ENABLE
  • SIGNALPROBE
  • SIGNALPROBE_NUM_REGISTERS
  • SIGNAL_PROBE_SOURCE
  • SIGNALPROBE_SOURCE
  • SIGNALRACE_CAT
  • SIGNALRACE_RULE_ASYNCHPIN_SYNCH_CLKPIN
  • SIGNALRACE_RULE_CLK_PORT_RACE
  • SIGNALRACE_RULE_RESET_RACE
  • SIGNALRACE_RULE_SECOND_SIGNAL_RACE
  • SIGNALRACE_RULE_TRISTATE
  • SIGNALTAP_ASSIGNMENTS
  • SIGNALTAP_FILE
  • SIGNALTAP
  • SIGNALTAP_LOGIC_ANALYZER_PROJECT_FILES
  • SIGNALTAP_LOGIC_ANALYZER_SETTINGS
  • SIM_AUTO_USE_GLITCH_FILTERING
  • SIM_BEHAVIOR_SIMULATION
  • SIM_BUS_CHANNEL_GROUPING
  • SIM_CELL_DELAY_MODEL_TYPE
  • SIM_COMPARE_SIGNAL
  • SIM_COMPILE_HDL_FILES
  • SIM_DEFAULT_VECTOR_COMPARE_TOLERANCE
  • SIM_DELAY_MODEL_TYPE
  • SIM_ENABLE_SIMULATION_NETLIST_VIEWER
  • SIMGEN_ARBITRARY_BLACKBOX
  • SIMGEN_BLACKBOX_FILE
  • SIMGEN_PARAMETER
  • SIM_HDL_TOP_MODULE_NAME
  • SIM_INTERCONNECT_DELAY_MODEL_TYPE
  • SIM_NO_DELAYS
  • SIM_OUTPUT_POWERPLAY_VCD
  • SIM_OUTPUT_POWERPLAY_VCD_NAME
  • SIM_OUTPUT_SAF
  • SIM_OUTPUT_SAF_NAME
  • SIM_OVERWRITE_WAVEFORM_INPUTS
  • SIMPLE_18_BIT_MULTIPLIERS
  • SIMPLE_MULTIPLIERS
  • SIMPLE_MULT
  • SIMPLE_MULT_UPGRADE_WIDTH
  • SIMPLIFIED_LOGIC
  • SIM_POWERPLAY_VCD_END_TIME
  • SIM_POWERPLAY_VCD_START_TIME
  • SIM_PVT_TIMING_MODEL_TYPE
  • SIM_SET_NO_DELAYS_VIRTUAL_IO
  • SIM_SIGNAL_ACTIVITY_END_TIME
  • SIM_SIGNAL_ACTIVITY_START_TIME
  • SIM_SIGNAL_COMPARE_TOLERANCE
  • SIM_SIGNAL_TRIGGER_VECTOR_COMPARE
  • SIM_SIMULATION_DEBUGGER
  • SIM_TAP_REGISTER_D_Q_PORTS
  • SIMULATION_ASSIGNMENT
  • SIMULATION_BUS_CHANNEL_GROUPING
  • SIMULATION_CELL_DELAY_MODEL_TYPE
  • SIMULATION_COMPARE_SIGNAL
  • SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL
  • SIMULATION_COVERAGE
  • SIMULATION_DEFAULT_VECTOR_COMPARE_TOLERANCE
  • SIMULATION_DELAY_MODEL_TYPE
  • SIMULATION_INCREMENTAL_TIME_INPUT
  • SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE
  • SIMULATION
  • SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL
  • SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL
  • SIMULATION_MODE
  • SIMULATION_NETLIST_VIEWER
  • SIMULATION_SIGNAL_COMPARE_TOLERANCE
  • SIMULATION_TYPE
  • SIMULATION_VDB_RESULT_FLUSH
  • SIMULATION_VECTOR_COMPARE_BEGIN_TIME
  • SIMULATION_VECTOR_COMPARE_END_TIME
  • SIMULATION_VECTOR_COMPARE_RULE_FOR_0
  • SIMULATION_VECTOR_COMPARE_RULE_FOR_1
  • SIMULATION_VECTOR_COMPARE_RULE_FOR_DC
  • SIMULATION_VECTOR_COMPARE_RULE_FOR_H
  • SIMULATION_VECTOR_COMPARE_RULE_FOR_L
  • SIMULATION_VECTOR_COMPARE_RULE_FOR_U
  • SIMULATION_VECTOR_COMPARE_RULE_FOR_W
  • SIMULATION_VECTOR_COMPARE_RULE_FOR_X
  • SIMULATION_VECTOR_COMPARE_RULE_FOR_Z
  • SIMULATION_WITH_AUTO_GLITCH_FILTERING
  • SIMULATION_WITH_GLITCH_FILTERING_IN_NORMAL_FLOW
  • SIMULATION_WITH_GLITCH_FILTERING
  • SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF
  • SIMULATOR_ACTION_POINTS
  • SIMULATOR_GENERATE_POWERPLAY_VCD_FILE
  • SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE
  • SIMULATOR_POWERPLAY_VCD_FILE_END_TIME
  • SIMULATOR_POWERPLAY_VCD_FILE_OUTPUT_DESTINATION
  • SIMULATOR_POWERPLAY_VCD_FILE_START_TIME
  • SIMULATOR_PVT_TIMING_MODEL_TYPE
  • SIMULATOR_SETTINGS
  • SIMULATOR_SETTINGS_LIST
  • SIMULATOR_SIGNAL_ACTIVITY_FILE_END_TIME
  • SIMULATOR_SIGNAL_ACTIVITY_FILE_OUTPUT_DESTINATION
  • SIMULATOR_SIGNAL_ACTIVITY_FILE_START_TIME
  • SIMULATOR_TCL_SCRIPT_FILE
  • SIM_USE_FAST_TIMING_MODEL
  • SIM_USE_GLITCH_FILTERING
  • SIM_USE_GLITCH_FILTERING_WHEN_GENERATING_SAF
  • SIM_USE_PDB_NETLIST
  • SIM_VDB_RESULT_FLUSH
  • SIM_VECTOR_COMPARE_BEGIN_TIME
  • SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE
  • SIM_VECTOR_COMPARED_CLOCK_OFFSET
  • SIM_VECTOR_COMPARED_CLOCK_PERIOD
  • SIM_VECTOR_COMPARE_END_TIME
  • SIM_VECTOR_COMPARE_RULE_FOR_0
  • SIM_VECTOR_COMPARE_RULE_FOR_1
  • SIM_VECTOR_COMPARE_RULE_FOR_DC
  • SIM_VECTOR_COMPARE_RULE_FOR_H
  • SIM_VECTOR_COMPARE_RULE_FOR_L
  • SIM_VECTOR_COMPARE_RULE_FOR_U
  • SIM_VECTOR_COMPARE_RULE_FOR_W
  • SIM_VECTOR_COMPARE_RULE_FOR_X
  • SIM_VECTOR_COMPARE_RULE_FOR_Z
  • SIM_VECTOR_COMPARE_TRIGGER_CLOCK
  • SIM_VECTOR_COMPARE_TRIGGER_MODE
  • SIM_VECTOR_COMPARE_TRIGGER_SIGNAL
  • SIM_VECTOR_OUTPUT_FILE
  • SIM_VECTOR_OUTPUT_FORMAT
  • SINGLE_COMP_IMAGE
  • SINGLE_COMP_IMAGE_WITH_ERAM
  • SINGLE_IMAGE
  • SINGLE_IMAGE_WITH_ERAM
  • SINGLE_PIN
  • SIP_FILE
  • SIZE_OF_LATCH_REPORT
  • SIZE_OF_PR_INITIAL_CONDITIONS_REPORT
  • SKIP_ATOM_SWEEPER
  • SKIP_CONFLICTING
  • SKIP_CRC_CHECK_IN_HC
  • SKIP_REGENERATING_IP_IF_HDL_MODIFIED
  • SLD_BIDIR_PIN_CONNECT_FROM_PORT
  • SLD_FABRIC_PARTITION
  • SLD_FILE
  • SLD_INCR_NODE_CREATOR_ID
  • SLD_INCR_NODE_ENTITY_NAME
  • SLD_INCR_NODE_PARAMETER_ASSIGNMENT
  • SLD_INCR_NODE_SOURCE_FILE
  • SLD_INFO
  • SLD_NODE_CONNECT_FROM_PORT
  • SLD_NODE_CONNECT_TO_PORT
  • SLD_NODE_CREATOR_ID
  • SLD_NODE_ENTITY_NAME
  • SLD_NODE_PARAMETER_ASSIGNMENT
  • SLD_NODE_SOURCE_FILE
  • SLD_PARAMETER_ASSIGNMENT
  • SLD_PARAMETER_COMPATIBILITY_STRING
  • SLD_PIN_CONNECT_FROM_PORT
  • SLD_PIN_CONNECT_TO_PORT
  • SLD_PRE_SYN_COMPATIBILITY_STRING
  • SLEW_R0
  • SLEW_R1
  • SLEW_R2
  • SLEW_R3
  • SLEW_R4
  • SLEW_R5
  • SLEW_R6
  • SLEW_R7
  • SLEW_RATE
  • SLOW_POR_DELAY
  • SLOW_SLEW_RATE
  • SMALL
  • SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES
  • SMART_RECOMPILE
  • SMF_FILE
  • SMP_PROCESS_TYPE
  • SOFT
  • SOFTWARE_ACTION_POINTS
  • SOFTWARE_LIBRARY_FILE
  • SOFTWARE_SETTINGS
  • SOFTWARE_SETTINGS_LIST
  • SONET
  • SONET_OC12_622
  • SONET_OC192_9953
  • SONET_OC3_155
  • SONET_OC48_2488
  • SOPC_BUILDER_SIGNATURE_ID
  • SOPC_FILE
  • SOPCINFO_FILE
  • SOURCE_FILE
  • SOURCE
  • SOURCE_MULTICYCLE_HOLD
  • SOURCE_MULTICYCLE
  • SOURCES_PER_DESTINATION_INCLUDE_COUNT
  • SOURCE_SYNCHRONOUS
  • SOURCE_TCL_SCRIPT_FILE
  • SOURCE_TCL_SCRIPT
  • SPARSE_AUTO
  • SPARSE
  • SPAUI_6250
  • SPD_FILE
  • SPECTRAQ_PHYSICAL_SYNTHESIS
  • SPEED_DISK_USAGE_TRADEOFF
  • SPEED
  • SRAM_OBJECT_FILE
  • SRC_HOLD_MULTICYCLE
  • SRC_MULTICYCLE
  • SRECORDS_FILE
  • SRIO_1250_LR
  • SRIO_1250_SR
  • SRIO_2500_LR
  • SRIO_2500_SR
  • SRIO_3125_LR
  • SRIO_3125_SR
  • SRIO_5000_LR
  • SRIO_5000_MR
  • SRIO_5000_SR
  • SRIO_6250_LR
  • SRIO_6250_MR
  • SRIO_6250_SR
  • SRIO
  • STA_IGNORED_EMBEDDED_SDC_STATEMENT
  • STA_MODE
  • STANDARD_DELAY_FORMAT_OUTPUT_FILE
  • STANDARD_FIT
  • STANDARD
  • STANDARD_PARTITION
  • START_TIME
  • START_UP_CLOCK
  • STATE_MACHINE_PROCESSING
  • STD_ONLY
  • STG1_GAIN7
  • STG2_GAIN7
  • STG3_GAIN7
  • STG4_GAIN7
  • STOP
  • STP_FILE
  • STP_INCREMENTAL_SOURCE
  • STP_SIGNAL_PROBE_SOURCE
  • STP_SIGNALPROBE_SOURCE
  • STP_VIRTUAL_PIN_CLK_SOURCE
  • STP_VIRTUAL_PIN
  • STRATIX_CARRY_CHAIN_LENGTH
  • STRATIX_CONFIG_DEVICE_JTAG_USER_CODE
  • STRATIX_CONFIGURATION_DEVICE
  • STRATIX_CONFIGURATION_SCHEME
  • STRATIX_CRC_ERROR_CHECKING
  • STRATIX_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
  • STRATIX_DEVICE_IO_STANDARD
  • STRATIX_FAST_PLL_INCREASE_LOCK_WINDOW
  • STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET
  • STRATIXGX_ALLOW_DEDICATED_CLOCK_FANOUT_WITH_ANALOG_RESET
  • STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE
  • STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE
  • STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER
  • STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B
  • STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE
  • STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE
  • STRATIXGX_ALLOW_POST8B10B_LOOPBACK
  • STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK
  • STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE
  • STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS
  • STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE
  • STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER
  • STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE
  • STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT
  • STRATIXGX_OCT_VALUE
  • STRATIXGX_TERMINATION_VALUE
  • STRATIXII_ALLOW_DUAL_PORT_DUAL_CLOCK_MRAM_USAGE
  • STRATIXII_CARRY_CHAIN_LENGTH
  • STRATIX_II_CONFIGURATION_DEVICE
  • STRATIXII_CONFIGURATION_DEVICE
  • STRATIX_II_CONFIGURATION_SCHEME
  • STRATIXII_CONFIGURATION_SCHEME
  • STRATIXII_EP2S60ES_ALLOW_MRAM_USAGE
  • STRATIXIIGX_OCT_VALUE
  • STRATIXIIGX_TERMINATION_VALUE
  • STRATIXIII_CONFIGURATION_SCHEME
  • STRATIXIII_LUTAB_SLOWDOWN
  • STRATIXIII_MRAM_COMPATIBILITY
  • STRATIXIII_OUTPUT_DUTY_CYCLE_DELAY
  • STRATIXIII_UPDATE_MODE
  • STRATIXII_MRAM_COMPATIBILITY
  • STRATIXII_OPTIMIZATION_TECHNIQUE
  • STRATIXII_OUTPUT_DUTY_CYCLE_CONTROL
  • STRATIXII_SILICON_VERSION
  • STRATIXII_TERMINATION
  • STRATIXIV_CONFIGURATION_SCHEME
  • STRATIX_JTAG_USER_CODE
  • STRATIX_OPTIMIZATION_TECHNIQUE
  • STRATIX_TECHNOLOGY_MAPPER
  • STRATIX_UPDATE_MODE
  • STRATIXV_CONFIGURATION_SCHEME
  • STRICT_POST_FIT
  • STRICT_RAM_RECOGNITION
  • STRIPE_TO_PLD_BRIDGE_EPXA4_10
  • STRIPE_TO_PLD_INTERRUPTS_EPXA4_10
  • SUBCLIQUE_OF
  • SUPERIOR_PERFORMANCE
  • SUPERIOR_PERFORMANCE_WITH_MAXIMUM_PLACEMENT_EFFORT
  • SUPPRESS_DA_RULE_INTERNAL
  • SUPPRESS_REG_MINIMIZATION_MSG
  • SVF_FILE
  • SXL9
  • SYMBOL_FILE
  • SYM_FILE
  • SYNCHRONIZATION_REGISTER_CHAIN_LENGTH
  • SYNCHRONIZER_IDENTIFICATION
  • SYNCHRONIZER_TOGGLE_RATE
  • SYNTH_CHECK_PORT_CONNECTIONS
  • SYNTH_CLOCK_MUX_PROTECTION
  • SYNTH_CRITICAL_CLOCK
  • SYNTH_CRITICAL_CLOCK_TO_OUTPUT
  • SYNTH_CRITICAL_ENABLE
  • SYNTH_CRITICAL_INPUT_TO_CLOCK
  • SYNTH_CRITICAL_PIN
  • SYNTHESIS_EFFORT
  • SYNTHESIS_FITTING_SETTINGS
  • SYNTHESIS_KEEP_SYNCH_CLEAR_PRESET_BEHAVIOR_IN_UNMAPPER
  • SYNTHESIS_ON_ATOMS
  • SYNTHESIS_ONLY
  • SYNTHESIS_ONLY_QIP
  • SYNTHESIS_S10_MIGRATION_CHECKS
  • SYNTHESIS_SEED
  • SYNTHESIS_WILDCARDS
  • SYNTHESIZE_LATCHES_AS_HIPIS
  • SYNTH_GATED_CLOCK_CONVERSION
  • SYNTH_MESSAGE_LEVEL
  • SYNTH_PROTECT_SDC_CONSTRAINT
  • SYNTH_REPORT_SOURCE_ASSIGNMENTS
  • SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM
  • SYNTH_RPT_SHOW_PARAMS_PER_ENTITY_INSTANCE
  • SYNTH_TIMING_DRIVEN_BALANCED_MAPPING
  • SYNTH_TIMING_DRIVEN_REGISTER_DUPLICATION
  • SYNTH_TIMING_DRIVEN_SYNTHESIS
  • SYSTEMVERILOG_2005
  • SYSTEMVERILOG_2009
  • SYSTEMVERILOG_FILE
  • T10_DELAY
  • T10_FINE_DELAY
  • T10_OCT_DELAY
  • T10_OE_DELAY
  • T10_OE_FINE_DELAY
  • T11_0_DELAY
  • T11_1_DELAY
  • T11_DELAY
  • T11_FINE_DELAY
  • T1_DELAY
  • T1_FINE_DELAY
  • T2_DELAY
  • T3_DELAY
  • T4_DELAY
  • T7_DELAY
  • T7_FINE_DELAY
  • T8_DELAY0
  • T8_DELAY1
  • T9_DELAY
  • T9_FINE_DELAY
  • T9_OCT_DELAY
  • T9_OE_DELAY
  • TAN_SCRIPT_FILE
  • TAO_FILE
  • TAO_FILE_NAME
  • TBFF_PULSE_WIDTH
  • TCL_ENTITY_FILE
  • TCL_FILE
  • TCL_SCRIPT_FILE
  • TCO_REQUIREMENT
  • TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT
  • TDC_CCPP_TRADEOFF_TOLERANCE
  • TDO_DUMP_FILE
  • TECH_MAPPER_APEX20K
  • TECH_MAPPER_DALI
  • TECH_MAPPER_FLEX10K
  • TECH_MAPPER_FLEX6K
  • TECH_MAPPER
  • TECH_MAPPER_MAX7000
  • TECH_MAPPER_YEAGER
  • TECHNOLOGY_MAPPER_DALI
  • TECHNOLOGY_MAPPER_FLEX6K
  • TECHNOLOGY_MAPPER
  • TEMPLATE_FILE
  • TENG_1588
  • TENG_BASER
  • TENG_KR_10312
  • TENG_SDI
  • TERMINATION_CONTROL_BLOCK
  • TERMINATION
  • TEST_BENCH_MODE
  • TESTING_BOOL
  • TESTING_ENUM
  • TESTING_FILE
  • TESTING_INT_GLOBAL_DISALLOWED_IN_QIP
  • TESTING_INT
  • TESTING_SINGLE_ABSOLUTE_NODE_ENTITY_INT
  • TESTING_SINGLE_BOOL
  • TESTING_SINGLE_ENUM
  • TESTING_SINGLE_INT
  • TESTING_SINGLE_RELATIVE_BOOL
  • TESTING_SINGLE_RELATIVE_ENTITY_INT
  • TESTING_SINGLE_RELATIVE_NODE_ENTITY_BOOL
  • TESTING_SINGLE_RELATIVE_NODE_ENTITY_INT
  • TESTING_SINGLE_RELATIVE_NODE_INT
  • TESTING_SINGLE_STRING
  • TESTING_STRING
  • TEXT_FILE
  • TEXT_FORMAT_REPORT_FILE
  • THIRD_PARTY_EDA_TOOLS
  • THREE
  • TH_REQUIREMENT
  • THR_THREAD_MAIN_ID
  • TIMEGROUP_EXCEPTION
  • TIMEGROUP_MEMBER
  • TIMEQUEST2
  • TIMEQUEST_CCPP_TRADEOFF_TOLERANCE
  • TIMEQUEST_DO_CCPP_REMOVAL
  • TIMEQUEST_DO_REPORT_CDC_VIEWER
  • TIMEQUEST_DO_REPORT_TIMING
  • TIMEQUEST_MULTICORNER_ANALYSIS
  • TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS
  • TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS
  • TIMEQUEST_REPORT_SCRIPT
  • TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS
  • TIMEQUEST_SIMULTANEOUS_MULTICORNER_ANALYSIS
  • TIMEQUEST_SPECTRA_Q
  • TIMING_ANALYSIS_OUTPUT_FILE
  • TIMING_ANALYZER_CCPP_TRADEOFF_TOLERANCE
  • TIMING_ANALYZER_DO_CCPP_REMOVAL
  • TIMING_ANALYZER_DO_REPORT_CDC_VIEWER
  • TIMING_ANALYZER_DO_REPORT_TIMING
  • TIMING_ANALYZER_MULTICORNER_ANALYSIS
  • TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS
  • TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS
  • TIMING_ANALYZER_REPORT_SCRIPT
  • TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS
  • TIMING_ANALYZER_SIMULTANEOUS_MULTICORNER_ANALYSIS
  • TIMING_ASSIGNMENT
  • TIMING_CAT
  • TIMING_DERATING_FILE
  • TIMING_DRIVEN_COMPILE
  • TIMING
  • TIMING_REQUIREMENTS
  • TIMING_RULE_COIN_CLKEDGE
  • TIMING_RULE_HIGH_FANOUTS
  • TIMING_RULE_SHIFT_REG
  • TIMING_USING_FAST_TIMING_MODEL
  • TOGGLE_RATE
  • TOOLSET
  • TOP_LEVEL_ENTITY
  • TOP_PARTITION_PIN
  • TPD_REQUIREMENT
  • TRANSPORT
  • TREAT_BIDIR_AS_OUTPUT
  • TRI_CONVERTED_FROM_DIRECTIONAL_BUFFER
  • TRIGGER_EQUATION
  • TRIGGER_VECTOR_COMPARE_ON_SIGNAL
  • TRISTATE1
  • TRISTATED1
  • TRI_STATE
  • TRISTATE
  • TRISTATE_OFF
  • TRISTATE_ON
  • TRI_STATE_SPI_PINS
  • TRUE
  • TRUE_WYSIWYG_FLOW
  • TSUNAMI_OPTIMIZATION_TECHNIQUE
  • TSU_REQUIREMENT
  • TURBO_BIT
  • TXPMA_SLEW_RATE
  • TYPICAL
  • U0H9
  • UC_DCD_CAL_OFF
  • UC_DCD_CAL_ON
  • UC_RO_CAL_OFF
  • UC_RO_CAL_ON
  • UC_RX_DFE_CAL_OFF
  • UC_RX_DFE_CAL_ON
  • UC_SKEW_CAL_OFF
  • UC_SKEW_CAL_ON
  • UC_TX_VOD_CAL_CONT_OFF
  • UC_TX_VOD_CAL_CONT_ON
  • UC_TX_VOD_CAL_OFF
  • UC_TX_VOD_CAL_ON
  • UI_DEFAULT_ASSEMBLER_SETTING
  • UI_DEFAULT_COMP_PROCESS_SETTING
  • UI_DEFAULT_EDA_NATIVELINK_SETTING
  • UI_DEFAULT_EDA_SIMULATION_SETTING
  • UI_DEFAULT_FITTER_SETTING
  • UI_DEFAULT_HYPERFLEX_SETTING
  • UI_DEFAULT_OPTIMIZATION_SETTING
  • UI_DEFAULT_SIMULATOR_SETTING
  • UI_DEFAULT_SYNTHESIS_SETTING
  • UI_DEFAULT_TIMING_SETTING
  • UNFORCE_MERGE_PLL
  • UNFORCE_MERGE_PLL_OUTPUT_COUNTER
  • UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE
  • UNIPHY_TEMP_VER_CODE
  • UNNAMED_POOL
  • UNSECURED
  • UNUSED_RXCLK_BTI_MITIGATION
  • UNUSED_RXTXCLK_BTI_MITIGATION
  • UNUSED_TSD_PINS_GND
  • UPCORE_TRANSACTION_MODEL_FILE
  • UPDATE_ASE_FEATURE_TIME_WHEN_CHANGED
  • UPDATE_ASSIGNMENT_GROUP_FEATURE_TIME_WHEN_CHANGED
  • UPDATE_CHIP_EDITOR_FEATURE_TIME_WHEN_CHANGED
  • UPDATE_CONFLICTING
  • UPDATE_ECMC_FEATURE_TIME_WHEN_CHANGED
  • UPDATE_FLOORPLAN_EDITOR_FEATURE_TIME_WHEN_CHANGED
  • UPDATE_MODE_INTERNAL_FLASH
  • UPDATE_MODE_TITAN
  • UPDATE_MODE_YEAGER
  • UPDATE_PAT_FEATURE_TIME_WHEN_CHANGED
  • UPDATE_PIN_PLANNER_FEATURE_TIME_WHEN_CHANGED
  • UPDATE_SIM_FEATURE_TIME_WHEN_CHANGED
  • UPDATE_SSN_FEATURE_TIME_WHEN_CHANGED
  • UPDATE_TAN_FEATURE_TIME_WHEN_CHANGED
  • UPGRADE_WIDTH
  • USE_ADVANCED_DETAILED_LAB_LEGALITY
  • USE_AS_3V_GPIO
  • USE_AS_PROGRAMMING_PIN
  • USE_AS_REGULAR_IO
  • USE_CAP
  • USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT
  • USE_CHECKSUM_AS_USERCODE
  • USE_CHECKSUM_AS_USERCODE_MAX7000
  • USE_CLK_FOR_VIRTUAL_PIN
  • USE_CLOCK
  • USE_CLOCK_SETTINGS
  • USE_COMPILER_SETTINGS
  • USE_CONF_DONE
  • USE_CONFIGURATION_DEVICE
  • USE_CONFIGURATION_DEVICE_NAME_APEX20K
  • USE_CONFIGURATION_DEVICE_NAME_ARMSTRONG
  • USE_CONFIGURATION_DEVICE_NAME_CUDA
  • USE_CONFIGURATION_DEVICE_NAME_CYCLONE
  • USE_CONFIGURATION_DEVICE_NAME_DALI
  • USE_CONFIGURATION_DEVICE_NAME_EXCALIBUR
  • USE_CONFIGURATION_DEVICE_NAME_FLEX10K
  • USE_CONFIGURATION_DEVICE_NAME_FLEX6K
  • USE_CONFIGURATION_DEVICE_NAME
  • USE_CONFIGURATION_DEVICE_NAME_YEAGER
  • USE_CONFIGURATION_DEVICE_OPTIONS
  • USE_C_PREPROCESSOR_FOR_GNU_ASM_FILES
  • USE_CVP_CONFDONE
  • USE_DATA_UNLOCK
  • USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN
  • USE_DMF
  • USE_GENERATED_PHYSICAL_CONSTRAINTS
  • USE_GLOBAL_SETTINGS
  • USE_HIGH_SPEED_ADDER
  • USE_HPS_COLD_RESET
  • USE_HPS_WARM_RESET
  • USE_INIT_DONE
  • USE_LOCAL_APEX20K
  • USE_LOCAL_FLEX6K
  • USE_LOCAL
  • USE_LOGIC_ANALYZER_INTERFACE_FILE
  • USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING
  • USE_LPM_FOR_AHDL_OPERATORS
  • USE_MULTITAP_FILE
  • USE_NEW_TEXT_REPORT_TABLE_FORMAT
  • USE_PWRMGT_ALERT
  • USE_PWRMGT_PWM0
  • USE_PWRMGT_SCL
  • USE_PWRMGT_SDA
  • USER_CUSTOM
  • USER_ENABLED
  • USER_ENCODED
  • USER_FILES_NEW_EXTRACTOR
  • USER_JTAG_CODE_APEX20K
  • USER_JTAG_CODE_DALI
  • USER_JTAG_CODE_FLEX10K
  • USER_JTAG_CODE_FLEX6K
  • USER_JTAG_CODE
  • USER_JTAG_CODE_MAX7000
  • USER_JTAG_CODE_MAX7000S
  • USER_JTAG_CODE_YEAGER
  • USER_LIBRARIES
  • USER_MESSAGE
  • USER_START_UP_CLOCK
  • USER_VALUE
  • USE_SEU_ERROR
  • USE_SIGNALTAP_FILE
  • USE_TCL_PROC
  • USE_TIMEQUEST_TIMING_ANALYZER
  • USE_TIMING_DRIVEN_COMPILATION
  • USE_UIB_CATTRIP
  • USE_VPACK
  • USE_VPR
  • USE_VQM_INSTEAD_OF_SOURCE
  • V0P00
  • V0P58
  • V0P64
  • V0P67
  • V0P70
  • V0P75
  • V0P81
  • V0P86
  • V0P87
  • V0P93
  • V0P96
  • V1P00
  • V1P04
  • V1P13
  • V1P22
  • V1P30
  • V1P39
  • VALUE_IS_NODE
  • VARIABLE_VALUE_CANNOT_BE_CHANGED
  • VCCA_FPLL_USER_VOLTAGE
  • VCCA_GTBR_USER_VOLTAGE
  • VCCA_GTB_USER_VOLTAGE
  • VCCA_GXBL_USER_VOLTAGE
  • VCCA_GXBR_USER_VOLTAGE
  • VCCA_GXB_USER_VOLTAGE
  • VCCA_L_USER_VOLTAGE
  • VCCA_PLL_USER_VOLTAGE
  • VCCA_R_USER_VOLTAGE
  • VCCA_USER_VOLTAGE
  • VCCAUX_SHARED_USER_VOLTAGE
  • VCCAUX_USER_VOLTAGE
  • VCCBAT_USER_VOLTAGE
  • VCCCB_USER_VOLTAGE
  • VCCD_FPLL_USER_VOLTAGE
  • VCCD_PLL_USER_VOLTAGE
  • VCCD_USER_VOLTAGE
  • VCCE_GXBL_USER_VOLTAGE
  • VCCE_GXBR_USER_VOLTAGE
  • VCCE_GXB_USER_VOLTAGE
  • VCCEH_GXBL_USER_VOLTAGE
  • VCCEH_GXBR_USER_VOLTAGE
  • VCCEH_GXB_USER_VOLTAGE
  • VCCELA_0P85V
  • VCCELA_0P9V
  • VCCELA_1P0V
  • VCCELA_1P1V
  • VCCERAM_USER_VOLTAGE
  • VCCER
  • VCCE_USER_VOLTAGE
  • VCCH_GTBR_USER_VOLTAGE
  • VCCH_GTB_USER_VOLTAGE
  • VCCH_GXBL_USER_VOLTAGE
  • VCCH_GXBR_USER_VOLTAGE
  • VCCH_GXB_USER_VOLTAGE
  • VCCHIP_L_USER_VOLTAGE
  • VCCHIP_R_USER_VOLTAGE
  • VCCHIP_USER_VOLTAGE
  • VCCH_L_USER_VOLTAGE
  • VCC_HPS_USER_VOLTAGE
  • VCCH_R_USER_VOLTAGE
  • VCCHSSI_L_USER_VOLTAGE
  • VCCHSSI_R_USER_VOLTAGE
  • VCCINT_USER_VOLTAGE
  • VCCIO_45
  • VCCIO_50
  • VCCIO_55
  • VCCIO_65
  • VCCIO_70
  • VCCIO_75
  • VCCIO_CURRENT_1PT8V
  • VCCIO_CURRENT_2PT5V
  • VCCIO_CURRENT_GTL
  • VCCIO_CURRENT_GTL_PLUS
  • VCCIO_CURRENT_LVCMOS
  • VCCIO_CURRENT_LVTTL
  • VCCIO_CURRENT_PCI
  • VCCIO_CURRENT_SSTL2_CLASS1
  • VCCIO_CURRENT_SSTL2_CLASS2
  • VCCIO_CURRENT_SSTL3_CLASS1
  • VCCIO_CURRENT_SSTL3_CLASS2
  • VCCIO_HPS_USER_VOLTAGE
  • VCCIO_IOBANK1_MAX7000B
  • VCCIO_IOBANK2_MAX7000B
  • VCCIOREF_HPS_USER_VOLTAGE
  • VCCIO_USER_VOLTAGE
  • VCCL_GTBL_USER_VOLTAGE
  • VCCL_GTBR_USER_VOLTAGE
  • VCCL_GTB_USER_VOLTAGE
  • VCCL_GXBL_USER_VOLTAGE
  • VCCL_GXBR_USER_VOLTAGE
  • VCCL_GXB_USER_VOLTAGE
  • VCCL_HPS_USER_VOLTAGE
  • VCCL_USER_VOLTAGE
  • VCCPD_USER_VOLTAGE
  • VCCPD_VOLTAGE
  • VCCPGM_USER_VOLTAGE
  • VCCPLL_HPS_USER_VOLTAGE
  • VCCPT_USER_VOLTAGE
  • VCCP_USER_VOLTAGE
  • VCCR_GTBL_USER_VOLTAGE
  • VCCR_GTBR_USER_VOLTAGE
  • VCCR_GTB_USER_VOLTAGE
  • VCCR_GXBL_USER_VOLTAGE
  • VCCR_GXBR_USER_VOLTAGE
  • VCCR_GXB_USER_VOLTAGE
  • VCCR_L_USER_VOLTAGE
  • VCCR_R_USER_VOLTAGE
  • VCCRSTCLK_HPS_USER_VOLTAGE
  • VCCR_USER_VOLTAGE
  • VCC_SETTING0
  • VCC_SETTING1
  • VCC_SETTING2
  • VCC_SETTING3
  • VCCT_GTBL_USER_VOLTAGE
  • VCCT_GTBR_USER_VOLTAGE
  • VCCT_GTB_USER_VOLTAGE
  • VCCT_GXBL_USER_VOLTAGE
  • VCCT_GXBR_USER_VOLTAGE
  • VCCT_GXB_USER_VOLTAGE
  • VCCT_L_USER_VOLTAGE
  • VCCT_R_USER_VOLTAGE
  • VCCT_USER_VOLTAGE
  • VCC_USER_VOLTAGE
  • VCD_FILE
  • VCM_CURRENT_1
  • VCM_CURRENT_2
  • VCM_CURRENT_3
  • VCM_CURRENT_DEFAULT
  • VCM_SETTING_00
  • VCM_SETTING_01
  • VCM_SETTING_02
  • VCM_SETTING_03
  • VCM_SETTING_04
  • VCM_SETTING_05
  • VCM_SETTING_06
  • VCM_SETTING_07
  • VCM_SETTING_08
  • VCM_SETTING_09
  • VCM_SETTING_10
  • VCM_SETTING_11
  • VCM_SETTING_12
  • VCM_SETTING_13
  • VCM_SETTING_14
  • VCM_SETTING_15
  • VECTOR_CHANNEL_FILE
  • VECTOR_COMPARE_TRIGGER_MODE
  • VECTOR_FILE
  • VECTOR_INPUT_SOURCE
  • VECTOR_OUTPUT_DESTINATION
  • VECTOR_OUTPUT_FORMAT
  • VECTOR_SOURCE_FILE
  • VECTOR_TABLE_OUTPUT_FILE
  • VECTOR_TEXT_FILE
  • VECTOR_WAVEFORM_FILE
  • VER_COMPATIBLE_DB_DIR
  • VERILOG_1995
  • VERILOG_2001
  • VERILOG_CONSTANT_LOOP_LIMIT
  • VERILOG_CU_MODE
  • VERILOG_FILE
  • VERILOG_GLOBAL_COMPILER_MACRO_FILE
  • VERILOG_INCLUDE_FILE
  • VERILOG_INPUT_VERSION
  • VERILOG_LMF_FILE
  • VERILOG_MACRO
  • VERILOG_NON_CONSTANT_LOOP_LIMIT
  • VERILOG_OUTPUT_FILE
  • VERILOG_SHOW_LMF_MAPPING_MESSAGES
  • VERILOG_SHOW_LMF_MAPPING_MSGS
  • VERILOG_TEST_BENCH_FILE
  • VERILOG_VH_FILE
  • VHDL_1987
  • VHDL_1993
  • VHDL_2008
  • VHDL87
  • VHDL93
  • VHDL_FILE
  • VHDL_INPUT_LIBRARY
  • VHDL_INPUT_VERSION
  • VHDL_LMF_FILE
  • VHDL_OUTPUT_FILE
  • VHDL_SHOW_LMF_MAPPING_MESSAGES
  • VHDL_SHOW_LMF_MAPPING_MSGS
  • VHDL_TEST_BENCH_FILE
  • VID_OPERATION_MODE
  • VIRTUAL_CLOCK_REFERENCE
  • VIRTUAL_EFUSES
  • VIRTUAL_IO_DRIVES_CLOCK_PORT
  • VIRTUAL_PIN
  • VOLT_0MV
  • VOLT_0P35V
  • VOLT_0P50V
  • VOLT_0P55V
  • VOLT_0P60V
  • VOLT_0P65V
  • VOLT_0P70V
  • VOLT_0P75V
  • VOLT_0P80V
  • VOLTS
  • VPACK
  • VPACK_ONLY
  • VQM_FILE
  • VREF_MODE
  • VREF_VOLT_0
  • VREF_VOLT_0P5
  • VREF_VOLT_0P75
  • VREF_VOLT_1P0
  • VTT_0P35V
  • VTT_0P50V
  • VTT_0P55V
  • VTT_0P60V
  • VTT_0P65V
  • VTT_0P70V
  • VTT_0P75V
  • VTT_0P80V
  • VTT_PDN_STRONG
  • VTT_PDN_WEAK
  • VTT_PUP_STRONG
  • VTT_PUP_WEAK
  • VTT_VCMOFF0
  • VTT_VCMOFF1
  • VTT_VCMOFF2
  • VTT_VCMOFF3
  • VTT_VCMOFF4
  • VTT_VCMOFF5
  • VTT_VCMOFF6
  • VTT_VCMOFF7
  • WAIT_1_MS
  • WAIT_2_MS
  • WAIT_4_MS
  • WAIT_50_MS
  • WAIT_8_MS
  • WEAK_PULL_UP
  • WEAK_PULL_UP_RESISTOR
  • WHEN_REQUESTED_BY_FPGA
  • WHEN_TSU_AND_TPD_CONSTRAINTS_PERMIT
  • WIDTH_0
  • WIDTH_18_BIT_MULTIPLIERS
  • WIDTH_1
  • WIDTH_2
  • WIDTH_3
  • WIDTH
  • WRITE
  • X1_PLL_FREQUENCY
  • XACTO_INCREMENTAL_COMPILE_ASSIGNMENT
  • XACTO_INCREMENTAL_COMPILE_FILE
  • XACTO_REGION
  • XACTO_VQM_FILES
  • XAUI_3125
  • XAUI
  • XCVR_A10_CDR_PLL_ANALOG_MODE
  • XCVR_A10_CDR_PLL_POWER_MODE
  • XCVR_A10_CDR_PLL_REQUIRES_GT_CAPABLE_CHANNEL
  • XCVR_A10_CDR_PLL_UC_RO_CAL
  • XCVR_A10_CMU_FPLL_ANALOG_MODE
  • XCVR_A10_CMU_FPLL_PLL_DPRIO_CLK_VREG_BOOST
  • XCVR_A10_CMU_FPLL_PLL_DPRIO_FPLL_VREG1_BOOST
  • XCVR_A10_CMU_FPLL_PLL_DPRIO_FPLL_VREG_BOOST
  • XCVR_A10_CMU_FPLL_PLL_DPRIO_STATUS_SELECT
  • XCVR_A10_CMU_FPLL_POWER_MODE
  • XCVR_A10_LC_PLL_ANALOG_MODE
  • XCVR_A10_LC_PLL_POWER_MODE
  • XCVR_A10_PM_UC_CLKDIV_SEL
  • XCVR_A10_PM_UC_CLKSEL_CORE
  • XCVR_A10_PM_UC_CLKSEL_OSC
  • XCVR_A10_REFCLK_TERM_TRISTATE
  • XCVR_A10_RX_ADAPT_DFE_CONTROL_SEL
  • XCVR_A10_RX_ADAPT_DFE_SEL
  • XCVR_A10_RX_ADAPT_VGA_SEL
  • XCVR_A10_RX_ADAPT_VREF_SEL
  • XCVR_A10_RX_ADP_CTLE_ACGAIN_4S
  • XCVR_A10_RX_ADP_CTLE_EQZ_1S_SEL
  • XCVR_A10_RX_ADP_DFE_FLTAP_POSITION
  • XCVR_A10_RX_ADP_DFE_FXTAP10
  • XCVR_A10_RX_ADP_DFE_FXTAP10_SGN
  • XCVR_A10_RX_ADP_DFE_FXTAP11
  • XCVR_A10_RX_ADP_DFE_FXTAP11_SGN
  • XCVR_A10_RX_ADP_DFE_FXTAP1
  • XCVR_A10_RX_ADP_DFE_FXTAP2
  • XCVR_A10_RX_ADP_DFE_FXTAP2_SGN
  • XCVR_A10_RX_ADP_DFE_FXTAP3
  • XCVR_A10_RX_ADP_DFE_FXTAP3_SGN
  • XCVR_A10_RX_ADP_DFE_FXTAP4
  • XCVR_A10_RX_ADP_DFE_FXTAP4_SGN
  • XCVR_A10_RX_ADP_DFE_FXTAP5
  • XCVR_A10_RX_ADP_DFE_FXTAP5_SGN
  • XCVR_A10_RX_ADP_DFE_FXTAP6
  • XCVR_A10_RX_ADP_DFE_FXTAP6_SGN
  • XCVR_A10_RX_ADP_DFE_FXTAP7
  • XCVR_A10_RX_ADP_DFE_FXTAP7_SGN
  • XCVR_A10_RX_ADP_DFE_FXTAP8
  • XCVR_A10_RX_ADP_DFE_FXTAP8_SGN
  • XCVR_A10_RX_ADP_DFE_FXTAP9
  • XCVR_A10_RX_ADP_DFE_FXTAP9_SGN
  • XCVR_A10_RX_ADP_LFEQ_FB_SEL
  • XCVR_A10_RX_ADP_ONETIME_DFE
  • XCVR_A10_RX_ADP_VGA_SEL
  • XCVR_A10_RX_ADP_VREF_SEL
  • XCVR_A10_RX_BYPASS_EQZ_STAGES_234
  • XCVR_A10_RX_EQ_BW_SEL
  • XCVR_A10_RX_EQ_DC_GAIN_TRIM
  • XCVR_A10_RX_INPUT_VCM_SEL
  • XCVR_A10_RX_LINK
  • XCVR_A10_RX_OFFSET_CANCELLATION_CTRL
  • XCVR_A10_RX_ONE_STAGE_ENABLE
  • XCVR_A10_RX_POWER_MODE
  • XCVR_A10_RX_QPI_ENABLE
  • XCVR_A10_RX_RX_SEL_BIAS_SOURCE
  • XCVR_A10_RX_SD_OUTPUT_OFF
  • XCVR_A10_RX_SD_OUTPUT_ON
  • XCVR_A10_RX_SD_THRESHOLD
  • XCVR_A10_RX_TERM_SEL
  • XCVR_A10_RX_TERM_TRI_ENABLE
  • XCVR_A10_RX_UC_RX_DFE_CAL
  • XCVR_A10_RX_VCCELA_SUPPLY_VOLTAGE
  • XCVR_A10_RX_VCM_CURRENT_ADD
  • XCVR_A10_RX_VCM_SEL
  • XCVR_A10_RX_XRX_PATH_ANALOG_MODE
  • XCVR_A10_TX_COMPENSATION_EN
  • XCVR_A10_TX_DCD_DETECTION_EN
  • XCVR_A10_TX_DPRIO_CGB_VREG_BOOST
  • XCVR_A10_TX_LINK
  • XCVR_A10_TX_LOW_POWER_EN
  • XCVR_A10_TX_POWER_MODE
  • XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP
  • XCVR_A10_TX_PRE_EMP_SIGN_2ND_POST_TAP
  • XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_1T
  • XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_2T
  • XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP
  • XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP
  • XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T
  • XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T
  • XCVR_A10_TX_RES_CAL_LOCAL
  • XCVR_A10_TX_RX_DET
  • XCVR_A10_TX_RX_DET_OUTPUT_SEL
  • XCVR_A10_TX_RX_DET_PDB
  • XCVR_A10_TX_SLEW_RATE_CTRL
  • XCVR_A10_TX_TERM_CODE
  • XCVR_A10_TX_TERM_SEL
  • XCVR_A10_TX_UC_DCD_CAL
  • XCVR_A10_TX_UC_GEN3
  • XCVR_A10_TX_UC_GEN4
  • XCVR_A10_TX_UC_SKEW_CAL
  • XCVR_A10_TX_UC_TXVOD_CAL_CONT
  • XCVR_A10_TX_UC_TXVOD_CAL
  • XCVR_A10_TX_UC_VCC_SETTING
  • XCVR_A10_TX_USER_FIR_COEFF_CTRL_SEL
  • XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL
  • XCVR_A10_TX_XTX_PATH_ANALOG_MODE
  • XCVR_ANALOG_SETTINGS_PROTOCOL
  • XCVR_C10_CDR_PLL_ANALOG_MODE
  • XCVR_C10_CDR_PLL_POWER_MODE
  • XCVR_C10_CDR_PLL_REQUIRES_GT_CAPABLE_CHANNEL
  • XCVR_C10_CDR_PLL_UC_RO_CAL
  • XCVR_C10_CMU_FPLL_ANALOG_MODE
  • XCVR_C10_CMU_FPLL_PLL_DPRIO_CLK_VREG_BOOST
  • XCVR_C10_CMU_FPLL_PLL_DPRIO_FPLL_VREG1_BOOST
  • XCVR_C10_CMU_FPLL_PLL_DPRIO_FPLL_VREG_BOOST
  • XCVR_C10_CMU_FPLL_PLL_DPRIO_STATUS_SELECT
  • XCVR_C10_CMU_FPLL_POWER_MODE
  • XCVR_C10_LC_PLL_ANALOG_MODE
  • XCVR_C10_LC_PLL_POWER_MODE
  • XCVR_C10_PM_UC_CLKDIV_SEL
  • XCVR_C10_PM_UC_CLKSEL_CORE
  • XCVR_C10_PM_UC_CLKSEL_OSC
  • XCVR_C10_REFCLK_TERM_TRISTATE
  • XCVR_C10_RX_ADAPT_DFE_CONTROL_SEL
  • XCVR_C10_RX_ADAPT_DFE_SEL
  • XCVR_C10_RX_ADAPT_VGA_SEL
  • XCVR_C10_RX_ADAPT_VREF_SEL
  • XCVR_C10_RX_ADP_CTLE_ACGAIN_4S
  • XCVR_C10_RX_ADP_CTLE_EQZ_1S_SEL
  • XCVR_C10_RX_ADP_DFE_FLTAP_POSITION
  • XCVR_C10_RX_ADP_DFE_FXTAP10
  • XCVR_C10_RX_ADP_DFE_FXTAP10_SGN
  • XCVR_C10_RX_ADP_DFE_FXTAP11
  • XCVR_C10_RX_ADP_DFE_FXTAP11_SGN
  • XCVR_C10_RX_ADP_DFE_FXTAP1
  • XCVR_C10_RX_ADP_DFE_FXTAP2
  • XCVR_C10_RX_ADP_DFE_FXTAP2_SGN
  • XCVR_C10_RX_ADP_DFE_FXTAP3
  • XCVR_C10_RX_ADP_DFE_FXTAP3_SGN
  • XCVR_C10_RX_ADP_DFE_FXTAP4
  • XCVR_C10_RX_ADP_DFE_FXTAP4_SGN
  • XCVR_C10_RX_ADP_DFE_FXTAP5
  • XCVR_C10_RX_ADP_DFE_FXTAP5_SGN
  • XCVR_C10_RX_ADP_DFE_FXTAP6
  • XCVR_C10_RX_ADP_DFE_FXTAP6_SGN
  • XCVR_C10_RX_ADP_DFE_FXTAP7
  • XCVR_C10_RX_ADP_DFE_FXTAP7_SGN
  • XCVR_C10_RX_ADP_DFE_FXTAP8
  • XCVR_C10_RX_ADP_DFE_FXTAP8_SGN
  • XCVR_C10_RX_ADP_DFE_FXTAP9
  • XCVR_C10_RX_ADP_DFE_FXTAP9_SGN
  • XCVR_C10_RX_ADP_LFEQ_FB_SEL
  • XCVR_C10_RX_ADP_ONETIME_DFE
  • XCVR_C10_RX_ADP_VGA_SEL
  • XCVR_C10_RX_ADP_VREF_SEL
  • XCVR_C10_RX_BYPASS_EQZ_STAGES_234
  • XCVR_C10_RX_EQ_BW_SEL
  • XCVR_C10_RX_EQ_DC_GAIN_TRIM
  • XCVR_C10_RX_INPUT_VCM_SEL
  • XCVR_C10_RX_LINK
  • XCVR_C10_RX_OFFSET_CANCELLATION_CTRL
  • XCVR_C10_RX_ONE_STAGE_ENABLE
  • XCVR_C10_RX_POWER_MODE
  • XCVR_C10_RX_QPI_ENABLE
  • XCVR_C10_RX_RX_SEL_BIAS_SOURCE
  • XCVR_C10_RX_SD_OUTPUT_OFF
  • XCVR_C10_RX_SD_OUTPUT_ON
  • XCVR_C10_RX_SD_THRESHOLD
  • XCVR_C10_RX_TERM_SEL
  • XCVR_C10_RX_TERM_TRI_ENABLE
  • XCVR_C10_RX_UC_RX_DFE_CAL
  • XCVR_C10_RX_VCCELA_SUPPLY_VOLTAGE
  • XCVR_C10_RX_VCM_CURRENT_ADD
  • XCVR_C10_RX_VCM_SEL
  • XCVR_C10_RX_XRX_PATH_ANALOG_MODE
  • XCVR_C10_TX_COMPENSATION_EN
  • XCVR_C10_TX_DCD_DETECTION_EN
  • XCVR_C10_TX_DPRIO_CGB_VREG_BOOST
  • XCVR_C10_TX_LINK
  • XCVR_C10_TX_LOW_POWER_EN
  • XCVR_C10_TX_POWER_MODE
  • XCVR_C10_TX_PRE_EMP_SIGN_1ST_POST_TAP
  • XCVR_C10_TX_PRE_EMP_SIGN_2ND_POST_TAP
  • XCVR_C10_TX_PRE_EMP_SIGN_PRE_TAP_1T
  • XCVR_C10_TX_PRE_EMP_SIGN_PRE_TAP_2T
  • XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP
  • XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP
  • XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T
  • XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T
  • XCVR_C10_TX_RES_CAL_LOCAL
  • XCVR_C10_TX_RX_DET
  • XCVR_C10_TX_RX_DET_OUTPUT_SEL
  • XCVR_C10_TX_RX_DET_PDB
  • XCVR_C10_TX_SLEW_RATE_CTRL
  • XCVR_C10_TX_TERM_CODE
  • XCVR_C10_TX_TERM_SEL
  • XCVR_C10_TX_UC_DCD_CAL
  • XCVR_C10_TX_UC_GEN3
  • XCVR_C10_TX_UC_GEN4
  • XCVR_C10_TX_UC_SKEW_CAL
  • XCVR_C10_TX_UC_TXVOD_CAL_CONT
  • XCVR_C10_TX_UC_TXVOD_CAL
  • XCVR_C10_TX_UC_VCC_SETTING
  • XCVR_C10_TX_USER_FIR_COEFF_CTRL_SEL
  • XCVR_C10_TX_VOD_OUTPUT_SWING_CTRL
  • XCVR_C10_TX_XTX_PATH_ANALOG_MODE
  • XCVR_FAST_LOCK_MODE
  • XCVR_GT_IO_PIN_TERMINATION
  • XCVR_GT_RX_COMMON_MODE_VOLTAGE
  • XCVR_GT_RX_CTLE
  • XCVR_GT_RX_DC_GAIN
  • XCVR_GT_RX_FORCE_VCO_CONST
  • XCVR_GT_TX_COMMON_MODE_VOLTAGE
  • XCVR_GT_TX_PRE_EMP_1ST_POST_TAP
  • XCVR_GT_TX_PRE_EMP_INV_PRE_TAP
  • XCVR_GT_TX_PRE_EMP_PRE_TAP
  • XCVR_GT_TX_VOD_MAIN_TAP
  • XCVR_IO_PIN_TERMINATION
  • XCVR_RECONFIG_AVMM_GROUP
  • XCVR_RECONFIG_GROUP
  • XCVR_REFCLK_PIN_TERMINATION
  • XCVR_RX_ACGAIN_A
  • XCVR_RX_ACGAIN_V
  • XCVR_RX_ADCE_HSF_HFBW
  • XCVR_RX_ADCE_RGEN_BW
  • XCVR_RX_ADCE_RGEN_MODE
  • XCVR_RX_BYPASS_EQ_STAGES_234
  • XCVR_RX_COMMON_MODE_VOLTAGE
  • XCVR_RX_DC_GAIN
  • XCVR_RX_DFE_PI_BW
  • XCVR_RX_ENABLE_LINEAR_EQUALIZER_PCIEMODE
  • XCVR_RX_EQ_BW_SEL
  • XCVR_RX_EYEQ_BANDWIDTH
  • XCVR_RX_INPUT_VCM_SEL
  • XCVR_RX_LINEAR_EQUALIZER_CONTROL
  • XCVR_RX_PMOS_GAIN_PEAK
  • XCVR_RX_QPI_ENABLE
  • XCVR_RX_SD_ENABLE
  • XCVR_RX_SD_OFF
  • XCVR_RX_SD_ON
  • XCVR_RX_SD_THRESHOLD
  • XCVR_RX_SEL_BIAS_SOURCE
  • XCVR_RX_SEL_HALF_BW
  • XCVR_RX_VCM_DRIVE_STRENGTH
  • XCVR_S10_REFCLK_TERM_TRISTATE
  • XCVR_TX_COMMON_MODE_VOLTAGE
  • XCVR_TX_DRIVER_RESOLUTION_CTRL
  • XCVR_TX_LOCAL_IB_CTL
  • XCVR_TX_PLL_RECONFIG_GROUP
  • XCVR_TX_PRE_EMP_1ST_POST_TAP
  • XCVR_TX_PRE_EMP_2ND_POST_TAP
  • XCVR_TX_PRE_EMP_2ND_POST_TAP_USER
  • XCVR_TX_PRE_EMP_INV_2ND_TAP
  • XCVR_TX_PRE_EMP_INV_PRE_TAP
  • XCVR_TX_PRE_EMP_PRE_TAP
  • XCVR_TX_PRE_EMP_PRE_TAP_USER
  • XCVR_TX_QPI_EN
  • XCVR_TX_RX_DET_ENABLE
  • XCVR_TX_RX_DET_MODE
  • XCVR_TX_RX_DET_OUTPUT_SEL
  • XCVR_TX_SLEW_RATE_CTRL
  • XCVR_TX_SWING_BOOST
  • XCVR_TX_VCM_CTRL_SRC
  • XCVR_TX_VCM_DRIVE_STRENGTH
  • XCVR_TX_VOD_BOOST
  • XCVR_TX_VOD
  • XCVR_TX_VOD_PRE_EMP_CTRL_SRC
  • XCVR_USE_HQ_REFCLK
  • XCVR_USE_SKEW_BALANCED
  • XCVR_VCCA_VOLTAGE
  • XCVR_VCCR_VCCT_VOLTAGE
  • X_ON_VIOLATION_OPTION
  • XOR_SYNTHESIS
  • XR_AUTO_SIZE
  • XR_CORE_ONLY
  • XR_EXCLUDE
  • XR_HEIGHT
  • XR_MEMBER_OF
  • XR_MEMBER_OPTION
  • XR_MEMBER_RESOURCE_EXCLUDE
  • XR_MEMBER_STATE
  • XR_NODE_LOCATION
  • XR_ORIGIN
  • XR_PARENT
  • XR_PATH_EXCLUDE
  • XR_PATH_INCLUDE
  • XR_PRIORITY
  • XR_RESERVE
  • XR_ROOT_REGION
  • XR_ROUGH
  • XR_SOFT
  • XR_STATE
  • XR_WIDTH
  • XSTL_INPUT_ALLOW_SE_BUFFER
  • YEAGER_CONFIGURATION_DEVICE
  • YEAGER_CRC_ERROR_CHECKING
  • YEAGER_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
  • YEAGER_DEVICE_IO_STANDARD
  • YEAGER_OCT_AND_IMPEDANCE_MATCHING
  • YEAGER_OPTIMIZATION_TECHNIQUE
  • YEAGER_TECHNOLOGY_MAPPER
  • YEAGER_UPDATE_MODE
  • ZBT_OE_FALLING_EDGE_DELAY
  • ZERO_DELAY_BUFFER
  • ZERO
  • ZIP_VECTOR_CHANNEL_FILE
  • ZIP_VECTOR_WAVEFORM_FILE
]]> https://billauer.se/blog/2021/10/quartus-pro-qsf-list/feed/ 0 Quartus 17.1 (non-pro): List of QSF parameter names https://billauer.se/blog/2021/10/quartus-qsf-list/ https://billauer.se/blog/2021/10/quartus-qsf-list/#comments Thu, 14 Oct 2021 15:11:16 +0000 eli https://billauer.se/blog/?p=6417 Due to rather peculiar reasons described in this post, I found myself looking for all QSF parameter names that Quartus recognizes. I ended up searching a binary file in Quartus’ installation directory. So this is by no means an authoritative list, but since I made it, I thought I should post it. Just in case someone else is in the business of guesswork.

So this was done with non-Pro Quartus 17.1 running Linux. For Quartus Pro 19.2, refer to this post.

This is plain text search, so quite clearly not all items appearing here are legal QSF parameters, and neither is it clear if this list is complete. Or otherwise useful, for that matter.

$ strings ./quartus/linux64/libdb_acf.so | perl -ne '/^[A-Z][A-Z0-9_]+\n*$/ && print' | sort -u
  • ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS
  • ACCEPTS_NEGATIVE
  • ACCEPTS_OPEN
  • ACCEPTS_SHORT
  • ACCEPTS_TRACK_VCCIO
  • ACCEPTS_WILDCARDS
  • ACCEPTS_ZERO
  • AC_COUPLING
  • ACF_ASSIGNMENT_USE_STRING_POOL
  • ACF_NOTIFY_ACF_MANAGER_ASSIGNMENTS_CHANGED
  • ACF_STRING_POOL_MASSIVE_DUMP
  • ACF_VARIABLE_TRAIT_TYPE_MAX_TRAIT_TYPE
  • ACF_VARIABLE_TYPE_ACF_ACF_LAST_VARIABLE
  • ACLK_CAT
  • ACLK_RULE_IMSZER_ADOMAIN
  • ACLK_RULE_NO_SZER_ACLK_DOMAIN
  • ACLK_RULE_SZER_BTW_ACLK_DOMAIN
  • ACTIVE_PARALLEL
  • ACTIVE_SERIAL_CLOCK
  • ACTIVE_SERIAL
  • ACTIVE_SERIAL_X1
  • ACTIVE_SERIAL_X4
  • ADCE_ENABLED
  • ADCE_FULL_BW
  • ADCE_HALF_BW
  • ADCE_HIGH_BW
  • ADCE_HIGH_FREQ_MODE
  • ADCE_LOW_BW
  • ADCE_LOW_FREQ_MODE
  • ADCE_MED_HIGH_BW
  • ADCE_MED_HIGH_MODE
  • ADCE_MED_LOW_BW
  • ADCE_MED_LOW_MODE
  • ADD_DEFAULT_PINS_TO_OUTPUT_VECTOR_FILE
  • ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS
  • ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
  • ADD_TO_SIMULATION_OUTPUT_WAVEFORMS
  • ADVANCED_CLOCK_OPTIMIZATION
  • ADVANCED
  • ADVANCED_PHYSICAL_OPTIMIZATION
  • ADVANCED_PHYSICAL_RETIMING
  • ADVANCED_PHYSICAL_SYNTHESIS
  • ADV_NETLIST_OPT_ALLOWED
  • ADV_NETLIST_OPT_DONT_TOUCH
  • ADV_NETLIST_OPT_FIT_LE_DUPLICATION
  • ADV_NETLIST_OPT_FIT_LE_DUPLICATION_WITH_LUT_RESYNTHESIS
  • ADV_NETLIST_OPT_FIT_LE_RETIME
  • ADV_NETLIST_OPT_METASTABLE_REGS
  • ADV_NETLIST_OPT_RETIME_CORE_AND_IO
  • ADV_NETLIST_OPT_STRING
  • ADV_NETLIST_OPT_SYNTH_ALLOW_IP_WYS_UNMAPPING
  • ADV_NETLIST_OPT_SYNTH_GATE_RETIME_1
  • ADV_NETLIST_OPT_SYNTH_GATE_RETIME_2
  • ADV_NETLIST_OPT_SYNTH_GATE_RETIME
  • ADV_NETLIST_OPT_SYNTH_REMAP_1
  • ADV_NETLIST_OPT_SYNTH_REMAP_2
  • ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO
  • ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP
  • ADV_NETLIST_OPT_TEST
  • AGGREGATE
  • AGGREGATE_REVISION
  • AGGRESSIVE_AREA
  • AGGRESSIVE
  • AGGRESSIVE_PERFORMANCE
  • AGGRESSIVE_POWER
  • AHDL_FILE
  • AHDL_INCLUDE_FILE
  • AHDL_LIMIT_INT_TO_32
  • AHDL_TEXT_DESIGN_OUTPUT_FILE
  • AHDL_USE_LPM_FOR_OPERATORS
  • ALIAS
  • ALL_EDGE
  • ALL_EXCEPT_COMBINATIONAL_LOGIC_ELEMENT_OUTPUTS
  • ALL_NODES
  • ALLOW_ACLR_FOR_SHIFT_REGISTER_RECOGNITION
  • ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION
  • ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION
  • ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION
  • ALLOW_CASCADE_GPLL_TO_LVDS_TX
  • ALLOW_CHILD_PARTITIONS
  • ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER
  • ALLOW_MULTIPLE_PERSONAS
  • ALLOW_PARALLEL_TERMINATION
  • ALLOW_POWER_UP_DONT_CARE
  • ALLOW_REGISTER_DUPLICATION
  • ALLOW_REGISTER_MERGING
  • ALLOW_REGISTER_RETIMING
  • ALLOW_SERIES_TERMINATION
  • ALLOW_SERIES_WITH_CALIBRATION_TERMINATION
  • ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES
  • ALLOW_SYNCH_CTRL_USAGE
  • ALLOW_XOR_GATE_USAGE
  • ALL_PATHS
  • ALL_STAGES_ENABLED
  • ALM_REGISTER
  • ALM_REGISTER_PACKING_EFFORT
  • ALTERA_A10_IOPLL_BOOTSTRAP
  • ALTERA_INTERNAL_FIB
  • ALTERA
  • ALWAYS_ALLOW
  • ALWAYS_ENABLE_INPUT_BUFFERS
  • ALWAYS
  • ALWAYS_REGENERATE_IP
  • ALWAYS_WRITE_TO_FILE
  • ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS
  • ANALYZE_LATCHES
  • ANALYZE_METASTABILITY
  • APEX20K_CLIQUE_TYPE
  • APEX20K_CONFIG_DEVICE_JTAG_USER_CODE
  • APEX20K_CONFIGURATION_DEVICE
  • APEX20K_CONFIGURATION_SCHEME
  • APEX20K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
  • APEX20K_DEVICE_IO_STANDARD
  • APEX20KE_DEVICE_IO_STANDARD
  • APEX20KF_DEVICE_IO_STANDARD
  • APEX20K_JTAG_USER_CODE
  • APEX20K_LOCAL_ROUTING_SOURCE
  • APEX20K_OPTIMIZATION_TECHNIQUE
  • APEX20K_TECHNOLOGY_MAPPER
  • APEX_FITTER_TYPE
  • APEXII_1_8V_HSTL
  • APEX_II_CONFIGURATION_SCHEME
  • APEXII_CONFIGURATION_SCHEME
  • APEXII_DEVICE_IO_STANDARD
  • AREF_VOLT_0
  • AREF_VOLT_0P5
  • AREF_VOLT_0P75
  • AREF_VOLT_1P0
  • ARMSTRONG_CARRY_CHAIN_LENGTH
  • ARMSTRONG_OPTIMIZATION_TECHNIQUE
  • ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE
  • AS_BIDIRECTIONAL
  • ASCII_REPORT_FILE
  • AS_FREQ_100MHZ
  • AS_FREQ_25MHZ
  • AS_FREQ_50MHZ
  • AS_INPUT_TRI_STATED
  • AS_INPUT_TRI_STATED_WITH_BUS_HOLD
  • AS_INPUT_TRI_STATED_WITH_WEAK_PULL_UP
  • ASM_FILE
  • ASM_OPTIONS_FILE_KEYWORD
  • AS_OUTPUT_DRIVING_AN_UNSPECIFIED_SIGNAL
  • AS_OUTPUT_DRIVING_GROUND
  • AS_OUTPUT_DRIVING_VCC
  • ASP_ASM_COMMAND_LINE
  • ASP_CPP_COMMAND_LINE
  • ASP_LINK_COMMAND_LINE
  • ASSEMBLER_ASSIGNMENT
  • ASSG_CAT
  • ASSG_RULE_MISSING_FMAX
  • ASSG_RULE_MISSING_TIMING
  • AS_SIGNALPROBE_OUTPUT
  • ASSIGNMENT_GROUP_ASSIGNMENT
  • ASSIGNMENT_GROUP_EXCEPTION
  • ASSIGNMENT_GROUP_MEMBER
  • AS_VREFA
  • AS_VREFB
  • AS_VREF
  • ASYNC_PIPELINE_DISABLE_DESTINATION_CHECK
  • ASYNC_PIPELINE_REG_REACH
  • ATUH
  • ATUSH
  • ATUS
  • AUATA
  • AUATI
  • AUATL
  • AUATUD
  • AUATUH
  • AUATU
  • AUATUSH
  • AUATUS
  • AUTO_C3_M9K_BIT_SKIP
  • AUTO_CARRY_CHAINS
  • AUTO_CARRY
  • AUTO_CASCADE_CHAINS
  • AUTO_CASCADE
  • AUTO_CLOCK_ENABLE_RECOGNITION
  • AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS
  • AUTO_DELAY_CHAINS
  • AUTO_DISCOVER_AND_SORT
  • AUTO_DISCOVERY
  • AUTO_DSP_RECOGNITION
  • AUTO_ENABLE_SMART_COMPILE
  • AUTO_EXPORT_INCREMENTAL_COMPILATION
  • AUTO_EXPORT_VER_COMPATIBLE_DB
  • AUTO_FAST_INPUT_REGISTERS
  • AUTO_FAST_OUTPUT_ENABLE_REGISTERS
  • AUTO_FAST_OUTPUT_REGISTERS
  • AUTO_FIT
  • AUTO_GLOBAL_CLOCK
  • AUTO_GLOBAL_CLOCK_MAX
  • AUTO_GLOBAL_MEM_CTRL
  • AUTO_GLOBAL_MEMORY_CONTROLS
  • AUTO_GLOBAL_OE
  • AUTO_GLOBAL_OE_MAX
  • AUTO_GLOBAL_REG_CTRL
  • AUTO_GLOBAL_REG_CTRL_MAX
  • AUTO_GLOBAL_REGISTER_CONTROLS
  • AUTO_IMPLEMENT_IN_ROM
  • AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE
  • AUTO_INCREMENT_EPROM_JTAG_CODE
  • AUTO_INCREMENT_USER_JTAG_CODE
  • AUTO_INPUT_REGISTER
  • AUTO_INPUT_REGISTERS
  • AUTO_INSERT_SLD_HUB_ENTITY
  • AUTO_INSERT_SLD_INCR_NODE_ENTITY
  • AUTO_INSERT_SLD_NODE_ENTITY
  • AUTO_LCELL_INSERTION
  • AUTOMATIC
  • AUTO_MERGE_PLLS
  • AUTO_MODIFIED_PACKED_REGISTERS
  • AUTO_OPEN_DRAIN
  • AUTO_OPEN_DRAIN_PINS
  • AUTO_OUTPUT_ENABLE_REGISTER
  • AUTO_OUTPUT_REGISTER
  • AUTO_OUTPUT_REGISTERS
  • AUTO_PACKED_REG_CYCLONE
  • AUTO_PACKED_REGISTERS_ARMSTRONG
  • AUTO_PACKED_REGISTERS_CYCLONE
  • AUTO_PACKED_REGISTERS_MAXII
  • AUTO_PACKED_REGISTERS_MAX
  • AUTO_PACKED_REGISTERS_STRATIXII
  • AUTO_PACKED_REGISTERS_STRATIX
  • AUTO_PACKED_REGISTERS_TSUNAMI
  • AUTO_PARALLEL_EXPANDERS
  • AUTO_PARALLEL_SYNTHESIS
  • AUTO_PERIPH
  • AUTO_PEXP
  • AUTO_QIC_EXPORT
  • AUTO_QXP_PARTITION
  • AUTO_RAM_BLOCK_BALANCING
  • AUTO_RAM_RECOGNITION
  • AUTO_RAM_TO_LCELL_CONVERSION
  • AUTO_RESERVE_CLKUSR_FOR_CALIBRATION
  • AUTO_RESOURCE_SHARING
  • AUTO_RESTART_CONFIGURATION
  • AUTO_RESTART
  • AUTO_ROM
  • AUTO_ROM_RECOGNITION
  • AUTO_SHIFT_REGISTER_RECOGNITION
  • AUTO_SLD_HUB_ENTITY
  • AUTO_TURBO_BIT
  • AUTO_USE_SIMULATION_PDB_NETLIST
  • AVAUA
  • AVAUATI
  • AVAUATUH
  • AVAUATUSD
  • AVAUATUSH
  • AVAUI
  • AVST_CLK_RESERVED
  • AVST_DATA15_0_RESERVED
  • AVST_DATA31_16_RESERVED
  • AVST_VALID_RESERVED
  • AVST_X16
  • AVST_X32
  • AVST_X8
  • AWAVA
  • AWAVAUA
  • AWAVAUATA
  • AWAVAUATE
  • AWAVAUATI
  • AWAVAUATL
  • AWAVAUATUH
  • AWAVAUATUSH
  • AWAVAUI
  • AWAVE
  • AWAVI
  • AWAVL
  • AWAVM
  • BAK_AUTO_EXPORT
  • BAK_EXPORT_DIR
  • BALANCED
  • BASED_ON_CLOCK_SETTINGS
  • BASEO
  • BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE
  • BASE_REVISION
  • BASE_REVISION_PROJECT_OUTPUT_DIRECTORY
  • BASIC
  • BDF_FILE
  • BEST
  • BIAS_INT
  • BIAS_VCMDRV
  • BLOCK_DESIGN_NAMING
  • BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES
  • BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS
  • BLOCK_RAM_TO_MLAB_CELL_CONVERSION
  • BOARD
  • BOARD_MODEL_CUSTOM
  • BOARD_MODEL_EBD_FAR_END
  • BOARD_MODEL_EBD_FILE_NAME
  • BOARD_MODEL_EBD_SIGNAL_NAME
  • BOARD_MODEL_FAR_C
  • BOARD_MODEL_FAR_DIFFERENTIAL_R
  • BOARD_MODEL_FAR_PULLDOWN_R
  • BOARD_MODEL_FAR_PULLUP_R
  • BOARD_MODEL_FAR_SERIES_R
  • BOARD_MODEL_NEAR_C
  • BOARD_MODEL_NEAR_DIFFERENTIAL_R
  • BOARD_MODEL_NEAR_PULLDOWN_R
  • BOARD_MODEL_NEAR_PULLUP_R
  • BOARD_MODEL_NEAR_SERIES_C
  • BOARD_MODEL_NEAR_SERIES_R
  • BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH
  • BOARD_MODEL_NEAR_TLINE_LENGTH
  • BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH
  • BOARD_MODEL_TERMINATION_V
  • BOARD_MODEL_TLINE_C_PER_LENGTH
  • BOARD_MODEL_TLINE_LENGTH
  • BOARD_MODEL_TLINE_L_PER_LENGTH
  • BOTH_EDGES
  • BREAKPOINT_FILE
  • BREAKPOINT
  • BREAKPOINT_LINE_NUMBER
  • BREAKPOINT_STATE
  • BSF_FILE
  • BW_FULL_12P5
  • BW_HALF_6P5
  • BYPASS_ERROR_RELEASE_CLEARS_BEFORE_TRISTATES_1S25
  • BYPASS
  • BYPASS_OFF
  • BYPASS_STAGES_234
  • BYTE_ORDER
  • BYYPASS_STAGES_234
  • CALIBRATED
  • CALIBRATED_SSTL
  • CAL_SIM_ACTIVATOR
  • CAP_NAME
  • CARRY_CHAIN_LENGTH_ARMSTRONG
  • CARRY_CHAIN_LENGTH_DALI
  • CARRY_CHAIN_LENGTH_FLEX10K
  • CARRY_CHAIN_LENGTH_FLEX6K
  • CARRY_CHAIN_LENGTH_TSUNAMI
  • CARRY_CHAIN_LENGTH_YEAGER
  • CARRY_OUT_PINS_LCELL_INSERT
  • CASCADE_CHAIN_LENGTH
  • CASE_SENSITIVE
  • CAT_ASSEMBLER
  • CAT_ASSIGNMENT_GROUP
  • CAT_DESIGN_ASSISTANT
  • CAT_FITTER
  • CAT_INCREMENTAL_COMPILATION
  • CAT_LOCATION_PIN
  • CAT_LOGICLOCK
  • CAT_MAPPER_SYNTHESIS
  • CAT_NETO
  • CAT_PARAMETERS
  • CAT_POWER_ESTIMATION
  • CAT_PROGRAMMER
  • CAT_SIGNALPROBE
  • CAT_SIGNALTAP
  • CAT_SIMULATION
  • CAT_SOFTWARE_BUILDER
  • CAT_TIMEGROUP
  • CAT_TIMING_ANALYSIS
  • CAT_TIMING
  • CB_CLKUSR
  • CB_INTOSC
  • CDF_FILE
  • CDR_BANDWIDTH_PRESET
  • CEI_11100_LR
  • CEI_11100_SR
  • CEI_4976_LR
  • CEI_4976_SR
  • CEI_6375_LR
  • CEI_6375_SR
  • CEI_9950_LR
  • CEI_9950_SR
  • CE_OPTION
  • CHAIN_FILE
  • CHECK_AGAINST_TSM_DELAY
  • CHECK_OUTPUTS
  • CHIP
  • CKN_CK_PAIR
  • CLAMPING_DIODE
  • CLIQUE_TYPE_APEX20K
  • CLIQUE_TYPE_DALI
  • CLIQUE_TYPE_FLEX10K
  • CLIQUE_TYPE_FLEX6K
  • CLIQUE_TYPE_MAX7K
  • CLK_FPLL_VREG_BOOST_1_STEP
  • CLK_FPLL_VREG_BOOST_2_STEP
  • CLK_FPLL_VREG_BOOST_3_STEP
  • CLK_FPLL_VREG_BOOST_4_STEP
  • CLK_FPLL_VREG_BOOST_5_STEP
  • CLK_FPLL_VREG_BOOST_6_STEP
  • CLK_FPLL_VREG_BOOST_7_STEP
  • CLK_FPLL_VREG_NO_VOLTAGE_BOOST
  • CLKLOCKX1_INPUT_FREQ
  • CLK_RULE_ALL
  • CLK_RULE_CLKNET_CLKSPINES
  • CLK_RULE_CLKNET_CLKSPINES_THRESHOLD
  • CLK_RULE_COMB_CLOCK
  • CLK_RULE_GATED_CLK_FANOUT
  • CLK_RULE_GATING_SCHEME
  • CLK_RULE_INPINS_CLKNET
  • CLK_RULE_INV_CLOCK
  • CLK_RULE_MIX_EDGES
  • CLOCK_ANALYSIS_ONLY
  • CLOCK_ENABLE_MULTICYCLE_HOLD
  • CLOCK_ENABLE_MULTICYCLE
  • CLOCK_ENABLE_ROUTING
  • CLOCK_ENABLE_SOURCE_MULTICYCLE_HOLD
  • CLOCK_ENABLE_SOURCE_MULTICYCLE
  • CLOCK_HOLD_UNCERTAINTY
  • CLOCK_SETUP_UNCERTAINTY
  • CLOCK_SOURCE
  • CLOCK_SPINE
  • CLOCK_TO_OUTPUT_DELAY
  • CLOUD_NOTIFY_COMPILE_ID
  • CLOUD_NOTIFY_ENABLE
  • CLOUD_NOTIFY_ENABLE_LOGGING
  • CLOUD_NOTIFY_GROUP_ID
  • CLOUD_NOTIFY_LOGGING
  • CLOUD_NOTIFY_PROXY
  • CLOUD_NOTIFY_SEND_CRIT_WARNINGS
  • CLOUD_NOTIFY_SEND_ERRORS
  • CLOUD_NOTIFY_SEND_JSON_REPORTS
  • CLOUD_NOTIFY_SERVER
  • CLOUD_NOTIFY_TOKEN
  • COMMAND_MACRO_FILE
  • COMMAND_MACRO_MODE
  • COMPANION_REVISION_NAME
  • COMPARED_CLOCK
  • COMPATIBLE_PLACEMENT_AND_ROUTING
  • COMPATIBLE_PLACEMENT
  • COMPILATION_LEVEL
  • COMPILE_NEW_PROJECT
  • COMPILER_ACTION_POINTS
  • COMPILER_ASSIGNMENT
  • COMPILER_CONFIGURED
  • COMPILER_SETTINGS_LIST
  • COMPILER_SIGNATURE_ID
  • COMPRESSION_MODE
  • CONBINATION10
  • CONBINATION11
  • CONBINATION1
  • CONBINATION2
  • CONBINATION3
  • CONBINATION4
  • CONBINATION5
  • CONBINATION6
  • CONBINATION7
  • CONBINATION8
  • CONBINATION9
  • CONFIG_DEVICE_JTAG_USER_CODE_DALI
  • CONFIG_DEVICE_JTAG_USER_CODE_FLEX6K
  • CONFIG_DEVICE_JTAG_USER_CODE
  • CONFIGURATION_CLOCK_DIVISOR
  • CONFIGURATION_CLOCK_FREQUENCY
  • CONFIGURATION_DEVICE_DALI
  • CONFIGURATION_DEVICE_FLEX6K
  • CONFIGURATION_SCHEME_DALI
  • CONFIGURATION_SCHEME_FLEX6K
  • CONFIGURATION_VCCIO_LEVEL
  • CONNECT_BIDIR_PIN_FROM_SLD_INCR_NODE_ENTITY_PORT
  • CONNECT_BIDIR_PIN_FROM_SLD_NODE_ENTITY_PORT
  • CONNECT_FROM_SLD_INCR_NODE_ENTITY_PORT
  • CONNECT_FROM_SLD_NODE_ENTITY_PORT
  • CONNECT_PIN_FROM_SLD_INCR_NODE_ENTITY_PORT
  • CONNECT_PIN_FROM_SLD_NODE_ENTITY_PORT
  • CONNECT_PIN_TO_SLD_INCR_NODE_ENTITY_PORT
  • CONNECT_PIN_TO_SLD_NODE_ENTITY_PORT
  • CONNECT_TO
  • CONNECT_TO_SLD_INCR_NODE_ENTITY_PORT
  • CONNECT_TO_SLD_NODE_ENTITY_PORT
  • CONTAINS_FAMILY_SPECIFIC_DATA
  • CONVERT_ALOAD_TO_CLEAR_PRESET
  • CONVERT_PR_WARNINGS_TO_ERRORS
  • COPY_IF_NODE_IS_DUPLICATED
  • COPY_VARIABLE_TYPE_IN_PIN_PLANNER
  • CORE_INITIALIZATION_AND_UPDATE
  • CORE_INITIALIZATION
  • CORE_ONLY_PLACE_REGION
  • CORE_UPDATE
  • COVERAGE_COMPLETE_PANEL_ENABLED
  • COVERAGE_MISSING_0_VALUE_PANEL_ENABLED
  • COVERAGE_MISSING_1_VALUE_PANEL_ENABLED
  • CPP_FILE
  • CPP_INCLUDE_FILE
  • CPRI_12500
  • CPRI_E12HV
  • CPRI_E12LVIII
  • CPRI_E12LVII
  • CPRI_E12LV
  • CPRI_E24LVIII
  • CPRI_E24LVII
  • CPRI_E24LV
  • CPRI_E30LVIII
  • CPRI_E30LVII
  • CPRI_E30LV
  • CPRI_E48LVIII
  • CPRI_E48LVII
  • CPRI_E60LVIII
  • CPRI_E60LVII
  • CPRI_E6HV
  • CPRI_E6LVIII
  • CPRI_E6LVII
  • CPRI_E6LV
  • CPRI_E96LVIII
  • CPRI_E99LVIII
  • CPRI
  • CRC_ERROR_CHECKING_YEAGER
  • CRC_ERROR_OPEN_DRAIN
  • CREATED_BY
  • CREATED_FROM
  • CROSS_BOUNDARY_OPTIMIZATIONS
  • CURRENT_STRENGTH
  • CURRENT_STRENGTH_NEW
  • CUSP_FILE
  • CUSTOM_BUILD_COMMAND_LINE
  • CUSTOM_CLOCK_TREE
  • CUT_OFF_CLEAR_AND_PRESET_PATHS
  • CUT_OFF_IO_PIN_FEEDBACK
  • CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS
  • CUT_OFF_READ_DURING_WRITE_PATH
  • CUT_OFF_READ_DURING_WRITE_PATHS
  • CVPCIE_CONFDONE_OPEN_DRAIN
  • CVPCIE_MODE
  • CVP_CONFDONE_OPEN_DRAIN
  • CVP_MODE
  • CVP_REVISION
  • CVWF
  • CYCLONE_CONFIGURATION_DEVICE
  • CYCLONE_CONFIGURATION_SCHEME
  • CYCLONEII_CONFIGURATION_SCHEME
  • CYCLONEIII_CONFIGURATION_DEVICE
  • CYCLONEIII_CONFIGURATION_SCHEME
  • CYCLONEII_M4K_COMPATIBILITY
  • CYCLONEII_OPTIMIZATION_TECHNIQUE
  • CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION
  • CYCLONEII_TERMINATION
  • CYCLONE_OPTIMIZATION_TECHNIQUE
  • D1_DELAY
  • D1_FINE_DELAY
  • D2_DELAY
  • D3_DELAY
  • D4_DELAY
  • D4_FINE_DELAY
  • D5_DELAY
  • D5_FINE_DELAY
  • D5_OCT_DELAY
  • D5_OE_DELAY
  • D6_DELAY
  • D6_FINE_DELAY
  • D6_OCT_DELAY
  • D6_OE_DELAY
  • D6_OE_FINE_DELAY
  • DA_CUSTOM_RULE_FILE
  • DATA0_PIN
  • DATA0_RESERVED
  • DATA15_8_RESERVED
  • DATA1_RESERVED
  • DATA7_1_RESERVED
  • DATA7_2_RESERVED
  • DATA7_5_RESERVED
  • DC_COUPLING_EXTERNAL_RESISTOR
  • DC_COUPLING_EXTERNAL_TERMINATION
  • DC_COUPLING_INTERNAL_100_OHMS
  • DC_CURRENT_FOR_ELECTROMIGRATION_CHECK
  • DCLK_PIN
  • DCLK_RESERVED
  • DDIO_INPUT_REGISTER
  • DDIO_OUTPUT_REGISTER_DISTANCE
  • DDIO_OUTPUT_REGISTER
  • DEBUG_BOUNDARY
  • DEBUG_TRACE
  • DECREASE_INPUT_DELAY_TO_INPUT_REGISTER
  • DECREASE_INPUT_DELAY_TO_OUTPUT_REGISTER
  • DEFAULT_DESIGN_ASSISTANT_SETTINGS
  • DEFAULT_DEVICE_OPTIONS
  • DEFAULT_EQUIVALENCE_CHECKER_SETTINGS
  • DEFAULT_HARDCOPY_SETTINGS
  • DEFAULT_HOLD_MULTICYCLE
  • DEFAULT_LOGIC_OPTIONS
  • DEFAULT_NETLIST_VIEWER_SETTINGS
  • DEFAULT_PARAMETERS
  • DEFAULT_SDC_FILE
  • DEFAULT_TIMING_REQUIREMENTS
  • DEFAULT_VALUE
  • DELAY_SETTING_FROM_CORE_TO_CE_INPUT_REGISTER
  • DELAY_SETTING_FROM_CORE_TO_CE_IO_REGISTER
  • DELAY_SETTING_FROM_CORE_TO_CE_OE_REGISTER
  • DELAY_SETTING_FROM_CORE_TO_CE_OUTPUT_REGISTER
  • DELAY_SETTING_FROM_CORE_TO_OUTPUT_REGISTER
  • DELAY_SETTING_FROM_VIO_TO_CORE
  • DELAY_SETTING_TO_CORE_APEX20K
  • DELAY_SETTING_TO_CORE_DALI
  • DELAY_SETTING_TO_CORE_FLEX10K
  • DELAY_SETTING_TO_CORE_FLEX6K
  • DELAY_SETTING_TO_CORE_TO_OUTPUT_REGISTER
  • DELAY_SETTING_TO_CORE_TSUNAMI
  • DELAY_SETTING_TO_CORE_YEAGER
  • DELAY_SETTING_TO_INPUT_REGISTER
  • DELAY_SETTING_TO_OUTPUT_ENABLE
  • DELAY_SETTING_TO_OUTPUT
  • DELAY_SETTING_TO_ZBT
  • DEPENDENCY_FILE
  • DESIGN_ASSISTANT_ASSIGNMENT
  • DEV_FAMILY_ACEX1K
  • DEV_FAMILY_APEX20KC
  • DEV_FAMILY_APEX20KE
  • DEV_FAMILY_APEX20K
  • DEV_FAMILY_APEXII
  • DEV_FAMILY_ARMSTRONG
  • DEV_FAMILY_ARRIAIIGZ
  • DEV_FAMILY_ARRIAVGZ
  • DEV_FAMILY_ARRIAV
  • DEV_FAMILY_ASC
  • DEV_FAMILY_AURORA
  • DEV_FAMILY_BEDROCK
  • DEV_FAMILY_BS
  • DEV_FAMILY_CUDA
  • DEV_FAMILY_CYCLONE10LP
  • DEV_FAMILY_CYCLONEII
  • DEV_FAMILY_CYCLONEIVE
  • DEV_FAMILY_CYCLONEV
  • DEV_FAMILY_DALI
  • DEV_FAMILY_EMBEDDED_PROCESSOR
  • DEV_FAMILY_EPC1
  • DEV_FAMILY_EPC2
  • DEV_FAMILY_EXCALIBUR_ARM
  • DEV_FAMILY_FLASH_LOGIC
  • DEV_FAMILY_FLEX10KA
  • DEV_FAMILY_FLEX10KB
  • DEV_FAMILY_FLEX10KE
  • DEV_FAMILY_FLEX10K
  • DEV_FAMILY_FLEX6K
  • DEV_FAMILY_FLEX8000
  • DEV_FAMILY_FUSION
  • DEV_FAMILY_HCXIV
  • DEV_FAMILY_HCX
  • DEV_FAMILY_INTEL_CFI
  • DEV_FAMILY_MAX3000A
  • DEV_FAMILY_MAX7000AE
  • DEV_FAMILY_MAX7000A
  • DEV_FAMILY_MAX7000B
  • DEV_FAMILY_MAX7000S
  • DEV_FAMILY_MAX9000
  • DEV_FAMILY_MAXV
  • DEV_FAMILY_NADDER_EMULATOR
  • DEV_FAMILY_NADDER
  • DEV_FAMILY_NIGHTFURY
  • DEV_FAMILY_PIRANHA
  • DEV_FAMILY_SOC_SERIES_V
  • DEV_FAMILY_STINGRAY
  • DEV_FAMILY_STRATIXHC
  • DEV_FAMILY_STRATIXIIGX
  • DEV_FAMILY_STRATIXIIGXLITE
  • DEV_FAMILY_STRATIXV
  • DEV_FAMILY_SYN
  • DEV_FAMILY_TARPON
  • DEV_FAMILY_TGX
  • DEV_FAMILY_TITAN
  • DEV_FAMILY_TORNADO
  • DEV_FAMILY_TSUNAMI
  • DEV_FAMILY_VERMEER
  • DEV_FAMILY_VIRTUAL_JTAG_TAP
  • DEV_FAMILY_YEAGER
  • DEV_FAMILY_ZIPPLEBACK
  • DEVICE_FILTER_PACKAGE
  • DEVICE_FILTER_PIN_COUNT
  • DEVICE_FILTER_SPEED_GRADE
  • DEVICE_FILTER_VOLTAGE
  • DEVICE_INITIALIZATION_CLOCK
  • DEVICE_IO_STANDARD_APEX20KE
  • DEVICE_IO_STANDARD_APEX20KF
  • DEVICE_IO_STANDARD_APEX20K
  • DEVICE_IO_STANDARD_DALI
  • DEVICE_IO_STANDARD_FLEX10K
  • DEVICE_IO_STANDARD_FLEX6K
  • DEVICE_IO_STANDARD_MAX7000
  • DEVICE_IO_STANDARD_YEAGER
  • DEVICE_MIGRATION_LIST
  • DEVICE_TECHNOLOGY_MIGRATION_LIST
  • DEV_PART_GENERIC
  • DEV_PART_INVALID
  • DEV_PART_MAX
  • DFE_PI_BW_0P5GHZ
  • DFE_PI_BW_10GHZ
  • DFE_PI_BW_2P5GHZ
  • DFE_PI_BW_5GHZ
  • DIFFERENTIAL
  • DIRECT_FORMAT
  • DIRECT
  • DISABLE_CONF_DONE_AND_NSTATUS_ON_EPROM
  • DISABLE_CONF_DONE_AND_NSTATUS_PULLUPS_ON_CONFIG_DEVICE
  • DISABLE_CORE_CLK
  • DISABLE_DA_GX_RULE
  • DISABLE_DA_RULE
  • DISABLED
  • DISABLE_DSP_NEGATE_INFERENCING
  • DISABLE_EMBEDDED_TIMING_CONSTRAINT
  • DISABLE_MLAB_RAM_USE
  • DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE
  • DISABLE_OCP_HW_EVAL
  • DISABLE_PLL_COMPENSATION_DELAY_CHANGE_WARNING
  • DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES
  • DISABLE_TRI
  • DISALLOW_GLOBAL_ASSIGNMENT_IN_QIP
  • DIV2
  • DIV4
  • DIVIDE_BASE_CLOCK_BY
  • DIVIDE_BASE_CLOCK_PERIOD_BY
  • DM_PIN
  • DO_COMBINED_ANALYSIS
  • DO_MIN_ANALYSIS
  • DO_MINMAX_ANALYSIS_USING_RISEFALL_DELAYS
  • DO_MIN_TIMING
  • DONT_AUTODISCOVER_CPP_FILES
  • DONT_CONVERT_TO_USER_FRIENDLY_STRING
  • DONT_COPY_TO_CREATED_COMPANION_REVISION
  • DONT_COPY_TO_NEW_FILE_FORMAT
  • DONT_COPY_TO_NEW_REVISION
  • DONT_MERGE_REGISTER
  • DONT_REUSE_REMOVED_ASSIGNMENT
  • DONT_TOUCH_USER_CELL
  • DO_POST_BUILD_COMMAND_LINE
  • DO_SYSTEM_FMAX
  • DP_1620
  • DP_2700
  • DP_5400
  • DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1
  • DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1
  • DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1
  • DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1
  • DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1
  • DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1
  • DPRAM_DEEP_MODE_INPUT_EPXA4_10
  • DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10
  • DPRAM_DEEP_MODE_OUTPUT_EPXA4_10
  • DPRAM_DUAL_PORT_MODE_INPUT_EPXA1
  • DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10
  • DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1
  • DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10
  • DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1
  • DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10
  • DPRAM_INPUT_EPXA4_10
  • DPRAM_OTHER_SIGNALS_EPXA4_10
  • DPRAM_OUTPUT_EPXA4_10
  • DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10
  • DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10
  • DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10
  • DPRAM_WIDE_MODE_INPUT_EPXA4_10
  • DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10
  • DPRAM_WIDE_MODE_OUTPUT_EPXA4_10
  • DPRIO_CHANNEL_NUM
  • DPRIO_CRUCLK_NUM
  • DPRIO_INTERFACE_REG
  • DPRIO_NORMAL_STATUS
  • DPRIO_QUAD_NUM
  • DPRIO_QUAD_PLL_NUM
  • DPRIO_TX_PLL0_REFCLK_NUM
  • DPRIO_TX_PLL1_REFCLK_NUM
  • DPRIO_TX_PLL_NUM
  • DQ_GROUP
  • DQ_PIN
  • DQSB_DQS_PAIR
  • DQS_DELAY
  • DQS_ENABLE_DELAY_CHAIN
  • DQS_FREQUENCY
  • DQSOUT_DELAY_CHAIN
  • DQS_SHIFT
  • DQS_SYSTEM_CLOCK
  • DRC_DEADLOCK_STATE_LIMIT
  • DRC_DETAIL_MESSAGE_LIMIT
  • DRC_FANOUT_EXCEEDING
  • DRC_GATED_CLOCK_FEED
  • DRC_MAX_TOP_FANOUT
  • DRC_REPORT_FANOUT_EXCEEDING
  • DRC_REPORT_MAX_TOP_FANOUT
  • DRC_REPORT_TOP_FANOUT
  • DRC_TOP_FANOUT
  • DRC_VIOLATION_MESSAGE_LIMIT
  • DSE_SEND_REPORT_PANEL
  • DSE_SERVER_SEND_REPORTS
  • DSE_SERVER_URL
  • DSE_SYNTH_EXTRA_EFFORT_MODE
  • DSE_WORKER_ID
  • DSM_DFT_OUT
  • DSM_LSB_OUT
  • DSM_MSB_OUT
  • DSP_BLOCK_BALANCING_IMPLEMENTATION
  • DSP_BLOCK_BALANCING
  • DSPBUILDER_FILE
  • DUAL_FAST_REGIONAL_CLOCK
  • DUAL_IMAGES
  • DUAL_PURPOSE_CLOCK_PIN_DELAY
  • DUAL_REGIONAL_CLOCK
  • DUPLICATE_ATOM
  • DUPLICATE_LOGIC_EXTRACTION
  • DUPLICATE_REGISTER_EXTRACTION
  • DUP_LOGIC_EXTRACTION
  • DUP_REG_EXTRACTION
  • DYNAMIC_ATOM_CONNECTION
  • DYNAMIC_CTL
  • DYNAMIC_OCT_CONTROL_GROUP
  • E8H9
  • EARLY_CLOCK_LATENCY
  • ECO_ALLOW_ROUTING_CHANGES
  • ECO_OPTIMIZE_TIMING
  • ECO_REGENERATE_REPORT
  • ECO_TIMING_DRIVEN_COMPILE
  • EDA_BOARD_BOUNDARY_SCAN_OPERATION
  • EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL
  • EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL
  • EDA_BOARD_DESIGN_SYMBOL_TOOL
  • EDA_BOARD_DESIGN_TIMING_TOOL
  • EDA_BOARD_DESIGN_TOOL
  • EDA_DATA_FORMAT
  • EDA_DESIGN_ENTRY_SYNTHESIS_TOOL
  • EDA_DESIGN_EXTRA_ALTERA_SIM_LIB
  • EDA_DESIGN_INSTANCE_NAME
  • EDA_ENABLE_GLITCH_FILTERING
  • EDA_ENABLE_IPUTF_MODE
  • EDA_ENABLE_OCV_TIMING_ANALYSIS
  • EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE
  • EDA_EXCALIBUR_SINGLE_SLICE
  • EDA_EXTRA_ELAB_OPTION
  • EDA_FLATTEN_BUSES
  • EDA_FORMAL_VERIFICATION_ALLOW_RETIMING
  • EDA_FORMAL_VERIFICATION_TOOL
  • EDA_FV_HIERARCHY
  • EDA_GENERATE_FUNCTIONAL_NETLIST
  • EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT
  • EDA_GENERATE_POWER_INPUT_FILE
  • EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT
  • EDA_GENERATE_SDF_OUTPUT_FILE
  • EDA_GENERATE_TIMING_CLOSURE_DATA
  • EDA_IBIS_EXTENDED_MODEL_SELECTOR
  • EDA_IBIS_MODEL_SELECTOR
  • EDA_IBIS_MUTUAL_COUPLING
  • EDA_IBIS_SPECIFICATION_VERSION
  • EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION
  • EDA_INPUT_DATA_FORMAT
  • EDA_INPUT_GND
  • EDA_INPUT_GND_NAME
  • EDA_INPUT_VCC
  • EDA_INPUT_VCC_NAME
  • EDA_IPFS_FILE
  • EDA_LAUNCH_CMD_LINE_TOOL
  • EDA_LAUNCH_TOOL
  • EDA_LMF_FILE
  • EDA_MAINTAIN_DESIGN_HIERARCHY
  • EDA_MAP_ILLEGAL_CHARACTERS
  • EDA_MAP_ILLEGAL
  • EDA_NATIVELINK_GENERATE_SCRIPT_ONLY
  • EDA_NATIVELINK_PORTABLE_FILE_PATHS
  • EDA_NATIVELINK_SIMULATION_SETUP_SCRIPT
  • EDA_NATIVELINK_SIMULATION_TEST_BENCH
  • EDA_NETLIST_TYPE
  • EDA_NETLIST_WRITER_OUTPUT_DIR
  • EDA_OCV_CORE_DERATING_FACTOR
  • EDA_OCV_IO_DERATING_FACTOR
  • EDA_OUTPUT_DATA_FORMAT
  • EDA_RESYNTHESIS_TOOL
  • EDA_RTL_SIM_MODE
  • EDA_RTL_SIMULATION_RUN_SCRIPT
  • EDA_RTL_TEST_BENCH_FILE_NAME
  • EDA_RTL_TEST_BENCH_NAME
  • EDA_RTL_TEST_BENCH_RUN_FOR
  • EDA_RUN_TOOL_AUTOMATICALLY
  • EDA_SDC_FILE_NAME
  • EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED
  • EDA_SHOW_LMF_MAPPING_MESSAGES
  • EDA_SHOW_LMF_MAPPING_MSGS
  • EDA_SIMULATION_RUN_SCRIPT
  • EDA_SIMULATION_TOOL
  • EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE
  • EDA_SIMULATION_VCD_OUTPUT_TCL_FILE
  • EDA_SIMULATION_VCD_OUTPUT_TCL_FILE_NAME
  • EDA_TEST_BENCH_DESIGN_INSTANCE_NAME
  • EDA_TEST_BENCH_ENABLE_STATUS
  • EDA_TEST_BENCH_ENTITY_MODULE_NAME
  • EDA_TEST_BENCH_EXTRA_ALTERA_SIM_LIB
  • EDA_TEST_BENCH_FILE
  • EDA_TEST_BENCH_FILE_NAME
  • EDA_TEST_BENCH_GATE_LEVEL_NETLIST_LIBRARY
  • EDA_TEST_BENCH_MODULE_NAME
  • EDA_TEST_BENCH_NAME
  • EDA_TEST_BENCH_RUN_FOR
  • EDA_TEST_BENCH_RUN_SIM_FOR
  • EDA_TEST_BENCH_SETTINGS
  • EDA_TIME_SCALE
  • EDA_TIMESCALE
  • EDA_TIMING_ANALYSIS_TOOL
  • EDA_TOOL_SETTINGS
  • EDA_TRUNCATE_HPATH
  • EDA_TRUNCATE_LONG_HIERARCHY_PATHS
  • EDA_USE_IBIS_RLC_TYPE
  • EDA_USE_LMF
  • EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY
  • EDA_USE_RISE_FALL_DELAYS
  • EDA_VHDL_ARCH_NAME
  • EDA_VHDL_LIBRARY
  • EDA_WAIT_FOR_GUI_TOOL_COMPLETION
  • EDA_WRITE_CONFIG
  • EDA_WRITE_DEVICE_CONTROL_PORTS
  • EDA_WRITE_NODES_FOR_POWER_ESTIMATION
  • EDA_WRITER_DONT_WRITE_TOP_ENTITY
  • EDIF_FILE
  • ELA_FILE
  • ELEMENT_INDEX
  • ELF_FILE
  • EMIF
  • EMIF_SOC_PHYCLK_ADVANCE_MODELING
  • EMPTY
  • ENABLE_ACCELERATED_INCREMENTAL_COMPILE
  • ENABLE_ADVANCED_IO_ANALYSIS
  • ENABLE_ADVANCED_IO_DELAY_CHAIN_OPTIMIZATION
  • ENABLE_ADVANCED_IO_TIMING
  • ENABLE_ADV_SEU_DETECTION
  • ENABLE_ALT2GXB_CONFIGURATION
  • ENABLE_APEX_FITTER_CHOICE
  • ENABLE_ASMI_FOR_FLASH_LOADER
  • ENABLE_ASM_OPTIONS_FILE
  • ENABLE_ATTEMPT_SIMILAR_PLACEMENT
  • ENABLE_AUTONOMOUS_PCIE_HIP
  • ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS
  • ENABLE_BENEFICIAL_SKEW_OPTIMIZATION
  • ENABLE_BOOT_SEL_PIN
  • ENABLE_BUS_HOLD_CIRCUITRY
  • ENABLE_BUS_HOLD
  • ENABLE_CHIP_WIDE_OE
  • ENABLE_CHIP_WIDE_RESET
  • ENABLE_CLOCK_LATENCY
  • ENABLE_COMPACT_REPORT_TABLE
  • ENABLE_CONFIGURATION_PINS
  • ENABLE_CORE_CLK
  • ENABLE_CRC_ERROR_PIN
  • ENABLE_CVPCIE_CONFDONE
  • ENABLE_CVP_CONFDONE
  • ENABLE_DA_RULE
  • ENABLE_DEVICE_WIDE_OE
  • ENABLE_DEVICE_WIDE_RESET
  • ENABLE_DISABLED_STRATIX_LVDS_MODES
  • ENABLE_DRC
  • ENABLE_DRC_SETTINGS
  • ENABLE_ED_CRC_CHECK
  • ENABLE_EXTRA_DQ_DELAY
  • ENABLE_FALLBACK_TO_EXTERNAL_FLASH
  • ENABLE_HOLD_BACK_OFF
  • ENABLE_HOLD_MULTICYCLE
  • ENABLE_HPS_INTERNAL_TIMING
  • ENABLE_INCREMENTAL_DESIGN
  • ENABLE_INCREMENTAL_REUSE
  • ENABLE_INCREMENTAL_SYNTHESIS
  • ENABLE_INIT_DONE_OUTPUT
  • ENABLE_IP_DEBUG
  • ENABLE_JTAG_BST_SUPPORT
  • ENABLE_JTAG_PIN_SHARING
  • ENABLE_LAB_SHARING_WITH_PARENT_PARTITION
  • ENABLE_LLIS
  • ENABLE_LOGIC_ANALYZER_INTERFACE
  • ENABLE_LOW_VOLT_MODE_FLEX10K
  • ENABLE_LOW_VOLT_MODE_FLEX6K
  • ENABLE_LOW_VOLT_MODE
  • ENABLE_M512
  • ENABLE_MERCURY_CDR
  • ENABLE_MIXED_PORT_RDW_OLD_DATA_FOR_RAM_WITH_TWO_CLOCKS
  • ENABLE_MULTITAP
  • ENABLE_NCEO_OUTPUT
  • ENABLE_NCE_PIN
  • ENABLE_NCONFIG_FROM_CORE
  • ENABLE_OCT_DONE
  • ENABLE_OCTDONE
  • ENABLE_PR_PINS
  • ENABLE_RAPID_RECOMPILE
  • ENABLE_RECOVERY_REMOVAL_ANALYSIS
  • ENABLE_REDUCED_MEMORY_MODE
  • ENABLE_SIGNALTAP
  • ENABLE_SMART_VOLTAGE_ID
  • ENABLE_SOURCE_MULTICYCLE_HOLD
  • ENABLE_SOURCE_MULTICYCLE
  • ENABLE_SPI_MODE_CHECK
  • ENABLE_SRC_HOLD_MULTICYCLE
  • ENABLE_SRC_MULTICYCLE
  • ENABLE_STATE_MACHINE_INFERENCE
  • ENABLE_STRATIX_II_DPA_DEBUG
  • ENABLE_STRATIXII_DPA_DEBUG
  • ENABLE_STRATIX_II_LVDS_LOOPBACK
  • ENABLE_STRATIXII_LVDS_LOOPBACK
  • ENABLE_STRICT_PRESERVATION
  • ENABLE_SYNCH_INPUT_REGISTER_1S25
  • ENABLE_TRI
  • ENABLE_UNUSED_RX_CLOCK_WORKAROUND
  • ENABLE_VREFA_PIN
  • ENABLE_VREFB_PIN
  • ENCRYPTED_LUTMASK
  • ENFORCE_CONFIGURATION_VCCIO
  • EN_SPI_IO_WEAK_PULLUP
  • EN_USER_IO_WEAK_PULLUP
  • EPROM_JTAG_CODE_APEX20K
  • EPROM_JTAG_CODE_DALI
  • EPROM_JTAG_CODE_FLEX10K
  • EPROM_JTAG_CODE_FLEX6K
  • EPROM_JTAG_CODE
  • EPROM_JTAG_CODE_YEAGER
  • EPROM_USE_CHECKSUM_AS_USERCODE
  • EQ_BW_1
  • EQ_BW_2
  • EQ_BW_3
  • EQ_BW_4
  • EQC_AUTO_BREAK_CONE
  • EQC_AUTO_COMP_LOOP_CUT
  • EQC_AUTO_INVERSION
  • EQC_AUTO_PORTSWAP
  • EQC_AUTO_TERMINATE
  • EQC_BBOX_MERGE
  • EQC_CONSTANT_DFF_DETECTION
  • EQC_DETECT_DONT_CARES
  • EQC_DFF_SS_EMULATION
  • EQC_DUPLICATE_DFF_DETECTION
  • EQC_ENUM_AUTO_BREAK_CONE
  • EQC_ENUM_AUTO_COMP_LOOP_CUT
  • EQC_ENUM_AUTO_INVERSION
  • EQC_ENUM_AUTO_PORTSWAP
  • EQC_ENUM_AUTO_TERMINATE
  • EQC_ENUM_BBOX_MERGE
  • EQC_ENUM_CONSTANT_DFF_DETECTION
  • EQC_ENUM_DETECT_DONT_CARES
  • EQC_ENUM_DFF_SS_EMULATION
  • EQC_ENUM_DUPLICATE_DFF_DETECTION
  • EQC_ENUM_IO_BUFFER_CONVERSION
  • EQC_ENUM_LVDS_MERGE
  • EQC_ENUM_MAC_REGISTER_UNPACK
  • EQC_ENUM_MANUAL_MAP_LIST
  • EQC_ENUM_MAX_BDD_NODES
  • EQC_ENUM_PARAMETER_CHECK
  • EQC_ENUM_POWER_UP_COMPARE
  • EQC_ENUM_RAM_REGISTER_UNPACK
  • EQC_ENUM_RAM_UNMERGING
  • EQC_ENUM_RENAMING_RULES
  • EQC_ENUM_RENAMING_RULES_LIST
  • EQC_ENUM_SET_PARTITION_BB_TO_VCC_GND
  • EQC_ENUM_SHOW_ALL_MAPPED_POINTS
  • EQC_ENUM_STRUCTURE_MATCHING
  • EQC_ENUM_SUB_CONE_REPORT
  • EQC_LVDS_MERGE
  • EQC_MAC_REGISTER_UNPACK
  • EQC_PARAMETER_CHECK
  • EQC_POWER_UP_COMPARE
  • EQC_RAM_REGISTER_UNPACK
  • EQC_RAM_UNMERGING
  • EQC_RENAMING_RULES
  • EQC_RENAMING_RULES_LIST
  • EQC_SET_PARTITION_BB_TO_VCC_GND
  • EQC_SHOW_ALL_MAPPED_POINTS
  • EQC_STRUCTURE_MATCHING
  • EQC_SUB_CONE_REPORT
  • EQUATION_FILE
  • EQUIVALENCE_CHECKER_ASSIGNMENT
  • EQZP_DIS_PEAKING
  • EQZP_EN_PEAKING
  • ERROR_CHECK_FREQUENCY_DIVISOR
  • ESTIMATE_POWER_CONSUMPTION
  • EXCALIBUR_CONFIGURATION_DEVICE
  • EXCALIBUR_CONFIGURATION_SCHEME
  • EXC_BUSTRANS_SIM_FILE
  • EXCLUDE_FMAX_PATHS_GREATER_THAN
  • EXCLUDE_SLACK_PATHS_GREATER_THAN
  • EXCLUDE_TCO_PATHS_LESS_THAN
  • EXCLUDE_TH_PATHS_LESS_THAN
  • EXCLUDE_TPD_PATHS_LESS_THAN
  • EXCLUDE_TSU_PATHS_LESS_THAN
  • EXCLUSIVE_IO_GROUP
  • EXPANDED
  • EXTENDS_TOP_BLOCK
  • EXTERNAL_FEEDBACK
  • EXTERNAL_FLASH_FALLBACK_ADDRESS
  • EXTERNAL_INPUT_DELAY
  • EXTERNAL
  • EXTERNAL_LVDS_RX_USES_DPA
  • EXTERNAL_OUTPUT_DELAY
  • EXTERNAL_PIN_CONNECTION
  • EXTRACT_AND_OPTIMIZE_BUS_MUXES
  • EXTRACT_VERILOG_STATE_MACHINES
  • EXTRACT_VHDL_STATE_MACHINES
  • EXTRA_EFFORT
  • EXTRA
  • EYEQ_BW_1G_TO_2P5G
  • EYEQ_BW_2P5G_TO_7P5G
  • EYEQ_BW_GREATER_THAN_7P5G
  • EYEQ_BW_LESS_THAN_1G
  • F10K_ACEX1K_PCI_LOW_CAP
  • FALLBACK_TO_EXTERNAL_FLASH
  • FALL
  • FALSE
  • FANIN_PER_CELL_MAX7000
  • FAP_NAME
  • FAR_GLOBAL_CLOCK
  • FAR_REGIONAL_CLOCK
  • FAST_FIT_COMPILATION
  • FAST_FIT
  • FAST_INPUT_REGISTER
  • FAST_IO
  • FAST
  • FAST_OCT_REGISTER
  • FAST_OUTPUT_ENABLE_REGISTER
  • FAST_OUTPUT_REGISTER
  • FAST_PASSIVE_PARALLEL
  • FAST_POR_DELAY
  • FASTROW_INTERCONNECT
  • FAST_VIO
  • FBCLK_COUNTER_OUT
  • FFFFFFFF
  • FINAL_PLACEMENT_OPTIMIZATION
  • FIR_POST_1T_NEG
  • FIR_POST_1T_POS
  • FIR_POST_2T_NEG
  • FIR_POST_2T_POS
  • FIR_PRE_1T_NEG
  • FIR_PRE_1T_POS
  • FIR_PRE_2T_NEG
  • FIR_PRE_2T_POS
  • FIT_ATTEMPTS_TO_SKIP
  • FIT_INI_VARS
  • FIT_ONLY_ONE_ATTEMPT
  • FIT_SCRIPT_FILE
  • FIT_SEED
  • FIT_SMART_IO
  • FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND
  • FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION
  • FITTER_ASSIGNMENT
  • FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN
  • FITTER_EARLY_TIMING_ESTIMATE_MODE
  • FITTER_EFFORT
  • FITTER_ONLY
  • FITTER_OPTIMIZED
  • FITTER_PLL_SCAN_CHAIN_RECONFIG_FILE
  • FITTER_TCL_CALLBACK_FILE
  • FITTER_WILDARDS
  • FITTER_WILDCARDS
  • FIT_WYSIWYG_PIA
  • FLASH_NCE_RESERVED
  • FLASH_PROGRAMMING_FILE_NAME
  • FLEX10K_CARRY_CHAIN_LENGTH
  • FLEX10K_CLIQUE_TYPE
  • FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE
  • FLEX10K_CONFIGURATION_DEVICE
  • FLEX10K_CONFIGURATION_SCHEME
  • FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
  • FLEX10K_DEVICE_IO_STANDARD
  • FLEX10K_ENABLE_LOCK_OUTPUT
  • FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE
  • FLEX10KE_PCI_LOW_CAP_ADJUST
  • FLEX10K_JTAG_USER_CODE
  • FLEX10K_MAX_PERIPHERAL_OE
  • FLEX10K_OPTIMIZATION_TECHNIQUE
  • FLEX10K_TECHNOLOGY_MAPPER
  • FLEX6000
  • FLEX6K_CARRY_CHAIN_LENGTH
  • FLEX6K_CLIQUE_TYPE
  • FLEX6K_CONFIG_DEVICE_JTAG_USER_CODE
  • FLEX6K_CONFIGURATION_DEVICE
  • FLEX6K_CONFIGURATION_SCHEME
  • FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
  • FLEX6K_DEVICE_IO_STANDARD
  • FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE
  • FLEX6K_JTAG_USER_CODE
  • FLEX6K_LOCAL_ROUTING_DESTINATION
  • FLEX6K_LOCAL_ROUTING_SOURCE
  • FLEX6K_OPTIMIZATION_TECHNIQUE
  • FLEX6K_TECHNOLOGY_MAPPER
  • FLEXIBLE_TIMING
  • FLOATING
  • FLOW_DISABLE_ASSEMBLER
  • FLOW_ENABLE_HC_COMPARE
  • FLOW_ENABLE_HCII_COMPARE
  • FLOW_ENABLE_HYPER_RETIMER_FAST_FORWARD
  • FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS
  • FLOW_ENABLE_PARALLEL_MODULES
  • FLOW_ENABLE_POWER_ANALYZER
  • FLOW_ENABLE_RTL_VIEWER
  • FLOW_ENABLE_TIMING_CONSTRAINT_CHECK
  • FLOW_HARDCOPY_DESIGN_READINESS_CHECK
  • FMAX_REQUIREMENT
  • FOCUS_ENTITY_NAME
  • FORCE_ALL_TILES_WITH_FAILING_TIMING_PATHS_TO_HIGH_SPEED
  • FORCE_ALL_USED_TILES_TO_HIGH_SPEED
  • FORCED_IF_ASYNCHRONOUS
  • FORCED
  • FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS
  • FORCE_FRACTURED_MODE_ALM_IMPLEMENTATION
  • FORCE_MERGE_PLL_FANOUTS
  • FORCE_NON_FRACTURED_MODE_ALM_IMPLEMENTATION
  • FORCE_POINT_TO_POINT
  • FORCE_RECOMPILE
  • FORCE_SLACK
  • FORCE_SSMCLK_TO_ISMCLK
  • FORCE_SYNCH_CLEAR
  • FORM_DDR_CLUSTERING_CLIQUE
  • FPLL
  • FPLL_VREG1_BOOST_1_STEP
  • FPLL_VREG1_BOOST_2_STEP
  • FPLL_VREG1_BOOST_3_STEP
  • FPLL_VREG1_BOOST_4_STEP
  • FPLL_VREG1_BOOST_5_STEP
  • FPLL_VREG1_BOOST_6_STEP
  • FPLL_VREG1_BOOST_7_STEP
  • FPLL_VREG1_NO_VOLTAGE_BOOST
  • FPLL_VREG_NO_VOLTAGE_BOOST
  • FREQ_12_5MHZ
  • FREQ_20MHZ
  • FREQ_40MHZ
  • FSDA_LEVEL_AUTO
  • FSDA_LEVEL_C1
  • FSDA_LEVEL_C2
  • FSDA_LEVEL_U
  • FSM_CAT
  • FSM_RULE_DEADLOCK_STATE
  • FSM_RULE_NO_RESET_STATE
  • FSM_RULE_NO_SZER_ACLK_DOMAIN
  • FSM_RULE_UNREACHABLE_STATE
  • FSM_RULE_UNUSED_TRANSITION
  • FSYN_AND_ICP_REGTEST_MODE
  • FULL_COMPILATION
  • FULL_INCREMENTAL_COMPILATION
  • FULL_INCREMENTAL_DESIGN
  • FULL_VPACK
  • FULL_VPR
  • FUNCTIONAL
  • FV_BLACKBOX
  • G8A94
  • G8H9
  • GBE_1250
  • GDF_FILE
  • GEN3_OFF
  • GEN3_ON
  • GEN4_OFF
  • GEN4_ON
  • GENERAL_POOL
  • GENERATE_CONFIG_HEXOUT_FILE
  • GENERATE_CONFIG_ISC_FILE
  • GENERATE_CONFIG_JAM_FILE
  • GENERATE_CONFIG_JBC_FILE_COMPRESSED
  • GENERATE_CONFIG_JBC_FILE
  • GENERATE_CONFIG_SVF_FILE
  • GENERATE_GXB_RECONFIG_MIF
  • GENERATE_GXB_RECONFIG_MIF_WITH_PLL
  • GENERATE_HEX_FILE
  • GENERATE_ISC_FILE
  • GENERATE_JAM_FILE
  • GENERATE_JBC_FILE_COMPRESSED
  • GENERATE_JBC_FILE
  • GENERATE_PMSF_FILES
  • GENERATE_RBF_FILE
  • GENERATE_SVF_FILE
  • GENERATE_TTF_FILE
  • GENERATION_DIRECTORY
  • GENERIC_TRAIT
  • GIGE
  • GIVE_ERROR
  • GIVE_INFO
  • GIVE_WARNING
  • GLITCH_DETECTION
  • GLITCH_DETECTION_PULSE
  • GLITCH_INTERVAL
  • GLOBAL_SIGNAL_CLKCTRL_LOCATION
  • GNDIO_CURRENT_1PT8V
  • GNDIO_CURRENT_2PT5V
  • GNDIO_CURRENT_GTL
  • GNDIO_CURRENT_GTL_PLUS
  • GNDIO_CURRENT_LVCMOS
  • GNDIO_CURRENT_LVTTL
  • GNDIO_CURRENT_PCI
  • GNDIO_CURRENT_SSTL2_CLASS1
  • GNDIO_CURRENT_SSTL2_CLASS2
  • GNDIO_CURRENT_SSTL3_CLASS1
  • GNDIO_CURRENT_SSTL3_CLASS2
  • GNU_ASM_COMMAND_LINE
  • GNU_CPP_COMMAND_LINE
  • GNU_CSP_ASM_COMMAND_LINE
  • GNU_CSP_CPP_COMMAND_LINE
  • GNU_CSP_LINK_COMMAND_LINE
  • GNU_LINK_COMMAND_LINE
  • GNUPRO_ARM_ASM_COMMAND_LINE
  • GNUPRO_ARM_CPP_COMMAND_LINE
  • GNUPRO_ARM_LINK_COMMAND_LINE
  • GNUPRO_MIPS_ASM_COMMAND_LINE
  • GNUPRO_MIPS_CPP_COMMAND_LINE
  • GNUPRO_MIPS_LINK_COMMAND_LINE
  • GNUPRO_NIOS_ASM_COMMAND_LINE
  • GNUPRO_NIOS_CPP_COMMAND_LINE
  • GNUPRO_NIOS_LINK_COMMAND_LINE
  • GPH9
  • GPON_1244
  • GPON_155
  • GPON_2488
  • GPON_622
  • GROUNDED
  • GROUP_COMB_LOGIC_IN_CLOUD
  • GROUP_COMB_LOGIC_IN_CLOUD_TMV
  • GROUP_NODES
  • GROUP_NODES_TMV
  • GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME
  • GXB_0PPM_CLOCK_GROUP_DRIVER
  • GXB_0PPM_CLOCK_GROUP
  • GXB_0PPM_CORECLK
  • GXB_0PPM_CORE_CLOCK
  • GXB_CLOCK_GROUP_DRIVER
  • GXB_CLOCK_GROUP
  • GXB_IO_PIN_TERMINATION
  • GXB_RECONFIG_GROUP
  • GXB_RECONFIG_MIF_PLL
  • GXB_REFCLK_COUPLING_TERMINATION_SETTING
  • GXB_REFCLK_PIN_TERMINATION
  • GXB_RESERVED_TRANSMIT_CHANNEL
  • GXB_TX_PLL_RECONFIG_GROUP
  • GXB_VCCA_VOLTAGE
  • GXB_VCCR_VCCT_VOLTAGE
  • HALF
  • HALF_MEGALAB_COLUMN
  • HALF_RESOLUTION
  • HALF_ROW
  • HARD_BLOCK_PARTITION
  • HARDCOPY_DEVICE_IDENTIFIER
  • HARDCOPY_EXTERNAL_CLOCK_JITTER
  • HARDCOPY_FLOW_AUTOMATION
  • HARDCOPYII_COMPANION_REVISION_NAME
  • HARDCOPYII_POWER_ON_EXTRA_DELAY
  • HARDCOPYII_RUN_COMPARISON_ON_EVERY_COMPILE
  • HARDCOPYII_SAVE_MIGRATION_INFO_DURING_COMPILATION
  • HARDCOPY_INDIVIDUAL_SETTINGS
  • HARDCOPY_INPUT_TRANSITION_CLOCK_PIN
  • HARDCOPY_INPUT_TRANSITION_DATA_PIN
  • HARDCOPY_NEW_PROJECT_PATH
  • HARD_POST_FIT
  • HCII_OUTPUT_DIR
  • HC_OUTPUT_DIR
  • HCPY_ALOAD_SIGNALS
  • HCPY_ASYN_RAM
  • HCPY_CAT
  • HCPY_EXCEED_RAM_USAGE
  • HCPY_EXCEED_USER_IO_USAGE
  • HCPY_EXT_CLK_JITTER_CHECK
  • HCPY_EXT_CLK_JITTER_EDGE
  • HCPY_EXT_CLK_JITTER
  • HCPY_ILLEGAL_HC_DEV_PKG
  • HCPY_INPUT_TRANS_CLK_PIN
  • HCPY_INPUT_TRANS_DATA_PIN
  • HCPY_PLL_MULTIPLE_CLK_NETWORK_TYPES
  • HCPY_TRANS_CONDITION_CLK_PIN
  • HCPY_TRANS_CONDITION_DATA_PIN
  • HCPY_TRANS_EDGE_CLK_PIN
  • HCPY_TRANS_EDGE_DATA_PIN
  • HCPY_VREF_PINS
  • HDL_INITIAL_FANOUT_LIMIT
  • HDL_INTERFACE_INSTANCE_ENTITY
  • HDL_INTERFACE_INSTANCE_NAME
  • HDL_INTERFACE_INSTANCE_PARAMETERS
  • HDL_INTERFACE_OUTPUT_PATH
  • HDL_MESSAGE_LEVEL
  • HDL_MESSAGE_OFF
  • HDL_MESSAGE_ON
  • HDL_SETTINGS
  • HDL_VERSION
  • HEX_FILE_COUNT_UP_DOWN
  • HEX_FILE_COUNT_UP_OR_DOWN
  • HEX_FILE_START_ADDRESS
  • HEXOUT_FILE_COUNT_DIRECTION
  • HEXOUT_FILE_START_ADDRESS
  • HEX_OUTPUT_FILE
  • HIDE_RCF_WARNINGS
  • HIERARCHICAL_COMPILE
  • HIERARCHY_BLACKBOX_FILE
  • HIGH_PERF
  • HIGH_PERFORMANCE_EFFORT
  • HIGH_POWER_EFFORT
  • HIGH_VCM
  • HIGIG_4062
  • HIGIG_5000
  • HIGIG_6250
  • HIGIG_6562
  • HOLD_MULTICYCLE_DEFAULT
  • HOLD_RELATIONSHIP
  • HPS_AUTO_PARTITION
  • HPS_EARLY_IO_RELEASE
  • HPS_IO
  • HPS_ISW_FILE
  • HPS_LOCATION
  • HPS_PARTITION
  • HSSI_A10_CDR_PLL_ANALOG_MODE
  • HSSI_A10_CDR_PLL_POWER_MODE
  • HSSI_A10_CDR_PLL_REQUIRES_GT_CAPABLE_CHANNEL
  • HSSI_A10_CDR_PLL_UC_RO_CAL
  • HSSI_A10_CMU_FPLL_ANALOG_MODE
  • HSSI_A10_CMU_FPLL_PLL_DPRIO_CLK_VREG_BOOST
  • HSSI_A10_CMU_FPLL_PLL_DPRIO_FPLL_VREG1_BOOST
  • HSSI_A10_CMU_FPLL_PLL_DPRIO_FPLL_VREG_BOOST
  • HSSI_A10_CMU_FPLL_PLL_DPRIO_STATUS_SELECT
  • HSSI_A10_CMU_FPLL_POWER_MODE
  • HSSI_A10_LC_PLL_ANALOG_MODE
  • HSSI_A10_LC_PLL_POWER_MODE
  • HSSI_A10_PM_UC_CLKDIV_SEL
  • HSSI_A10_PM_UC_CLKSEL_CORE
  • HSSI_A10_PM_UC_CLKSEL_OSC
  • HSSI_A10_REFCLK_TERM_TRISTATE
  • HSSI_A10_RX_ADAPT_DFE_CONTROL_SEL
  • HSSI_A10_RX_ADAPT_DFE_SEL
  • HSSI_A10_RX_ADAPT_VGA_SEL
  • HSSI_A10_RX_ADAPT_VREF_SEL
  • HSSI_A10_RX_ADP_CTLE_ACGAIN_4S
  • HSSI_A10_RX_ADP_CTLE_EQZ_1S_SEL
  • HSSI_A10_RX_ADP_DFE_FLTAP_POSITION
  • HSSI_A10_RX_ADP_DFE_FXTAP10
  • HSSI_A10_RX_ADP_DFE_FXTAP10_SGN
  • HSSI_A10_RX_ADP_DFE_FXTAP11
  • HSSI_A10_RX_ADP_DFE_FXTAP11_SGN
  • HSSI_A10_RX_ADP_DFE_FXTAP1
  • HSSI_A10_RX_ADP_DFE_FXTAP2
  • HSSI_A10_RX_ADP_DFE_FXTAP2_SGN
  • HSSI_A10_RX_ADP_DFE_FXTAP3
  • HSSI_A10_RX_ADP_DFE_FXTAP3_SGN
  • HSSI_A10_RX_ADP_DFE_FXTAP4
  • HSSI_A10_RX_ADP_DFE_FXTAP4_SGN
  • HSSI_A10_RX_ADP_DFE_FXTAP5
  • HSSI_A10_RX_ADP_DFE_FXTAP5_SGN
  • HSSI_A10_RX_ADP_DFE_FXTAP6
  • HSSI_A10_RX_ADP_DFE_FXTAP6_SGN
  • HSSI_A10_RX_ADP_DFE_FXTAP7
  • HSSI_A10_RX_ADP_DFE_FXTAP7_SGN
  • HSSI_A10_RX_ADP_DFE_FXTAP8
  • HSSI_A10_RX_ADP_DFE_FXTAP8_SGN
  • HSSI_A10_RX_ADP_DFE_FXTAP9
  • HSSI_A10_RX_ADP_DFE_FXTAP9_SGN
  • HSSI_A10_RX_ADP_LFEQ_FB_SEL
  • HSSI_A10_RX_ADP_ONETIME_DFE
  • HSSI_A10_RX_ADP_VGA_SEL
  • HSSI_A10_RX_ADP_VREF_SEL
  • HSSI_A10_RX_BYPASS_EQZ_STAGES_234
  • HSSI_A10_RX_EQ_BW_SEL
  • HSSI_A10_RX_EQ_DC_GAIN_TRIM
  • HSSI_A10_RX_INPUT_VCM_SEL
  • HSSI_A10_RX_LINK
  • HSSI_A10_RX_OFFSET_CANCELLATION_CTRL
  • HSSI_A10_RX_ONE_STAGE_ENABLE
  • HSSI_A10_RX_POWER_MODE
  • HSSI_A10_RX_QPI_ENABLE
  • HSSI_A10_RX_RX_SEL_BIAS_SOURCE
  • HSSI_A10_RX_SD_OUTPUT_OFF
  • HSSI_A10_RX_SD_OUTPUT_ON
  • HSSI_A10_RX_SD_THRESHOLD
  • HSSI_A10_RX_TERM_SEL
  • HSSI_A10_RX_TERM_TRI_ENABLE
  • HSSI_A10_RX_UC_RX_DFE_CAL
  • HSSI_A10_RX_VCCELA_SUPPLY_VOLTAGE
  • HSSI_A10_RX_VCM_CURRENT_ADD
  • HSSI_A10_RX_VCM_SEL
  • HSSI_A10_RX_XRX_PATH_ANALOG_MODE
  • HSSI_A10_TX_COMPENSATION_EN
  • HSSI_A10_TX_DCD_DETECTION_EN
  • HSSI_A10_TX_DPRIO_CGB_VREG_BOOST
  • HSSI_A10_TX_LINK
  • HSSI_A10_TX_LOW_POWER_EN
  • HSSI_A10_TX_POWER_MODE
  • HSSI_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP
  • HSSI_A10_TX_PRE_EMP_SIGN_2ND_POST_TAP
  • HSSI_A10_TX_PRE_EMP_SIGN_PRE_TAP_1T
  • HSSI_A10_TX_PRE_EMP_SIGN_PRE_TAP_2T
  • HSSI_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP
  • HSSI_A10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP
  • HSSI_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T
  • HSSI_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T
  • HSSI_A10_TX_RES_CAL_LOCAL
  • HSSI_A10_TX_RX_DET
  • HSSI_A10_TX_RX_DET_OUTPUT_SEL
  • HSSI_A10_TX_RX_DET_PDB
  • HSSI_A10_TX_SLEW_RATE_CTRL
  • HSSI_A10_TX_TERM_CODE
  • HSSI_A10_TX_TERM_SEL
  • HSSI_A10_TX_UC_DCD_CAL
  • HSSI_A10_TX_UC_GEN3
  • HSSI_A10_TX_UC_GEN4
  • HSSI_A10_TX_UC_SKEW_CAL
  • HSSI_A10_TX_UC_TXVOD_CAL_CONT
  • HSSI_A10_TX_UC_TXVOD_CAL
  • HSSI_A10_TX_UC_VCC_SETTING
  • HSSI_A10_TX_USER_FIR_COEFF_CTRL_SEL
  • HSSI_A10_TX_VOD_OUTPUT_SWING_CTRL
  • HSSI_A10_TX_XTX_PATH_ANALOG_MODE
  • HSSI_ADCE_RGEN_MODE
  • HSSI_ANALOG_SETTINGS_PROTOCOL
  • HSSI_FAST_LOCK_MODE
  • HSSI_GT_FORCE_VCO_CONST
  • HSSI_GT_RX_CTLE
  • HSSI_GT_RX_RX_DC_GAIN
  • HSSI_GT_RX_VCM_SEL
  • HSSI_GT_TERMINATION
  • HSSI_GT_TX_COMMON_MODE_DRIVER_SEL
  • HSSI_GT_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP
  • HSSI_GT_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP
  • HSSI_GT_TX_SIG_INV_PRE_TAP
  • HSSI_GT_TX_VOD_SWITCHING_CTRL_MAIN_TAP
  • HSSI_ODI_EYE_MONITOR_BW_SEL
  • HSSI_PARAMETER
  • HSSI_REFCLK_TERMINATION
  • HSSI_RX_ACGAIN_A
  • HSSI_RX_ACGAIN_V
  • HSSI_RX_ADCE_HSF_HFBW
  • HSSI_RX_ADCE_RGEN_BW
  • HSSI_RX_BYPASS_EQZ_STAGES_234
  • HSSI_RX_CT_EQUALIZER_SETTING
  • HSSI_RX_DFE_PI_BW
  • HSSI_RX_ENABLE_RX_GAINCTRL_PCIEMODE
  • HSSI_RX_EQ_BW_SEL
  • HSSI_RX_INPUT_VCM_SEL
  • HSSI_RX_PDB_SD
  • HSSI_RX_PMOS_GAIN_PEAK
  • HSSI_RX_QPI_ENABLE
  • HSSI_RX_RX_DC_GAIN
  • HSSI_RX_RX_SEL_BIAS_SOURCE
  • HSSI_RX_SD_OFF
  • HSSI_RX_SD_ON
  • HSSI_RX_SD_THRESHOLD
  • HSSI_RX_SEL_HALF_BW
  • HSSI_RX_VCCELA_SUPPLY_VOLTAGE
  • HSSI_RX_VCM_CURRENT_ADD
  • HSSI_RX_VCM_SEL
  • HSSI_TERMINATION
  • HSSI_TX_COMMON_MODE_DRIVER_SEL
  • HSSI_TX_DRIVER_RESOLUTION_CTRL
  • HSSI_TX_FIR_COEFF_CTRL_SEL
  • HSSI_TX_LOCAL_IB_CTL
  • HSSI_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP
  • HSSI_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP
  • HSSI_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP_USER
  • HSSI_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP
  • HSSI_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_USER
  • HSSI_TX_QPI_EN
  • HSSI_TX_RX_DET
  • HSSI_TX_RX_DET_OUTPUT_SEL
  • HSSI_TX_RX_DET_PDB
  • HSSI_TX_SIG_INV_2ND_TAP
  • HSSI_TX_SIG_INV_PRE_TAP
  • HSSI_TX_SLEW_RATE_CTRL
  • HSSI_TX_SWING_BOOST
  • HSSI_TX_VCM_CTRL_SEL
  • HSSI_TX_VCM_CURRENT_ADDL
  • HSSI_TX_VOD_BOOST
  • HSSI_TX_VOD_SWITCHING_CTRL_MAIN_TAP
  • HSSI_VCCEH_VOLTAGE
  • HSSI_VCCER_VCCET_VOLTAGE
  • HTML_FILE
  • HTML_REPORT_FILE
  • HUB_AUTO_INSERT
  • HUB_ENTITY_NAME
  • HUB_INSTANCE_NAME
  • HUB_SOURCE_FILE
  • HYBRID_FLOW_NEW_EXTRACTOR
  • HYPER_AWARE_OPTIMIZE_REGISTER_CHAINS
  • HYPER_AWARE_OPTIMIZE_SHORT_PATHS
  • HYPER_AWARE_OPTIMIZE_TIMING
  • HYPER_AWARE_REGISTER_PLACEMENT
  • HYPER_AWARE_SET_REGISTER_BYPASS
  • HYPER_AWARE_SET_REGISTER_INITIAL_STATE
  • HYPER_EARLY_RETIMER
  • HYPER_REGISTER
  • HYPER_RETIMER_ADD_PIPELINING
  • HYPER_RETIMER_FALSE_PATH_RESTRICTION
  • HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING
  • HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX
  • HYPER_RETIMER_FAST_FORWARD_AGGRESSIVE_EXPLORATION
  • HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR
  • HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS
  • HYPER_RETIMER_FAST_FORWARD_EMULATE_ADD_PIPELINING
  • HYPER_RETIMER_FAST_FORWARD_EMULATE_AGGRESSIVE_EXPLORATION
  • HYPER_RETIMER_FAST_FORWARD_EMULATE_ASYNCH_CLEAR
  • HYPER_RETIMER_FAST_FORWARD_EMULATE_USER_PRESERVE_RESTRICTION
  • HYPER_RETIMER_FAST_FORWARD
  • HYPER_RETIMER_FAST_FORWARD_OFF_DESCRIPTION
  • HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS
  • HYPER_RETIMER_FAST_FORWARD_TARGET_MAX_PERFORMANCE
  • HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION
  • HYPER_RETIMER
  • HYPER_RETIMER_REGISTERS_REMOVED
  • IB_22OHM
  • IB_29OHM
  • IB_42OHM
  • IB_49OHM
  • IEEE_10G_BASE_CR_10312
  • IEEE_10G_KR_10312
  • IEEE_40G_BASE_KR_10312
  • IGNORE_CARRY_BUFFERS
  • IGNORE_CARRY
  • IGNORE_CASCADE_BUFFERS
  • IGNORE_CASCADE
  • IGNORE_CLOCK_SETTINGS
  • IGNORE_DUPLICATE_DESIGN_ENTITY
  • IGNORE_GLOBAL_BUFFERS
  • IGNORE_GLOBAL
  • IGNORE_HSSI_COLUMN_POWER_FOR_BTI_MITIGATION
  • IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS
  • IGNORE_LCELL
  • IGNORE_LCELL_MAX7000
  • IGNORE_MAX_FANOUT_ASSIGNMENTS
  • IGNORE_MODE_FOR_MERGE
  • IGNORE_PARTITIONS
  • IGNORE_ROW_GLOBAL_BUFFERS
  • IGNORE_ROW_GLOBAL
  • IGNORE_SOFT
  • IGNORE_SOFT_MAX7000
  • IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF
  • IGNORE_TRANSLATE_OFF
  • IGNORE_VERILOG_INITIAL_CONSTRUCTS
  • IGNORE_VREF_RESTRICTION
  • IMMEDIATE_ASSERTION_FAIL_ACTION
  • IMMEDIATE_ASSERTION_FAIL_MESSAGE
  • IMMEDIATE_ASSERTION
  • IMMEDIATE_ASSERTION_PASS_MESSAGE
  • IMMEDIATE_ASSERTION_STATE
  • IMMEDIATE_ASSERTION_TEST_CONDITION
  • IMPLEMENT_AS_CLOCK_ENABLE
  • IMPLEMENT_AS_LCELL
  • IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL
  • IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE
  • IMPORT_BASED_POST_FIT
  • IMPORT_BLOCK
  • IMPORTED
  • IMPORT
  • INCLUDED_IN_OLD_CHIP_SECTION
  • INCLUDED_IN_OLD_PROJECT_INFO_SECTION
  • INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS
  • INCLUDE_IN_ALL_TB2
  • INCLUDE_IN_COMPILER_REPORT
  • INCLUDE_IN_FITTER_TB2
  • INCLUDE_IN_POWER_TB2
  • INCLUDE_IN_SIMULATOR_REPORT
  • INCLUDE_IN_SYNTHESIS_REPORT
  • INCLUDE_IN_SYNTHESIS_TB2
  • INCLUDE_IN_TIMING_TB2
  • INCLUDE_PATHS_GREATER_THAN_TCO
  • INCLUDE_PATHS_GREATER_THAN_TH
  • INCLUDE_PATHS_GREATER_THAN_TPD
  • INCLUDE_PATHS_GREATER_THAN_TSU
  • INCLUDE_PATHS_LESS_THAN_FMAX
  • INCLUDE_PATHS_LESS_THAN_SLACK
  • INCLUDE_PIN_DELAYS_IN_CALCULATIONS
  • INC_PLACE_PREF_LOCATION
  • INC_PLC_MODE
  • INCREASE_DELAY_TO_OUTPUT_ENABLE_PIN
  • INCREASE_DELAY_TO_OUTPUT_PIN
  • INCREASE_INPUT_CLOCK_ENABLE_DELAY
  • INCREASE_INPUT_DELAY_TO_CE_IO_REGISTER
  • INCREASE_OUTPUT_CLOCK_ENABLE_DELAY
  • INCREASE_OUTPUT_ENABLE_CLOCK_ENABLE_DELAY
  • INCREASE_OUTPUT_ENABLE_CLOCK_ENABLE_DELAYR
  • INCREASE_TZX_DELAY_TO_OUTPUT_PIN
  • INCREMENTAL_COMPILATION_EXPORT_FILE
  • INCREMENTAL_COMPILATION_EXPORT_FLATTEN
  • INCREMENTAL_COMPILATION_EXPORT_NETLIST_TYPE
  • INCREMENTAL_COMPILATION_EXPORT_PARTITION_NAME
  • INCREMENTAL_COMPILATION_EXPORT_POST_FIT
  • INCREMENTAL_COMPILATION_EXPORT_POST_SYNTH
  • INCREMENTAL_COMPILATION_EXPORT_ROUTING
  • INCREMENTAL_DESIGN_PARTITION
  • INCREMENTAL_INPUT_VECTOR_FILE
  • INCREMENTAL_SYNTHESIS_FULL
  • INCREMENTAL_SYNTHESIS_PARTITION
  • INCREMENTAL_SYNTHESIS_TOP
  • INCREMENTAL_TIME_INPUT
  • INCREMENTAL_VECTOR_INPUT_SOURCE
  • INCR_SIGNALTAP_PARTITION
  • INCR_TAP
  • INDIRECT_PORT_ASSIGNMENT
  • INERTIAL
  • INFER_RAMS_FROM_RAW_LOGIC
  • INIT_CLKUSR
  • INIT_DCLK
  • INIT_DONE_OPEN_DRAIN
  • INITIAL_PLACEMENT_CONFIGURATION
  • INIT_INTOSC
  • INNER_NUM
  • INPUT_DELAY_CHAIN
  • INPUT_EDGE
  • INPUT_MAX_DELAY
  • INPUT_MIN_DELAY
  • INPUT_OCT_VALUE
  • INPUT_PERSONA
  • INPUT_REFERENCE
  • INPUT_TERMINATION
  • INPUT_TRANSITION_TIME
  • INSERT_ADDITIONAL_LOGIC_CELL
  • INSERT_BOUNDARY_WIRE_LUTS
  • INSTANT_ON
  • INTERFACE_ROLE
  • INTERFACES
  • INTERFACE_TYPE
  • INTERLAKEN_11100
  • INTERLAKEN_12500
  • INTERLAKEN_3125
  • INTERLAKEN_6375
  • INTERLAKEN
  • INTERNAL_CONFIGURATION
  • INTERNAL_FLASH_UPDATE_MODE
  • INTERNAL_OSCILLATOR_DIVIDE_DOWN
  • INTERNAL_SCRUBBING
  • INTERNAL_VREF_MODE
  • INVERT_BASE_CLOCK
  • INVERTED_CLOCK
  • IO_12_LANE_INPUT_DATA_DELAY_CHAIN
  • IO_12_LANE_INPUT_DATA_DELAY
  • IO_12_LANE_INPUT_STROBE_DELAY_CHAIN
  • IO_12_LANE_INPUT_STROBE_DELAY
  • IOBANK
  • IOBANK_VCCIO
  • IO_MAXIMUM_TOGGLE_RATE
  • IO_PATHS_AND_MINIMUM_TPD_PATHS
  • IO_PLACEMENT_OPTIMIZATION
  • IOPLL
  • IO_SSO_CHECKING
  • IP_ADVISOR_FILE
  • IPA_FILE
  • IP_COMPONENT_AUTHOR
  • IP_COMPONENT_DESCRIPTION
  • IP_COMPONENT_DISPLAY_NAME
  • IP_COMPONENT_DOCUMENTATION_LINK
  • IP_COMPONENT_GROUP
  • IP_COMPONENT_INTERNAL
  • IP_COMPONENT_NAME
  • IP_COMPONENT_PARAMETER
  • IP_COMPONENT_REPORT_HIERARCHY
  • IP_COMPONENT_SETTING
  • IP_COMPONENT_VERSION
  • IP_DEBUG_VISIBLE
  • IP_GENERATED_DEVICE_FAMILY
  • IP_QSYS_MODE
  • IP_SHOW_ANALYSIS_MESSAGES
  • IP_SHOW_ELABORATION_MESSAGES
  • IP_TARGETED_DEVICE_FAMILY
  • IP_TARGETED_PART_TRAIT
  • IP_TOOL_ENV
  • IP_TOOL_HIERARCHY_LEVELS
  • IP_TOOL_NAME
  • IP_TOOL_VERSION
  • IPX_FILE
  • IS_DEBUG
  • IS_FREEFORM
  • ISP_CLAMP_STATE_DEFAULT
  • ISP_CLAMP_STATE
  • JESD204_A_B_12500
  • JESD204_A_B_6375
  • JOHNSON
  • JTAG_BST_SUPPORT_MAX7000
  • JTAG_USER_CODE_DALI
  • JTAG_USER_CODE_FLEX6K
  • KEEP_LCELL_FOLLOWING_PLL
  • L3HH
  • LARGE_PERIPHERY_CLOCK
  • LAST_QUARTUS_VERSION
  • LATE_CLOCK_LATENCY
  • LEVEL1
  • LEVEL2
  • LEVEL3
  • LIBRARY_SEARCH_ORDER
  • LICENSE_FILE
  • LIMIT_AHDL_INTEGERS_TO_32_BITS
  • LINEAR_FORMAT
  • LL_AUTO_SIZE
  • LL_COLOR
  • LL_CORE_ONLY
  • LL_ENABLED
  • LL_EXCLUDE
  • LL_FSDA_LEVEL
  • LL_FSDA_ROUTING_INTERFACE
  • LL_HEIGHT
  • LL_HORIZONTAL_FLIP
  • LL_IGNORE_IO_BANK_FSDA_CONSTRAINT
  • LL_IGNORE_IO_BANK_SECURITY_CONSTRAINT
  • LL_IGNORE_IO_PIN_FSDA_CONSTRAINT
  • LL_IGNORE_IO_PIN_SECURITY_CONSTRAINT
  • LL_IMPORT_FILE
  • LL_MEMBER_EXCEPTIONS
  • LL_MEMBER_OF_FSDA_ROUTING_INTERFACE
  • LL_MEMBER_OF
  • LL_MEMBER_OF_SECURITY_ROUTING_INTERFACE
  • LL_MEMBER_OPTION
  • LL_MEMBER_RESOURCE_EXCLUDE
  • LL_MEMBER_STATE
  • LL_NODE_LOCATION
  • LL_OLD_BEHAVIOR
  • LL_ORIGIN
  • LL_OUTPUT_SIGNAL_FSDA_LEVEL
  • LL_PARENT
  • LL_PATH_EXCLUDE
  • LL_PATH_INCLUDE
  • LL_PRIORITY
  • LL_PR_REGION
  • LL_RCF_IMPORT_FILE
  • LL_RECT
  • LL_REGION_SECURITY_LEVEL
  • LL_RESERVED_IS_LIMITED
  • LL_RESERVED
  • LL_RESERVED_MEMBERS_OF_IMMEDIATE_PARENT_REGION_HIERARCHY_ONLY
  • LL_RESERVE
  • LL_ROOT_REGION
  • LL_ROUGH
  • LL_ROUTING_REGION_EXPANSION_SIZE
  • LL_ROUTING_REGION
  • LL_SECURITY_ROUTING_INTERFACE
  • LL_SIGNAL_SECURITY_LEVEL
  • LL_SOFT
  • LL_SOURCE_PARTITION_HIERARCHY
  • LL_SOURCE_PARTITION
  • LL_SOURCE_REGION
  • LL_STATE
  • LL_WIDTH
  • LOCAL_LINE_DELAY_CHAIN
  • LOCATION_PIN_ASSIGNMENT
  • LOCKED
  • LOGIC_ANALYZER_INTERFACE_FILE
  • LOGIC_ELEMENTS
  • LOGICLOCK_ASSIGNMENT
  • LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT
  • LOGICLOCK_INCREMENTAL_COMPILE_FILE
  • LOGICLOCK_REGION
  • LOGIC_MINIMIZATION_SCRIPT
  • LOW_CAP_ADJUST_FLEX10KE
  • LOW_POWER
  • LOW_VCM
  • LVDS_CLOCK_DATA_DESKEW_ADJUST
  • LVDS_DESKEW
  • LVDS_DIRECT_LOOPBACK_MODE
  • LVDS_FIXED_CLOCK_DATA_PHASE
  • LVDS
  • LVDS_RX_REGISTER
  • M10K
  • M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY
  • M144K
  • M144K_USE_DCD
  • M20K
  • MACRO_HEAD
  • MACRO_MEMBER
  • MACRO_TIMING
  • MAP_FILE
  • MAPPER_SYNTHESIS_ASSIGNMENT
  • MASK_REVISION
  • MATCH_PLL_COMPENSATION_CLOCK
  • MAX10FPGA_CONFIGURATION_SCHEME
  • MAX15301
  • MAX7000B_VCCIO_IOBANK1
  • MAX7000B_VCCIO_IOBANK2
  • MAX7000_DEVICE_IO_STANDARD
  • MAX7000_ENABLE_JTAG_BST_SUPPORT
  • MAX7000_FANIN_PER_CELL
  • MAX7000_IGNORE_LCELL_BUFFERS
  • MAX7000_IGNORE_SOFT_BUFFERS
  • MAX7000_INDIVIDUAL_TURBO_BIT
  • MAX7000_JTAG_USER_CODE
  • MAX7000_OPTIMIZATION_TECHNIQUE
  • MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH
  • MAX7000S_JTAG_USER_CODE
  • MAX7000_TECHNOLOGY_MAPPER
  • MAX7000_USE_CHECKSUM_AS_USERCODE
  • MAX7K_CLIQUE_TYPE
  • MAX_AUTO_GLOBAL_REGISTER_CONTROLS
  • MAX_BALANCING_DSP_BLOCKS
  • MAX_CLOCK_ARRIVAL_SKEW
  • MAX_CLOCKS_ALLOWED
  • MAX_CONSECUTIVE_OUTPUTS_FOR_ELECTROMIGRATION
  • MAX_CONSECUTIVE_VIO_OUTPUTS_FOR_ELECTROMIGRATION
  • MAX_CORE_JUNCTION_TEMP
  • MAX_CORE_SUPPLY_VOLTAGE
  • MAX_CURRENT_FOR_ELECTROMIGRATION
  • MAX_CURRENT_FOR_VIO_ELECTROMIGRATION
  • MAX_DATA_ARRIVAL_SKEW
  • MAX_DELAY_FOR_CORE_PERIPHERY_TRANSFER
  • MAX_DELAY_FOR_PERIPHERY_CORE_TRANSFER
  • MAX_FANOUT
  • MAX_GLOBAL_CLOCKS_ALLOWED
  • MAXII_CARRY_CHAIN_LENGTH
  • MAXII_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
  • MAXII_OPTIMIZATION_TECHNIQUE
  • MAXIMUM
  • MAX_LABS
  • MAX_LARGE_PERIPHERY_CLOCKS_ALLOWED
  • MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS
  • MAX_PERIPHERY_CLOCKS_ALLOWED
  • MAXPLUSII
  • MAX_PROCESSORS_USED_FOR_MULTITHREADING
  • MAX_RAM_BLOCKS_M4K
  • MAX_RAM_BLOCKS_M512
  • MAX_RAM_BLOCKS_MRAM
  • MAX_REGIONAL_CLOCKS_ALLOWED
  • MAX_SCC_SIZE
  • MAX_WIRES_FOR_CORE_PERIPHERY_TRANSFER
  • MAX_WIRES_FOR_PERIPHERY_CORE_TRANSFER
  • MEDIUM
  • MEGAFUNCTION_GENERATED_TRI
  • MEGALAB
  • MEGARAM
  • MEM_INTERFACE_DELAY_CHAIN_CONFIG
  • MEMORY_INTERFACE_DATA_PIN_GROUP
  • MERCURY_CARRY_CHAIN_LENGTH
  • MERCURY_CLIQUE_TYPE
  • MERCURY_CONFIG_DEVICE_JTAG_USER_CODE
  • MERCURY_CONFIGURATION_DEVICE
  • MERCURY_CONFIGURATION_SCHEME
  • MERCURY_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
  • MERCURY_DEVICE_IO_STANDARD
  • MERCURY_FITTER_TYPE
  • MERCURY_JTAG_USER_CODE
  • MERCURY_OPTIMIZATION_TECHNIQUE
  • MERCURY_TECHNOLOGY_MAPPER
  • MERGE_EQUIVALENT_BIDIRS
  • MERGE_EQUIVALENT_INPUTS
  • MERGE_HEX_FILE
  • MERGE_TX_PLL_DRIVEN_BY_REGISTERS_WITH_SAME_CLEAR
  • MESSAGE_DISABLE
  • MESSAGE_ENABLE
  • MESSAGE_SUPPRESSION_RULE_FILE
  • MFCU
  • MID_POWER
  • MIF_FILE
  • MIGRATION_ASSIGNMENT
  • MIGRATION_AUTO_PACKED_REGISTERS
  • MIGRATION_AUTO_PORT_SWAP
  • MIGRATION_CONSTRAIN_CORE_RESOURCES
  • MIGRATION_DIFFERENT_SOURCE_FILE
  • MIGRATION_ONLY
  • MIGRATION_PORT_SWAPPING
  • MIGRATION_RAM_INFORMATION
  • MIGRATION_RAM_PACKING_INFORMATION
  • MIGRATION_REGISTER_PACKING
  • MIN_CORE_JUNCTION_TEMP
  • MIN_CORE_SUPPLY_VOLTAGE
  • MIN_DELAY_FOR_CORE_PERIPHERY_TRANSFER
  • MIN_DELAY_FOR_PERIPHERY_CORE_TRANSFER
  • MINIMAL_BITS
  • MINIMIZE_AREA
  • MINIMIZE_AREA_WITH_CHAINS
  • MINIMIZE_POWER_ONLY
  • MINIMUM_DELAY_REQUIREMENT
  • MINIMUM
  • MINIMUM_TPD_REQUIREMENT
  • MINIMUM_WIDTH_CLOCK_ENABLE
  • MINIMUM_WIDTH_SLOAD_SCLEAR
  • MIN_TCO_REQUIREMENT
  • MIN_TPD_REQUIREMENT
  • MINUS_DELTA10
  • MINUS_DELTA11
  • MINUS_DELTA12
  • MINUS_DELTA13
  • MINUS_DELTA14
  • MINUS_DELTA15
  • MINUS_DELTA1
  • MINUS_DELTA2
  • MINUS_DELTA3
  • MINUS_DELTA4
  • MINUS_DELTA5
  • MINUS_DELTA6
  • MINUS_DELTA7
  • MINUS_DELTA8
  • MINUS_DELTA9
  • MIN_WIRES_FOR_CORE_PERIPHERY_TRANSFER
  • MIN_WIRES_FOR_PERIPHERY_CORE_TRANSFER
  • MISC_FILE
  • MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE
  • MLAB
  • MLAB_TIMING_CONSTRAINTS_IN_FEED_THROUGH_DONT_CARE_MODE
  • MODE_0
  • MODE_10
  • MODE_11
  • MODE_12
  • MODE_13
  • MODE_14
  • MODE_15
  • MODE_1
  • MODE_2
  • MODE_3
  • MODE_4
  • MODE_5
  • MODE_6
  • MODE_7
  • MODE_8
  • MODE_9
  • MODE_DEFAULT
  • MODEL_1
  • MODEL_2
  • MODEL_3
  • MOVE_TO_TOP_IO
  • MP2_EXPORT_FILE
  • MULTIPLY_BASE_CLOCK_BY
  • MULTIPLY_BASE_CLOCK_PERIOD_BY
  • MUX_RESTRUCTURE
  • MUX_USE_ROUTING_ASSIGNMENT
  • NAVAUATI
  • NCEO_OPEN_DRAIN
  • NCEO_RESERVED_CYCLONEII
  • NCEO_RESERVED
  • NDQS_LOCAL_CLOCK_DELAY_CHAIN
  • NEAR_END
  • NEAR_GLOBAL_CLOCK
  • NEAR_REGIONAL_CLOCK
  • NEGATIVE_180
  • NEGATIVE_90
  • NEGATIVE_EDGE
  • NETLIST_ONLY
  • NETLIST_VIEWER_ASSIGNMENT
  • NETO_ASSIGNMENT
  • NEVER_ALLOW
  • NEVER
  • NEVER_REGENERATE_IP
  • NO_AUTO_INST_DISCOVERY
  • NO_BACK_ANNOTATION
  • NO_BYTE_ENABLE
  • NO_COMBINATIONAL_OUTPUT
  • NO_DC_GAIN
  • NO_FILE
  • NO_GLOBAL_ROUTE
  • NOMINAL_CORE_SUPPLY_VOLTAGE
  • NONDEFAULT_LIBS
  • NON_LOCAL
  • NON_QPI_MODE
  • NON_S1_MODE
  • NONSYNCHSTRUCT_CAT
  • NONSYNCHSTRUCT_RULE_ASYN_RAM
  • NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE
  • NONSYNCHSTRUCT_RULE_COMBLOOP
  • NONSYNCHSTRUCT_RULE_DELAY_CHAIN
  • NONSYNCHSTRUCT_RULE_DLATCH
  • NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN
  • NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED
  • NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR
  • NONSYNCHSTRUCT_RULE_REG_LOOP
  • NONSYNCHSTRUCT_RULE_RIPPLE_CLK
  • NONSYNCHSTRUCT_RULE_SRLATCH
  • NORMAL_COMPILATION
  • NORMAL_LCELL_INSERT
  • NORMAL
  • NO_SDC_PROMOTION
  • NOT_A_CLOCK
  • NOT_BOOST
  • NOT_CLOCK
  • NOT_GATE_PUSH_BACK
  • NOT_USED
  • NTFQ_MSG_ACF_ASSIGNMENTS_CHANGED
  • NUMBER_OF_DESTINATION_TO_REPORT
  • NUMBER_OF_INVERTED_REGISTERS_REPORTED
  • NUMBER_OF_PATHS_TO_REPORT
  • NUMBER_OF_PROTECTED_REGISTERS_REPORTED
  • NUMBER_OF_REMOVED_REGISTERS_REPORTED
  • NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT
  • NUMBER_OF_SWEPT_NODES_REPORTED
  • NUMBER_OF_SYNTHESIS_MIGRATION_ROWS
  • NUM_PARALLEL_PROCESSORS
  • NWS_NRS_NCS_CS_RESERVED
  • OBSAI_1536
  • OBSAI_3072
  • OBSAI_6144
  • OBSAI_768
  • OBSERVABLE
  • OCP_AUTO_PARTITION
  • OCP_FILE
  • OCP_PARTITION
  • OCP_TIMEOUT_PARTITION
  • OCT_100_OHMS
  • OCT_120_OHMS
  • OCT_150_OHMS
  • OCT_AND_IMPEDANCE_MATCHING_CYCLONEII
  • OCT_AND_IMPEDANCE_MATCHING
  • OCT_AND_IMPEDANCE_MATCHING_STRATIXII
  • OCT_CONTROL_BLOCK
  • OE_DELAY_CHAIN
  • OE_OPTION
  • OFFSET_FROM_BASE_CLOCK
  • OFFSET_MAIN
  • OFFSET_PO1
  • OFFSET_PRE
  • ON_CHIP_BITSTREAM_DECOMPRESSION
  • ONE_HOT
  • OPTIMISTIC
  • OPTIMIZATION_MODE
  • OPTIMIZATION_TECHNIQUE_APEX20K
  • OPTIMIZATION_TECHNIQUE_ARMSTRONG
  • OPTIMIZATION_TECHNIQUE_CYCLONEII
  • OPTIMIZATION_TECHNIQUE_CYCLONE
  • OPTIMIZATION_TECHNIQUE_DALI
  • OPTIMIZATION_TECHNIQUE_FLEX10K
  • OPTIMIZATION_TECHNIQUE_FLEX6K
  • OPTIMIZATION_TECHNIQUE_MAX7000
  • OPTIMIZATION_TECHNIQUE_TSUNAMI
  • OPTIMIZATION_TECHNIQUE_YEAGER
  • OPTIMIZE_FAST_CORNER_TIMING
  • OPTIMIZE_FOR_METASTABILITY
  • OPTIMIZE_HOLD_TIMING
  • OPTIMIZE_INTERNAL_TIMING
  • OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING
  • OPTIMIZE_IO_TIMING
  • OPTIMIZE_MULTI_CORNER_TIMING
  • OPTIMIZE_POWER_DURING_FITTING
  • OPTIMIZE_POWER_DURING_SYNTHESIS
  • OPTIMIZE_SIGNAL_INTEGRITY
  • OPTIMIZE_SSN
  • OPTIONS_FOR_ENTITIES_ONLY
  • OPTIONS_FOR_INDIVIDUAL_NODES_ONLY
  • OPTIONS_FOR_NODES_AND_ENTITIES
  • ORIGINAL_INTERFACE_PORT_NAME
  • ORIGINAL_QUARTUS_VERSION
  • ORIGINATING_COMPANION_REVISION
  • OSC_CLK_1_100MHZ
  • OSC_CLK_1_125MHZ
  • OSC_CLK_1_25MHZ
  • OTHER_APF_RESERVED
  • OTHER
  • OTP_AUTO_PARTITION
  • OTP_PARTITION
  • OUTPUT_BUFFER_DELAY_CONTROL
  • OUTPUT_BUFFER_DELAY
  • OUTPUT_DELAY_CHAIN
  • OUTPUT_ENABLE_DELAY
  • OUTPUT_ENABLE_GROUP
  • OUTPUT_ENABLE_REGISTER_DUPLICATION
  • OUTPUT_ENABLE_ROUTING
  • OUTPUT_FILE_NAME
  • OUTPUT_IO_TIMING_ENDPOINT
  • OUTPUT_IO_TIMING_FAR_END_VMEAS
  • OUTPUT_IO_TIMING_NEAR_END_VMEAS
  • OUTPUT_MAX_DELAY
  • OUTPUT_MIN_DELAY
  • OUTPUT_OCT_VALUE
  • OUTPUT_PIN_C_FAR
  • OUTPUT_PIN_C_NEAR
  • OUTPUT_PIN_C_PER_LENGTH
  • OUTPUT_PIN_LENGTH
  • OUTPUT_PIN_LOAD
  • OUTPUT_PIN_L_PER_LENGTH
  • OUTPUT_PIN_R_FAR_HIGH
  • OUTPUT_PIN_R_FAR_LOW
  • OUTPUT_PIN_R_FAR_SERIES
  • OUTPUT_PIN_R_NEAR_HIGH
  • OUTPUT_PIN_R_NEAR_LOW
  • OUTPUT_PIN_R_NEAR_SERIES
  • OUTPUT_PIN_V_TERMINATION
  • OUTPUT_TERMINATION
  • OUTPUT_TYPE
  • OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS
  • OXUSA
  • PACKAGE_SKEW_COMPENSATION
  • PACK_ALL_IO_REGISTERS
  • PAD_TO_CORE_DELAY
  • PAD_TO_DDIO_REGISTER_DELAY
  • PAD_TO_INPUT_REGISTER_DELAY
  • PARALLEL_50_OHMS_WITH_CALIBRATION
  • PARAMETER_ARRAY
  • PARAMETER_BOOL
  • PARAMETER_CHAR
  • PARAMETER_ENUM
  • PARAMETER_PHYSICAL
  • PARAMETER_SIGNED_BIN
  • PARAMETER_SIGNED_DEC
  • PARAMETER_SIGNED_FLOAT
  • PARAMETER_SIGNED_HEX
  • PARAMETER_SIGNED_OCT
  • PARAMETER_STRING
  • PARAMETER_UNKNOWN
  • PARAMETER_UNSIGNED_BIN
  • PARAMETER_UNSIGNED_DEC
  • PARAMETER_UNSIGNED_FLOAT
  • PARAMETER_UNSIGNED_HEX
  • PARAMETER_UNSIGNED_OCT
  • PARAMETER_UNSIZED_BIT_LITERAL
  • PARTIAL_RECONFIGURATION_PARTITION
  • PARTIAL_SRAM_OBJECT_FILE
  • PARTITION_ALWAYS_USE_QXP_NETLIST
  • PARTITION_ASD_REGION_ID
  • PARTITION_ASD_REGION
  • PARTITION_BACK_ANNOTATION
  • PARTITION_COLOR
  • PARTITION_COLOUR
  • PARTITION_ENABLE_STRICT_PRESERVATION
  • PARTITION_EXTRACT_HARD_BLOCK_NODES
  • PARTITION_FITTER_PRESERVATION_LEVEL
  • PARTITION_IGNORE_SOURCE_FILE_CHANGES
  • PARTITION_IMPORT_ASSIGNMENTS
  • PARTITION_IMPORT_EXISTING_ASSIGNMENTS
  • PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS
  • PARTITION_IMPORT_FILE
  • PARTITION_IMPORT_NEW_ASSIGNMENTS
  • PARTITION_IMPORT_PIN_ASSIGNMENTS
  • PARTITION_IMPORT_PROMOTE_ASSIGNMENTS
  • PARTITION_LAST_IMPORTED_FILE
  • PARTITION_NETLIST_TYPE
  • PARTITION_ONLY
  • PARTITION_PRESERVE_HIGH_SPEED_TILES
  • PARTITION_SOURCE
  • PARTITION_TYPE
  • PASSIVE_PARALLEL_ASYNCHRONOUS
  • PASSIVE_PARALLEL_SYNCHRONOUS
  • PASSIVE_PARALLEL_X16
  • PASSIVE_PARALLEL_X32
  • PASSIVE_PARALLEL_X8
  • PASSIVE_PROGRAMMING_FILE_NAME
  • PASSIVE_RESISTOR
  • PASSIVE_SERIAL_ASYNCHRONOUS
  • PASSIVE_SERIAL
  • PBIP_FILE
  • PCB_LAYER
  • PCB_LAYERS
  • PCB_LAYER_THICKNESS
  • PCIE_CABLE
  • PCIE_GEN1_3P5DB
  • PCIE_GEN1
  • PCIE_GEN2_3P5DB
  • PCIE_GEN2_6DB
  • PCIE_GEN2
  • PCIE_GEN3
  • PCIE_PRE_EMPH_GEN1
  • PCIE_PRE_EMPH_GEN2_3_5DB_DEEMPH
  • PCIE_PRE_EMPH_GEN2_6DB_DEEMPH
  • PCIE_PRE_EMPH_GEN2_LOW_MARGIN
  • PCIE_PRE_EMPH_GEN2_LOW_SWING
  • PCIE_VOD_GEN1
  • PCIE_VOD_GEN2_3_5DB_DEEMPH
  • PCIE_VOD_GEN2_6DB_DEEMPH
  • PCIE_VOD_GEN2_LOW_MARGIN
  • PCIE_VOD_GEN2_LOW_SWING
  • PCI_IO
  • PDC_FILE
  • PERIPHERAL
  • PERIPHERY_SEED
  • PERIPHERY_TO_CORE_HIPI_LOCKDOWN
  • PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION
  • PERIPH_FITTER_SCRIPT
  • PERIPH_REPORT_SCRIPT
  • PERSONA_FILE
  • PESSIMISTIC
  • PEXP_LENGTH
  • PEXP_LENGTH_MAX7000
  • PHASE_FROM_BASE_CLOCK
  • PHASE_OF_0_DEGREES
  • PHASE_OF_72_DEGREES
  • PHASE_OF_90_DEGREES
  • PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING_DISABLE_DESTINATION_CHECK
  • PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING
  • PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING_REG_REACH
  • PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA
  • PHYSICAL_SYNTHESIS_COMBO_LOGIC
  • PHYSICAL_SYNTHESIS_EFFORT
  • PHYSICAL_SYNTHESIS_EXTRA_EFFORT
  • PHYSICAL_SYNTHESIS_LOG_FILE
  • PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA
  • PHYSICAL_SYNTHESIS_PIPELINE
  • PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION
  • PHYSICAL_SYNTHESIS_REGISTER_RETIMING
  • PIN_CONNECT_FROM_NODE
  • PIN_FILE
  • PIN_PLANNER_DISPLAY_ASSIGNMENT_VALUE_FROM_POSITIVE_PIN_TO_NEGATIVE_PIN
  • PIN_PLANNER_FILE
  • PLACEMENT_AND_ROUTING_AND_HIGH_SPEED_TILE
  • PLACEMENT_AND_ROUTING_AND_HIGH_SPEED_TILES
  • PLACEMENT_AND_ROUTING_AND_TILE
  • PLACEMENT_AND_ROUTING
  • PLACEMENT_EFFORT_MULTIPLIER
  • PLD_TO_STRIPE_INTERRUPTS_EPXA4_10
  • PLL_APLLY_PFD_ISSUE_WORKAROUND
  • PLL_AUTO_RESET
  • PLL_BANDWIDTH_PRESET
  • PLL_C_COUNTER_DELAY_CHAIN
  • PLL_CHANNEL_SPACING
  • PLL_COMPENSATE
  • PLL_COMPENSATION_MODE
  • PLL_DISABLE_COUNTER_SETTINGS_OPTIMIZATION
  • PLL_ENFORCE_USER_PHASE_SHIFT
  • PLL_EXTERNAL_FEEDBACK_BOARD_DELAY
  • PLL_FEEDBACK_CLOCK_SIGNAL
  • PLL_FORCE_OUTPUT_COUNTER_HARDCOPY_REPLAY
  • PLL_FORCE_OUTPUT_COUNTER
  • PLL_IGNORE_MIGRATION_DEVICES
  • PLL_LOCK_10K
  • PLL_LOCK
  • PLL_LVDS_DELAY_CHAIN
  • PLL_OPTIMIZE_PHASE_SHIFT_FOR_TIMING
  • PLL_OUTPUT_CLOCK_FREQUENCY
  • PLL_PFD_CLOCK_FREQUENCY
  • PLL_PHASE_RECONFIG_COUNTER_REMAP_LCELL
  • PLL_PRE_C_COUNTER_DELAY_CHAIN
  • PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL
  • PLL_TYPE
  • PLL_VCO_CLOCK_FREQUENCY
  • PLUS_DELTA10
  • PLUS_DELTA11
  • PLUS_DELTA12
  • PLUS_DELTA13
  • PLUS_DELTA14
  • PLUS_DELTA15
  • PLUS_DELTA1
  • PLUS_DELTA2
  • PLUS_DELTA3
  • PLUS_DELTA4
  • PLUS_DELTA5
  • PLUS_DELTA6
  • PLUS_DELTA7
  • PLUS_DELTA8
  • PLUS_DELTA9
  • PMBUS_MASTER
  • PMBUS_SLAVE
  • POF_VERIFY_PROTECT
  • POR_SCHEME
  • POSITIVE_180
  • POSITIVE_90
  • POSITIVE_EDGE
  • POST_CONFIG
  • POST_FIT_CONNECT_FROM_SLD_NODE_ENTITY_PORT
  • POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT
  • POST_FIT_WITH_ROUTING
  • POST_FLOW_SCRIPT_FILE
  • POST_MAPPING_RESYNTHESIS
  • POST_MODULE_SCRIPT_FILE
  • POST_SYNTH
  • POWER_AUTO_COMPUTE_TJ
  • POWER_BOARD_TEMPERATURE
  • POWER_BOARD_THERMAL_MODEL
  • POWER_DEFAULT_INPUT_IO_TOGGLE_RATE
  • POWER_DEFAULT_TOGGLE_RATE
  • POWER_ESTIMATION_ASSIGNMENT
  • POWER_ESTIMATION_END_TIME
  • POWER_ESTIMATION_START_TIME
  • POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR
  • POWER_GLITCH_FACTOR
  • POWER_HPS_DYNAMIC_POWER_DUAL
  • POWER_HPS_DYNAMIC_POWER_SINGLE
  • POWER_HPS_ENABLE
  • POWER_HPS_JUNCTION_TEMPERATURE
  • POWER_HPS_PROC_FREQ
  • POWER_HPS_STATIC_POWER
  • POWER_HPS_TOTAL_POWER
  • POWER_HSSI_LEFT
  • POWER_HSSI
  • POWER_HSSI_RIGHT
  • POWER_HSSI_VCCHIP_LEFT
  • POWER_HSSI_VCCHIP_RIGHT
  • POWER_INPUT_FILE_NAME
  • POWER_INPUT_FILE_SETTINGS
  • POWER_INPUT_FILE_TYPE
  • POWER_INPUT_SAF_NAME
  • POWER_INPUT_VCD_FILE_NAME
  • POWER_OCS_VALUE
  • POWER_OJB_VALUE
  • POWER_OJC_VALUE
  • POWER_OSA_VALUE
  • POWER_OUTPUT_SAF_NAME
  • POWER_PRESET_COOLING_SOLUTION
  • POWER_READ_INPUT_FILE
  • POWER_REPORT_POWER_DISSIPATION
  • POWER_REPORT_SIGNAL_ACTIVITY
  • POWER_SIGNAL_ACTIVITY_END_TIME
  • POWER_SIGNAL_ACTIVITY_START_TIME
  • POWER_STATIC_PROBABILITY
  • POWER_STATIC_TOGGLE_RATE
  • POWER_TJ_VALUE
  • POWER_TOGGLE_RATE
  • POWER_TOGGLE_RATE_PERCENTAGE
  • POWER_UP_HIGH
  • POWER_UP_LEVEL
  • POWER_USE_CUSTOM_COOLING_SOLUTION
  • POWER_USE_DEVICE_CHARACTERISTICS
  • POWER_USE_INPUT_FILE
  • POWER_USE_INPUT_FILES
  • POWER_USE_PVA
  • POWER_USE_TA_VALUE
  • POWER_USE_VOLTAGE
  • POWER_VCCA_FPLL_USER_VOLTAGE
  • POWER_VCCA_GTBR_USER_VOLTAGE
  • POWER_VCCA_GTB_USER_VOLTAGE
  • POWER_VCCA_GXBL_USER_OPTION
  • POWER_VCCA_GXBL_USER_VOLTAGE
  • POWER_VCCA_GXBR_USER_OPTION
  • POWER_VCCA_GXBR_USER_VOLTAGE
  • POWER_VCCA_GXB_USER_OPTION
  • POWER_VCCA_GXB_USER_VOLTAGE
  • POWER_VCCA_L_USER_OPTION
  • POWER_VCCA_L_USER_VOLTAGE
  • POWER_VCCA_PLL_USER_VOLTAGE
  • POWER_VCCA_R_USER_OPTION
  • POWER_VCCA_R_USER_VOLTAGE
  • POWER_VCCA_USER_VOLTAGE
  • POWER_VCCAUX_SHARED_USER_VOLTAGE
  • POWER_VCCAUX_USER_OPTION
  • POWER_VCCAUX_USER_VOLTAGE
  • POWER_VCCBAT_USER_VOLTAGE
  • POWER_VCCCB_USER_OPTION
  • POWER_VCCCB_USER_VOLTAGE
  • POWER_VCCD_FPLL_USER_VOLTAGE
  • POWER_VCCD_PLL_USER_VOLTAGE
  • POWER_VCCD_USER_VOLTAGE
  • POWER_VCCE_GXBL_USER_VOLTAGE
  • POWER_VCCE_GXBR_USER_VOLTAGE
  • POWER_VCCE_GXB_USER_VOLTAGE
  • POWER_VCCEH_GXBL_USER_VOLTAGE
  • POWER_VCCEH_GXBR_USER_VOLTAGE
  • POWER_VCCEH_GXB_USER_VOLTAGE
  • POWER_VCCERAM_USER_VOLTAGE
  • POWER_VCCE_USER_VOLTAGE
  • POWER_VCCH_GTBR_USER_VOLTAGE
  • POWER_VCCH_GTB_USER_VOLTAGE
  • POWER_VCCH_GXBL_USER_OPTION
  • POWER_VCCH_GXBL_USER_VOLTAGE
  • POWER_VCCH_GXBR_USER_OPTION
  • POWER_VCCH_GXBR_USER_VOLTAGE
  • POWER_VCCH_GXB_USER_OPTION
  • POWER_VCCH_GXB_USER_VOLTAGE
  • POWER_VCCHIP_L_USER_VOLTAGE
  • POWER_VCCHIP_R_USER_VOLTAGE
  • POWER_VCCHIP_USER_VOLTAGE
  • POWER_VCCH_L_USER_VOLTAGE
  • POWER_VCC_HPS_USER_VOLTAGE
  • POWER_VCCH_R_USER_VOLTAGE
  • POWER_VCCHSSI_L_USER_VOLTAGE
  • POWER_VCCHSSI_R_USER_VOLTAGE
  • POWER_VCCINT_USER_VOLTAGE
  • POWER_VCCIO_HPS_USER_VOLTAGE
  • POWER_VCCIOREF_HPS_USER_VOLTAGE
  • POWER_VCCIO_USER_OPTION
  • POWER_VCCIO_USER_VOLTAGE
  • POWER_VCCL_GTBL_USER_VOLTAGE
  • POWER_VCCL_GTBR_USER_VOLTAGE
  • POWER_VCCL_GTB_USER_VOLTAGE
  • POWER_VCCL_GXBL_USER_VOLTAGE
  • POWER_VCCL_GXBR_USER_VOLTAGE
  • POWER_VCCL_GXB_USER_OPTION
  • POWER_VCCL_GXB_USER_VOLTAGE
  • POWER_VCCL_HPS_USER_VOLTAGE
  • POWER_VCCL_USER_VOLTAGE
  • POWER_VCCPD_USER_OPTION
  • POWER_VCCPD_USER_VOLTAGE
  • POWER_VCCPGM_USER_VOLTAGE
  • POWER_VCCPLL_HPS_USER_VOLTAGE
  • POWER_VCCPT_USER_VOLTAGE
  • POWER_VCCP_USER_VOLTAGE
  • POWER_VCCR_GTBL_USER_VOLTAGE
  • POWER_VCCR_GTBR_USER_VOLTAGE
  • POWER_VCCR_GTB_USER_VOLTAGE
  • POWER_VCCR_GXBL_USER_OPTION
  • POWER_VCCR_GXBL_USER_VOLTAGE
  • POWER_VCCR_GXBR_USER_OPTION
  • POWER_VCCR_GXBR_USER_VOLTAGE
  • POWER_VCCR_GXB_USER_OPTION
  • POWER_VCCR_GXB_USER_VOLTAGE
  • POWER_VCCR_L_USER_VOLTAGE
  • POWER_VCCR_R_USER_VOLTAGE
  • POWER_VCCRSTCLK_HPS_USER_VOLTAGE
  • POWER_VCCR_USER_VOLTAGE
  • POWER_VCCT_GTBL_USER_VOLTAGE
  • POWER_VCCT_GTBR_USER_VOLTAGE
  • POWER_VCCT_GTB_USER_VOLTAGE
  • POWER_VCCT_GXBL_USER_OPTION
  • POWER_VCCT_GXBL_USER_VOLTAGE
  • POWER_VCCT_GXBR_USER_OPTION
  • POWER_VCCT_GXBR_USER_VOLTAGE
  • POWER_VCCT_GXB_USER_OPTION
  • POWER_VCCT_GXB_USER_VOLTAGE
  • POWER_VCCT_L_USER_VOLTAGE
  • POWER_VCCT_R_USER_VOLTAGE
  • POWER_VCCT_USER_VOLTAGE
  • POWER_VCC_USER_VOLTAGE
  • POWER_VCD_FILE_END_TIME
  • POWER_VCD_FILE_START_TIME
  • POWER_VCD_FILTER_GLITCHES
  • POWER_WILDCARDS
  • PPF_FILE
  • PR_ALLOW_GLOBAL_LIMS
  • PR_BASE
  • PR_BASE_MSF
  • PR_BASE_SOF
  • PR_DONE_OPEN_DRAIN
  • PRE_CONFIG
  • PRE_FLOW_SCRIPT_FILE
  • PRE_MAPPING_RESYNTHESIS
  • PR_ERROR_OPEN_DRAIN
  • PRESERVE_FANOUT_FREE_NODE
  • PRESERVE_HIERARCHICAL_BOUNDARY
  • PRESERVE
  • PRESERVE_PLL_COUNTER_ORDER
  • PRESERVE_PORT_NAME
  • PRESERVE_REGISTER
  • PRESERVE_SYNONYMS
  • PRESERVE_UNUSED_XCVR_CHANNEL
  • PR_IMPL
  • PRINT_DEBUG_MSG_AND_EXIT
  • PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10
  • PRODUCT_TERM
  • PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES
  • PROGRAMMABLE_POWER_TECHNOLOGY_SETTING
  • PROGRAMMABLE_PREEMPHASIS
  • PROGRAMMABLE_VOD
  • PROGRAMMER_ASSIGNMENT
  • PROGRAMMER_OBJECT_FILE
  • PROGRAMMING_FILE_TYPE
  • PROGRAMMING_MODE_APEX20KF
  • PROGRAMMING_MODE_APEX20K
  • PROGRAMMING_MODE_ARMSTRONG
  • PROGRAMMING_MODE_CUDA
  • PROGRAMMING_MODE_CYCLONEII
  • PROGRAMMING_MODE_DALI
  • PROGRAMMING_MODE_EXCALIBUR
  • PROGRAMMING_MODE_FLEX10K
  • PROGRAMMING_MODE_FLEX6K
  • PROGRAMMING_MODE
  • PROGRAMMING_MODE_TITAN
  • PROGRAMMING_MODE_TORNADO
  • PROGRAMMING_MODE_YEAGER
  • PROGRAMMING_MODE_ZIPPLEBACK
  • PROJECT_ASSIGNMENT
  • PROJECT_CREATION_TIME_DATE
  • PROJECT_INFO
  • PROJECT_IP_REGENERATION_POLICY
  • PROJECT_IP_SEARCH_PATHS
  • PROJECT_MIGRATION_TIMESTAMP
  • PROJECT_OUTPUT_DIRECTORY
  • PROJECT_SHOW_ENTITY_NAME
  • PROJECT_SOURCE_FILE
  • PROJECT_THUNDER_BAY
  • PROJECT_USE_SIMPLIFIED_NAMES
  • PRO_ONLY
  • PROPAGATE_CONSTANTS_ON_INPUTS
  • PROPAGATE_INVERSIONS_ON_INPUTS
  • PR_PARTITION
  • PR_PINS_OPEN_DRAIN
  • PRPOF_ID
  • PR_READY_OPEN_DRAIN
  • PR_SKIP_BASE_CHECK
  • PR_SYN
  • PULL_DN
  • PULLDOWN_DRIVE_STRENGTH_BITS
  • PULL_DOWN
  • PULL_RESISTOR
  • PULLUP_DRIVE_STRENGTH_BITS
  • PULL_UP_TO_VCCELA
  • PULSE_WIDTH_0
  • PULSE_WIDTH_1
  • PULSE_WIDTH_2_LARGE
  • PULSE_WIDTH_2
  • PULSE_WIDTH_NONE
  • PV3102_OR_EM1130
  • PWRMGT_DIRECT_FORMAT_COEFFICIENT_B
  • PWRMGT_DIRECT_FORMAT_COEFFICIENT_M
  • PWRMGT_DIRECT_FORMAT_COEFFICIENT_R
  • PWRMGT_SLAVE_DEVICE0_ADDRESS
  • PWRMGT_SLAVE_DEVICE1_ADDRESS
  • PWRMGT_SLAVE_DEVICE2_ADDRESS
  • PWRMGT_SLAVE_DEVICE3_ADDRESS
  • PWRMGT_SLAVE_DEVICE4_ADDRESS
  • PWRMGT_SLAVE_DEVICE5_ADDRESS
  • PWRMGT_SLAVE_DEVICE6_ADDRESS
  • PWRMGT_SLAVE_DEVICE7_ADDRESS
  • PWRMGT_SLAVE_DEVICE_TYPE
  • PWRMGT_VOLTAGE_OUTPUT_FORMAT
  • QAR_FILE
  • QARLOG_FILE
  • QDB_FILE
  • QDB_PATH
  • QDFS_USE_CHERRY
  • QDR_D_PIN_GROUP
  • QHD_MODE
  • QIC_EXPORT_FILE
  • QIC_EXPORT_FLATTEN
  • QIC_EXPORT_NETLIST_TYPE
  • QIC_EXPORT_PARTITION_NAME
  • QIC_EXPORT_ROUTING
  • QIC_USE_BINARY_DATABASES
  • QID_ASSIGNMENT
  • QII_AUTO_PACKED_REGISTERS
  • QIP_FILE
  • QPRD
  • QSGMII_5000
  • QSYS_FILE
  • QUARTUS_ACF_FILE
  • QUARTUS_COMPILER_SETTINGS_FILE
  • QUARTUS_ENTITY_SETTINGS_FILE
  • QUARTUS_GUI_SIGNATURE_ID
  • QUARTUSII
  • QUARTUS_PROJECT_FILE
  • QUARTUS_PROJECT_SETTINGS_FILE
  • QUARTUS_PTF_FILE
  • QUARTUS_SBD_FILE
  • QUARTUS_SIMULATOR_SETTINGS_FILE
  • QUARTUS_SOFTWARE_SETTINGS_FILE
  • QUARTUS_STANDARD_DELAY_FILE
  • QUARTUS_WORKSPACE_FILE
  • QVAR_FILE
  • QXP_FILE
  • R08S
  • R_ADAPT_DFE_CONTROL_SEL_0
  • R_ADAPT_DFE_CONTROL_SEL_1
  • R_ADAPT_DFE_CONTROL_SEL_2
  • R_ADAPT_DFE_CONTROL_SEL_3
  • R_ADAPT_DFE_SEL_0
  • R_ADAPT_DFE_SEL_1
  • R_ADAPT_VGA_SEL_0
  • R_ADAPT_VGA_SEL_1
  • R_ADAPT_VREF_SEL_0
  • R_ADAPT_VREF_SEL_1
  • R_ADAPT_VREF_SEL_2
  • R_ADAPT_VREF_SEL_3
  • RADP_CTLE_ACGAIN_4S_0
  • RADP_CTLE_ACGAIN_4S_10
  • RADP_CTLE_ACGAIN_4S_11
  • RADP_CTLE_ACGAIN_4S_12
  • RADP_CTLE_ACGAIN_4S_13
  • RADP_CTLE_ACGAIN_4S_14
  • RADP_CTLE_ACGAIN_4S_15
  • RADP_CTLE_ACGAIN_4S_16
  • RADP_CTLE_ACGAIN_4S_17
  • RADP_CTLE_ACGAIN_4S_18
  • RADP_CTLE_ACGAIN_4S_19
  • RADP_CTLE_ACGAIN_4S_1
  • RADP_CTLE_ACGAIN_4S_20
  • RADP_CTLE_ACGAIN_4S_21
  • RADP_CTLE_ACGAIN_4S_22
  • RADP_CTLE_ACGAIN_4S_23
  • RADP_CTLE_ACGAIN_4S_24
  • RADP_CTLE_ACGAIN_4S_25
  • RADP_CTLE_ACGAIN_4S_26
  • RADP_CTLE_ACGAIN_4S_27
  • RADP_CTLE_ACGAIN_4S_28
  • RADP_CTLE_ACGAIN_4S_2
  • RADP_CTLE_ACGAIN_4S_3
  • RADP_CTLE_ACGAIN_4S_4
  • RADP_CTLE_ACGAIN_4S_5
  • RADP_CTLE_ACGAIN_4S_6
  • RADP_CTLE_ACGAIN_4S_7
  • RADP_CTLE_ACGAIN_4S_8
  • RADP_CTLE_ACGAIN_4S_9
  • RADP_CTLE_EQZ_1S_SEL_0
  • RADP_CTLE_EQZ_1S_SEL_10
  • RADP_CTLE_EQZ_1S_SEL_11
  • RADP_CTLE_EQZ_1S_SEL_12
  • RADP_CTLE_EQZ_1S_SEL_13
  • RADP_CTLE_EQZ_1S_SEL_14
  • RADP_CTLE_EQZ_1S_SEL_15
  • RADP_CTLE_EQZ_1S_SEL_1
  • RADP_CTLE_EQZ_1S_SEL_2
  • RADP_CTLE_EQZ_1S_SEL_3
  • RADP_CTLE_EQZ_1S_SEL_4
  • RADP_CTLE_EQZ_1S_SEL_5
  • RADP_CTLE_EQZ_1S_SEL_6
  • RADP_CTLE_EQZ_1S_SEL_7
  • RADP_CTLE_EQZ_1S_SEL_8
  • RADP_CTLE_EQZ_1S_SEL_9
  • RADP_DFE_FLTAP_POSITION_0
  • RADP_DFE_FLTAP_POSITION_10
  • RADP_DFE_FLTAP_POSITION_11
  • RADP_DFE_FLTAP_POSITION_12
  • RADP_DFE_FLTAP_POSITION_13
  • RADP_DFE_FLTAP_POSITION_14
  • RADP_DFE_FLTAP_POSITION_15
  • RADP_DFE_FLTAP_POSITION_16
  • RADP_DFE_FLTAP_POSITION_17
  • RADP_DFE_FLTAP_POSITION_18
  • RADP_DFE_FLTAP_POSITION_19
  • RADP_DFE_FLTAP_POSITION_1
  • RADP_DFE_FLTAP_POSITION_20
  • RADP_DFE_FLTAP_POSITION_21
  • RADP_DFE_FLTAP_POSITION_22
  • RADP_DFE_FLTAP_POSITION_23
  • RADP_DFE_FLTAP_POSITION_24
  • RADP_DFE_FLTAP_POSITION_25
  • RADP_DFE_FLTAP_POSITION_26
  • RADP_DFE_FLTAP_POSITION_27
  • RADP_DFE_FLTAP_POSITION_28
  • RADP_DFE_FLTAP_POSITION_29
  • RADP_DFE_FLTAP_POSITION_2
  • RADP_DFE_FLTAP_POSITION_30
  • RADP_DFE_FLTAP_POSITION_31
  • RADP_DFE_FLTAP_POSITION_32
  • RADP_DFE_FLTAP_POSITION_33
  • RADP_DFE_FLTAP_POSITION_34
  • RADP_DFE_FLTAP_POSITION_35
  • RADP_DFE_FLTAP_POSITION_36
  • RADP_DFE_FLTAP_POSITION_37
  • RADP_DFE_FLTAP_POSITION_38
  • RADP_DFE_FLTAP_POSITION_39
  • RADP_DFE_FLTAP_POSITION_3
  • RADP_DFE_FLTAP_POSITION_40
  • RADP_DFE_FLTAP_POSITION_41
  • RADP_DFE_FLTAP_POSITION_42
  • RADP_DFE_FLTAP_POSITION_43
  • RADP_DFE_FLTAP_POSITION_44
  • RADP_DFE_FLTAP_POSITION_45
  • RADP_DFE_FLTAP_POSITION_46
  • RADP_DFE_FLTAP_POSITION_47
  • RADP_DFE_FLTAP_POSITION_48
  • RADP_DFE_FLTAP_POSITION_49
  • RADP_DFE_FLTAP_POSITION_4
  • RADP_DFE_FLTAP_POSITION_50
  • RADP_DFE_FLTAP_POSITION_51
  • RADP_DFE_FLTAP_POSITION_52
  • RADP_DFE_FLTAP_POSITION_53
  • RADP_DFE_FLTAP_POSITION_54
  • RADP_DFE_FLTAP_POSITION_55
  • RADP_DFE_FLTAP_POSITION_5
  • RADP_DFE_FLTAP_POSITION_6
  • RADP_DFE_FLTAP_POSITION_7
  • RADP_DFE_FLTAP_POSITION_8
  • RADP_DFE_FLTAP_POSITION_9
  • RADP_DFE_FXTAP10_0
  • RADP_DFE_FXTAP10_10
  • RADP_DFE_FXTAP10_11
  • RADP_DFE_FXTAP10_12
  • RADP_DFE_FXTAP10_13
  • RADP_DFE_FXTAP10_14
  • RADP_DFE_FXTAP10_15
  • RADP_DFE_FXTAP10_16
  • RADP_DFE_FXTAP10_17
  • RADP_DFE_FXTAP10_18
  • RADP_DFE_FXTAP10_19
  • RADP_DFE_FXTAP10_1
  • RADP_DFE_FXTAP10_20
  • RADP_DFE_FXTAP10_21
  • RADP_DFE_FXTAP10_22
  • RADP_DFE_FXTAP10_23
  • RADP_DFE_FXTAP10_24
  • RADP_DFE_FXTAP10_25
  • RADP_DFE_FXTAP10_26
  • RADP_DFE_FXTAP10_27
  • RADP_DFE_FXTAP10_28
  • RADP_DFE_FXTAP10_29
  • RADP_DFE_FXTAP10_2
  • RADP_DFE_FXTAP10_30
  • RADP_DFE_FXTAP10_31
  • RADP_DFE_FXTAP10_32
  • RADP_DFE_FXTAP10_33
  • RADP_DFE_FXTAP10_34
  • RADP_DFE_FXTAP10_35
  • RADP_DFE_FXTAP10_36
  • RADP_DFE_FXTAP10_37
  • RADP_DFE_FXTAP10_38
  • RADP_DFE_FXTAP10_39
  • RADP_DFE_FXTAP10_3
  • RADP_DFE_FXTAP10_40
  • RADP_DFE_FXTAP10_41
  • RADP_DFE_FXTAP10_42
  • RADP_DFE_FXTAP10_43
  • RADP_DFE_FXTAP10_44
  • RADP_DFE_FXTAP10_45
  • RADP_DFE_FXTAP10_46
  • RADP_DFE_FXTAP10_47
  • RADP_DFE_FXTAP10_48
  • RADP_DFE_FXTAP10_49
  • RADP_DFE_FXTAP10_4
  • RADP_DFE_FXTAP10_50
  • RADP_DFE_FXTAP10_51
  • RADP_DFE_FXTAP10_52
  • RADP_DFE_FXTAP10_53
  • RADP_DFE_FXTAP10_54
  • RADP_DFE_FXTAP10_55
  • RADP_DFE_FXTAP10_56
  • RADP_DFE_FXTAP10_57
  • RADP_DFE_FXTAP10_58
  • RADP_DFE_FXTAP10_59
  • RADP_DFE_FXTAP10_5
  • RADP_DFE_FXTAP10_60
  • RADP_DFE_FXTAP10_61
  • RADP_DFE_FXTAP10_62
  • RADP_DFE_FXTAP10_63
  • RADP_DFE_FXTAP10_6
  • RADP_DFE_FXTAP10_7
  • RADP_DFE_FXTAP10_8
  • RADP_DFE_FXTAP10_9
  • RADP_DFE_FXTAP1_0
  • RADP_DFE_FXTAP10_SGN_0
  • RADP_DFE_FXTAP10_SGN_1
  • RADP_DFE_FXTAP1_100
  • RADP_DFE_FXTAP1_101
  • RADP_DFE_FXTAP1_102
  • RADP_DFE_FXTAP1_103
  • RADP_DFE_FXTAP1_104
  • RADP_DFE_FXTAP1_105
  • RADP_DFE_FXTAP1_106
  • RADP_DFE_FXTAP1_107
  • RADP_DFE_FXTAP1_108
  • RADP_DFE_FXTAP1_109
  • RADP_DFE_FXTAP1_10
  • RADP_DFE_FXTAP11_0
  • RADP_DFE_FXTAP1_110
  • RADP_DFE_FXTAP11_10
  • RADP_DFE_FXTAP1_111
  • RADP_DFE_FXTAP11_11
  • RADP_DFE_FXTAP1_112
  • RADP_DFE_FXTAP11_12
  • RADP_DFE_FXTAP1_113
  • RADP_DFE_FXTAP11_13
  • RADP_DFE_FXTAP1_114
  • RADP_DFE_FXTAP11_14
  • RADP_DFE_FXTAP1_115
  • RADP_DFE_FXTAP11_15
  • RADP_DFE_FXTAP1_116
  • RADP_DFE_FXTAP11_16
  • RADP_DFE_FXTAP1_117
  • RADP_DFE_FXTAP11_17
  • RADP_DFE_FXTAP1_118
  • RADP_DFE_FXTAP11_18
  • RADP_DFE_FXTAP1_119
  • RADP_DFE_FXTAP11_19
  • RADP_DFE_FXTAP1_11
  • RADP_DFE_FXTAP11_1
  • RADP_DFE_FXTAP1_120
  • RADP_DFE_FXTAP11_20
  • RADP_DFE_FXTAP1_121
  • RADP_DFE_FXTAP11_21
  • RADP_DFE_FXTAP1_122
  • RADP_DFE_FXTAP11_22
  • RADP_DFE_FXTAP1_123
  • RADP_DFE_FXTAP11_23
  • RADP_DFE_FXTAP1_124
  • RADP_DFE_FXTAP11_24
  • RADP_DFE_FXTAP1_125
  • RADP_DFE_FXTAP11_25
  • RADP_DFE_FXTAP1_126
  • RADP_DFE_FXTAP11_26
  • RADP_DFE_FXTAP1_127
  • RADP_DFE_FXTAP11_27
  • RADP_DFE_FXTAP11_28
  • RADP_DFE_FXTAP11_29
  • RADP_DFE_FXTAP1_12
  • RADP_DFE_FXTAP11_2
  • RADP_DFE_FXTAP11_30
  • RADP_DFE_FXTAP11_31
  • RADP_DFE_FXTAP11_32
  • RADP_DFE_FXTAP11_33
  • RADP_DFE_FXTAP11_34
  • RADP_DFE_FXTAP11_35
  • RADP_DFE_FXTAP11_36
  • RADP_DFE_FXTAP11_37
  • RADP_DFE_FXTAP11_38
  • RADP_DFE_FXTAP11_39
  • RADP_DFE_FXTAP1_13
  • RADP_DFE_FXTAP11_3
  • RADP_DFE_FXTAP11_40
  • RADP_DFE_FXTAP11_41
  • RADP_DFE_FXTAP11_42
  • RADP_DFE_FXTAP11_43
  • RADP_DFE_FXTAP11_44
  • RADP_DFE_FXTAP11_45
  • RADP_DFE_FXTAP11_46
  • RADP_DFE_FXTAP11_47
  • RADP_DFE_FXTAP11_48
  • RADP_DFE_FXTAP11_49
  • RADP_DFE_FXTAP1_14
  • RADP_DFE_FXTAP11_4
  • RADP_DFE_FXTAP11_50
  • RADP_DFE_FXTAP11_51
  • RADP_DFE_FXTAP11_52
  • RADP_DFE_FXTAP11_53
  • RADP_DFE_FXTAP11_54
  • RADP_DFE_FXTAP11_55
  • RADP_DFE_FXTAP11_56
  • RADP_DFE_FXTAP11_57
  • RADP_DFE_FXTAP11_58
  • RADP_DFE_FXTAP11_59
  • RADP_DFE_FXTAP1_15
  • RADP_DFE_FXTAP11_5
  • RADP_DFE_FXTAP11_60
  • RADP_DFE_FXTAP11_61
  • RADP_DFE_FXTAP11_62
  • RADP_DFE_FXTAP11_63
  • RADP_DFE_FXTAP1_16
  • RADP_DFE_FXTAP11_6
  • RADP_DFE_FXTAP1_17
  • RADP_DFE_FXTAP11_7
  • RADP_DFE_FXTAP1_18
  • RADP_DFE_FXTAP11_8
  • RADP_DFE_FXTAP1_19
  • RADP_DFE_FXTAP11_9
  • RADP_DFE_FXTAP1_1
  • RADP_DFE_FXTAP11_SGN_0
  • RADP_DFE_FXTAP11_SGN_1
  • RADP_DFE_FXTAP1_20
  • RADP_DFE_FXTAP1_21
  • RADP_DFE_FXTAP1_22
  • RADP_DFE_FXTAP1_23
  • RADP_DFE_FXTAP1_24
  • RADP_DFE_FXTAP1_25
  • RADP_DFE_FXTAP1_26
  • RADP_DFE_FXTAP1_27
  • RADP_DFE_FXTAP1_28
  • RADP_DFE_FXTAP1_29
  • RADP_DFE_FXTAP1_2
  • RADP_DFE_FXTAP1_30
  • RADP_DFE_FXTAP1_31
  • RADP_DFE_FXTAP1_32
  • RADP_DFE_FXTAP1_33
  • RADP_DFE_FXTAP1_34
  • RADP_DFE_FXTAP1_35
  • RADP_DFE_FXTAP1_36
  • RADP_DFE_FXTAP1_37
  • RADP_DFE_FXTAP1_38
  • RADP_DFE_FXTAP1_39
  • RADP_DFE_FXTAP1_3
  • RADP_DFE_FXTAP1_40
  • RADP_DFE_FXTAP1_41
  • RADP_DFE_FXTAP1_42
  • RADP_DFE_FXTAP1_43
  • RADP_DFE_FXTAP1_44
  • RADP_DFE_FXTAP1_45
  • RADP_DFE_FXTAP1_46
  • RADP_DFE_FXTAP1_47
  • RADP_DFE_FXTAP1_48
  • RADP_DFE_FXTAP1_49
  • RADP_DFE_FXTAP1_4
  • RADP_DFE_FXTAP1_50
  • RADP_DFE_FXTAP1_51
  • RADP_DFE_FXTAP1_52
  • RADP_DFE_FXTAP1_53
  • RADP_DFE_FXTAP1_54
  • RADP_DFE_FXTAP1_55
  • RADP_DFE_FXTAP1_56
  • RADP_DFE_FXTAP1_57
  • RADP_DFE_FXTAP1_58
  • RADP_DFE_FXTAP1_59
  • RADP_DFE_FXTAP1_5
  • RADP_DFE_FXTAP1_60
  • RADP_DFE_FXTAP1_61
  • RADP_DFE_FXTAP1_62
  • RADP_DFE_FXTAP1_63
  • RADP_DFE_FXTAP1_64
  • RADP_DFE_FXTAP1_65
  • RADP_DFE_FXTAP1_66
  • RADP_DFE_FXTAP1_67
  • RADP_DFE_FXTAP1_68
  • RADP_DFE_FXTAP1_69
  • RADP_DFE_FXTAP1_6
  • RADP_DFE_FXTAP1_70
  • RADP_DFE_FXTAP1_71
  • RADP_DFE_FXTAP1_72
  • RADP_DFE_FXTAP1_73
  • RADP_DFE_FXTAP1_74
  • RADP_DFE_FXTAP1_75
  • RADP_DFE_FXTAP1_76
  • RADP_DFE_FXTAP1_77
  • RADP_DFE_FXTAP1_78
  • RADP_DFE_FXTAP1_79
  • RADP_DFE_FXTAP1_7
  • RADP_DFE_FXTAP1_80
  • RADP_DFE_FXTAP1_81
  • RADP_DFE_FXTAP1_82
  • RADP_DFE_FXTAP1_83
  • RADP_DFE_FXTAP1_84
  • RADP_DFE_FXTAP1_85
  • RADP_DFE_FXTAP1_86
  • RADP_DFE_FXTAP1_87
  • RADP_DFE_FXTAP1_88
  • RADP_DFE_FXTAP1_89
  • RADP_DFE_FXTAP1_8
  • RADP_DFE_FXTAP1_90
  • RADP_DFE_FXTAP1_91
  • RADP_DFE_FXTAP1_92
  • RADP_DFE_FXTAP1_93
  • RADP_DFE_FXTAP1_94
  • RADP_DFE_FXTAP1_95
  • RADP_DFE_FXTAP1_96
  • RADP_DFE_FXTAP1_97
  • RADP_DFE_FXTAP1_98
  • RADP_DFE_FXTAP1_99
  • RADP_DFE_FXTAP1_9
  • RADP_DFE_FXTAP2_0
  • RADP_DFE_FXTAP2_100
  • RADP_DFE_FXTAP2_101
  • RADP_DFE_FXTAP2_102
  • RADP_DFE_FXTAP2_103
  • RADP_DFE_FXTAP2_104
  • RADP_DFE_FXTAP2_105
  • RADP_DFE_FXTAP2_106
  • RADP_DFE_FXTAP2_107
  • RADP_DFE_FXTAP2_108
  • RADP_DFE_FXTAP2_109
  • RADP_DFE_FXTAP2_10
  • RADP_DFE_FXTAP2_110
  • RADP_DFE_FXTAP2_111
  • RADP_DFE_FXTAP2_112
  • RADP_DFE_FXTAP2_113
  • RADP_DFE_FXTAP2_114
  • RADP_DFE_FXTAP2_115
  • RADP_DFE_FXTAP2_116
  • RADP_DFE_FXTAP2_117
  • RADP_DFE_FXTAP2_118
  • RADP_DFE_FXTAP2_119
  • RADP_DFE_FXTAP2_11
  • RADP_DFE_FXTAP2_120
  • RADP_DFE_FXTAP2_121
  • RADP_DFE_FXTAP2_122
  • RADP_DFE_FXTAP2_123
  • RADP_DFE_FXTAP2_124
  • RADP_DFE_FXTAP2_125
  • RADP_DFE_FXTAP2_126
  • RADP_DFE_FXTAP2_127
  • RADP_DFE_FXTAP2_12
  • RADP_DFE_FXTAP2_13
  • RADP_DFE_FXTAP2_14
  • RADP_DFE_FXTAP2_15
  • RADP_DFE_FXTAP2_16
  • RADP_DFE_FXTAP2_17
  • RADP_DFE_FXTAP2_18
  • RADP_DFE_FXTAP2_19
  • RADP_DFE_FXTAP2_1
  • RADP_DFE_FXTAP2_20
  • RADP_DFE_FXTAP2_21
  • RADP_DFE_FXTAP2_22
  • RADP_DFE_FXTAP2_23
  • RADP_DFE_FXTAP2_24
  • RADP_DFE_FXTAP2_25
  • RADP_DFE_FXTAP2_26
  • RADP_DFE_FXTAP2_27
  • RADP_DFE_FXTAP2_28
  • RADP_DFE_FXTAP2_29
  • RADP_DFE_FXTAP2_2
  • RADP_DFE_FXTAP2_30
  • RADP_DFE_FXTAP2_31
  • RADP_DFE_FXTAP2_32
  • RADP_DFE_FXTAP2_33
  • RADP_DFE_FXTAP2_34
  • RADP_DFE_FXTAP2_35
  • RADP_DFE_FXTAP2_36
  • RADP_DFE_FXTAP2_37
  • RADP_DFE_FXTAP2_38
  • RADP_DFE_FXTAP2_39
  • RADP_DFE_FXTAP2_3
  • RADP_DFE_FXTAP2_40
  • RADP_DFE_FXTAP2_41
  • RADP_DFE_FXTAP2_42
  • RADP_DFE_FXTAP2_43
  • RADP_DFE_FXTAP2_44
  • RADP_DFE_FXTAP2_45
  • RADP_DFE_FXTAP2_46
  • RADP_DFE_FXTAP2_47
  • RADP_DFE_FXTAP2_48
  • RADP_DFE_FXTAP2_49
  • RADP_DFE_FXTAP2_4
  • RADP_DFE_FXTAP2_50
  • RADP_DFE_FXTAP2_51
  • RADP_DFE_FXTAP2_52
  • RADP_DFE_FXTAP2_53
  • RADP_DFE_FXTAP2_54
  • RADP_DFE_FXTAP2_55
  • RADP_DFE_FXTAP2_56
  • RADP_DFE_FXTAP2_57
  • RADP_DFE_FXTAP2_58
  • RADP_DFE_FXTAP2_59
  • RADP_DFE_FXTAP2_5
  • RADP_DFE_FXTAP2_60
  • RADP_DFE_FXTAP2_61
  • RADP_DFE_FXTAP2_62
  • RADP_DFE_FXTAP2_63
  • RADP_DFE_FXTAP2_64
  • RADP_DFE_FXTAP2_65
  • RADP_DFE_FXTAP2_66
  • RADP_DFE_FXTAP2_67
  • RADP_DFE_FXTAP2_68
  • RADP_DFE_FXTAP2_69
  • RADP_DFE_FXTAP2_6
  • RADP_DFE_FXTAP2_70
  • RADP_DFE_FXTAP2_71
  • RADP_DFE_FXTAP2_72
  • RADP_DFE_FXTAP2_73
  • RADP_DFE_FXTAP2_74
  • RADP_DFE_FXTAP2_75
  • RADP_DFE_FXTAP2_76
  • RADP_DFE_FXTAP2_77
  • RADP_DFE_FXTAP2_78
  • RADP_DFE_FXTAP2_79
  • RADP_DFE_FXTAP2_7
  • RADP_DFE_FXTAP2_80
  • RADP_DFE_FXTAP2_81
  • RADP_DFE_FXTAP2_82
  • RADP_DFE_FXTAP2_83
  • RADP_DFE_FXTAP2_84
  • RADP_DFE_FXTAP2_85
  • RADP_DFE_FXTAP2_86
  • RADP_DFE_FXTAP2_87
  • RADP_DFE_FXTAP2_88
  • RADP_DFE_FXTAP2_89
  • RADP_DFE_FXTAP2_8
  • RADP_DFE_FXTAP2_90
  • RADP_DFE_FXTAP2_91
  • RADP_DFE_FXTAP2_92
  • RADP_DFE_FXTAP2_93
  • RADP_DFE_FXTAP2_94
  • RADP_DFE_FXTAP2_95
  • RADP_DFE_FXTAP2_96
  • RADP_DFE_FXTAP2_97
  • RADP_DFE_FXTAP2_98
  • RADP_DFE_FXTAP2_99
  • RADP_DFE_FXTAP2_9
  • RADP_DFE_FXTAP2_SGN_0
  • RADP_DFE_FXTAP2_SGN_1
  • RADP_DFE_FXTAP3_0
  • RADP_DFE_FXTAP3_100
  • RADP_DFE_FXTAP3_101
  • RADP_DFE_FXTAP3_102
  • RADP_DFE_FXTAP3_103
  • RADP_DFE_FXTAP3_104
  • RADP_DFE_FXTAP3_105
  • RADP_DFE_FXTAP3_106
  • RADP_DFE_FXTAP3_107
  • RADP_DFE_FXTAP3_108
  • RADP_DFE_FXTAP3_109
  • RADP_DFE_FXTAP3_10
  • RADP_DFE_FXTAP3_110
  • RADP_DFE_FXTAP3_111
  • RADP_DFE_FXTAP3_112
  • RADP_DFE_FXTAP3_113
  • RADP_DFE_FXTAP3_114
  • RADP_DFE_FXTAP3_115
  • RADP_DFE_FXTAP3_116
  • RADP_DFE_FXTAP3_117
  • RADP_DFE_FXTAP3_118
  • RADP_DFE_FXTAP3_119
  • RADP_DFE_FXTAP3_11
  • RADP_DFE_FXTAP3_120
  • RADP_DFE_FXTAP3_121
  • RADP_DFE_FXTAP3_122
  • RADP_DFE_FXTAP3_123
  • RADP_DFE_FXTAP3_124
  • RADP_DFE_FXTAP3_125
  • RADP_DFE_FXTAP3_126
  • RADP_DFE_FXTAP3_127
  • RADP_DFE_FXTAP3_12
  • RADP_DFE_FXTAP3_13
  • RADP_DFE_FXTAP3_14
  • RADP_DFE_FXTAP3_15
  • RADP_DFE_FXTAP3_16
  • RADP_DFE_FXTAP3_17
  • RADP_DFE_FXTAP3_18
  • RADP_DFE_FXTAP3_19
  • RADP_DFE_FXTAP3_1
  • RADP_DFE_FXTAP3_20
  • RADP_DFE_FXTAP3_21
  • RADP_DFE_FXTAP3_22
  • RADP_DFE_FXTAP3_23
  • RADP_DFE_FXTAP3_24
  • RADP_DFE_FXTAP3_25
  • RADP_DFE_FXTAP3_26
  • RADP_DFE_FXTAP3_27
  • RADP_DFE_FXTAP3_28
  • RADP_DFE_FXTAP3_29
  • RADP_DFE_FXTAP3_2
  • RADP_DFE_FXTAP3_30
  • RADP_DFE_FXTAP3_31
  • RADP_DFE_FXTAP3_32
  • RADP_DFE_FXTAP3_33
  • RADP_DFE_FXTAP3_34
  • RADP_DFE_FXTAP3_35
  • RADP_DFE_FXTAP3_36
  • RADP_DFE_FXTAP3_37
  • RADP_DFE_FXTAP3_38
  • RADP_DFE_FXTAP3_39
  • RADP_DFE_FXTAP3_3
  • RADP_DFE_FXTAP3_40
  • RADP_DFE_FXTAP3_41
  • RADP_DFE_FXTAP3_42
  • RADP_DFE_FXTAP3_43
  • RADP_DFE_FXTAP3_44
  • RADP_DFE_FXTAP3_45
  • RADP_DFE_FXTAP3_46
  • RADP_DFE_FXTAP3_47
  • RADP_DFE_FXTAP3_48
  • RADP_DFE_FXTAP3_49
  • RADP_DFE_FXTAP3_4
  • RADP_DFE_FXTAP3_50
  • RADP_DFE_FXTAP3_51
  • RADP_DFE_FXTAP3_52
  • RADP_DFE_FXTAP3_53
  • RADP_DFE_FXTAP3_54
  • RADP_DFE_FXTAP3_55
  • RADP_DFE_FXTAP3_56
  • RADP_DFE_FXTAP3_57
  • RADP_DFE_FXTAP3_58
  • RADP_DFE_FXTAP3_59
  • RADP_DFE_FXTAP3_5
  • RADP_DFE_FXTAP3_60
  • RADP_DFE_FXTAP3_61
  • RADP_DFE_FXTAP3_62
  • RADP_DFE_FXTAP3_63
  • RADP_DFE_FXTAP3_64
  • RADP_DFE_FXTAP3_65
  • RADP_DFE_FXTAP3_66
  • RADP_DFE_FXTAP3_67
  • RADP_DFE_FXTAP3_68
  • RADP_DFE_FXTAP3_69
  • RADP_DFE_FXTAP3_6
  • RADP_DFE_FXTAP3_70
  • RADP_DFE_FXTAP3_71
  • RADP_DFE_FXTAP3_72
  • RADP_DFE_FXTAP3_73
  • RADP_DFE_FXTAP3_74
  • RADP_DFE_FXTAP3_75
  • RADP_DFE_FXTAP3_76
  • RADP_DFE_FXTAP3_77
  • RADP_DFE_FXTAP3_78
  • RADP_DFE_FXTAP3_79
  • RADP_DFE_FXTAP3_7
  • RADP_DFE_FXTAP3_80
  • RADP_DFE_FXTAP3_81
  • RADP_DFE_FXTAP3_82
  • RADP_DFE_FXTAP3_83
  • RADP_DFE_FXTAP3_84
  • RADP_DFE_FXTAP3_85
  • RADP_DFE_FXTAP3_86
  • RADP_DFE_FXTAP3_87
  • RADP_DFE_FXTAP3_88
  • RADP_DFE_FXTAP3_89
  • RADP_DFE_FXTAP3_8
  • RADP_DFE_FXTAP3_90
  • RADP_DFE_FXTAP3_91
  • RADP_DFE_FXTAP3_92
  • RADP_DFE_FXTAP3_93
  • RADP_DFE_FXTAP3_94
  • RADP_DFE_FXTAP3_95
  • RADP_DFE_FXTAP3_96
  • RADP_DFE_FXTAP3_97
  • RADP_DFE_FXTAP3_98
  • RADP_DFE_FXTAP3_99
  • RADP_DFE_FXTAP3_9
  • RADP_DFE_FXTAP3_SGN_0
  • RADP_DFE_FXTAP3_SGN_1
  • RADP_DFE_FXTAP4_0
  • RADP_DFE_FXTAP4_10
  • RADP_DFE_FXTAP4_11
  • RADP_DFE_FXTAP4_12
  • RADP_DFE_FXTAP4_13
  • RADP_DFE_FXTAP4_14
  • RADP_DFE_FXTAP4_15
  • RADP_DFE_FXTAP4_16
  • RADP_DFE_FXTAP4_17
  • RADP_DFE_FXTAP4_18
  • RADP_DFE_FXTAP4_19
  • RADP_DFE_FXTAP4_1
  • RADP_DFE_FXTAP4_20
  • RADP_DFE_FXTAP4_21
  • RADP_DFE_FXTAP4_22
  • RADP_DFE_FXTAP4_23
  • RADP_DFE_FXTAP4_24
  • RADP_DFE_FXTAP4_25
  • RADP_DFE_FXTAP4_26
  • RADP_DFE_FXTAP4_27
  • RADP_DFE_FXTAP4_28
  • RADP_DFE_FXTAP4_29
  • RADP_DFE_FXTAP4_2
  • RADP_DFE_FXTAP4_30
  • RADP_DFE_FXTAP4_31
  • RADP_DFE_FXTAP4_32
  • RADP_DFE_FXTAP4_33
  • RADP_DFE_FXTAP4_34
  • RADP_DFE_FXTAP4_35
  • RADP_DFE_FXTAP4_36
  • RADP_DFE_FXTAP4_37
  • RADP_DFE_FXTAP4_38
  • RADP_DFE_FXTAP4_39
  • RADP_DFE_FXTAP4_3
  • RADP_DFE_FXTAP4_40
  • RADP_DFE_FXTAP4_41
  • RADP_DFE_FXTAP4_42
  • RADP_DFE_FXTAP4_43
  • RADP_DFE_FXTAP4_44
  • RADP_DFE_FXTAP4_45
  • RADP_DFE_FXTAP4_46
  • RADP_DFE_FXTAP4_47
  • RADP_DFE_FXTAP4_48
  • RADP_DFE_FXTAP4_49
  • RADP_DFE_FXTAP4_4
  • RADP_DFE_FXTAP4_50
  • RADP_DFE_FXTAP4_51
  • RADP_DFE_FXTAP4_52
  • RADP_DFE_FXTAP4_53
  • RADP_DFE_FXTAP4_54
  • RADP_DFE_FXTAP4_55
  • RADP_DFE_FXTAP4_56
  • RADP_DFE_FXTAP4_57
  • RADP_DFE_FXTAP4_58
  • RADP_DFE_FXTAP4_59
  • RADP_DFE_FXTAP4_5
  • RADP_DFE_FXTAP4_60
  • RADP_DFE_FXTAP4_61
  • RADP_DFE_FXTAP4_62
  • RADP_DFE_FXTAP4_63
  • RADP_DFE_FXTAP4_6
  • RADP_DFE_FXTAP4_7
  • RADP_DFE_FXTAP4_8
  • RADP_DFE_FXTAP4_9
  • RADP_DFE_FXTAP4_SGN_0
  • RADP_DFE_FXTAP4_SGN_1
  • RADP_DFE_FXTAP5_0
  • RADP_DFE_FXTAP5_10
  • RADP_DFE_FXTAP5_11
  • RADP_DFE_FXTAP5_12
  • RADP_DFE_FXTAP5_13
  • RADP_DFE_FXTAP5_14
  • RADP_DFE_FXTAP5_15
  • RADP_DFE_FXTAP5_16
  • RADP_DFE_FXTAP5_17
  • RADP_DFE_FXTAP5_18
  • RADP_DFE_FXTAP5_19
  • RADP_DFE_FXTAP5_1
  • RADP_DFE_FXTAP5_20
  • RADP_DFE_FXTAP5_21
  • RADP_DFE_FXTAP5_22
  • RADP_DFE_FXTAP5_23
  • RADP_DFE_FXTAP5_24
  • RADP_DFE_FXTAP5_25
  • RADP_DFE_FXTAP5_26
  • RADP_DFE_FXTAP5_27
  • RADP_DFE_FXTAP5_28
  • RADP_DFE_FXTAP5_29
  • RADP_DFE_FXTAP5_2
  • RADP_DFE_FXTAP5_30
  • RADP_DFE_FXTAP5_31
  • RADP_DFE_FXTAP5_32
  • RADP_DFE_FXTAP5_33
  • RADP_DFE_FXTAP5_34
  • RADP_DFE_FXTAP5_35
  • RADP_DFE_FXTAP5_36
  • RADP_DFE_FXTAP5_37
  • RADP_DFE_FXTAP5_38
  • RADP_DFE_FXTAP5_39
  • RADP_DFE_FXTAP5_3
  • RADP_DFE_FXTAP5_40
  • RADP_DFE_FXTAP5_41
  • RADP_DFE_FXTAP5_42
  • RADP_DFE_FXTAP5_43
  • RADP_DFE_FXTAP5_44
  • RADP_DFE_FXTAP5_45
  • RADP_DFE_FXTAP5_46
  • RADP_DFE_FXTAP5_47
  • RADP_DFE_FXTAP5_48
  • RADP_DFE_FXTAP5_49
  • RADP_DFE_FXTAP5_4
  • RADP_DFE_FXTAP5_50
  • RADP_DFE_FXTAP5_51
  • RADP_DFE_FXTAP5_52
  • RADP_DFE_FXTAP5_53
  • RADP_DFE_FXTAP5_54
  • RADP_DFE_FXTAP5_55
  • RADP_DFE_FXTAP5_56
  • RADP_DFE_FXTAP5_57
  • RADP_DFE_FXTAP5_58
  • RADP_DFE_FXTAP5_59
  • RADP_DFE_FXTAP5_5
  • RADP_DFE_FXTAP5_60
  • RADP_DFE_FXTAP5_61
  • RADP_DFE_FXTAP5_62
  • RADP_DFE_FXTAP5_63
  • RADP_DFE_FXTAP5_6
  • RADP_DFE_FXTAP5_7
  • RADP_DFE_FXTAP5_8
  • RADP_DFE_FXTAP5_9
  • RADP_DFE_FXTAP5_SGN_0
  • RADP_DFE_FXTAP5_SGN_1
  • RADP_DFE_FXTAP6_0
  • RADP_DFE_FXTAP6_10
  • RADP_DFE_FXTAP6_11
  • RADP_DFE_FXTAP6_12
  • RADP_DFE_FXTAP6_13
  • RADP_DFE_FXTAP6_14
  • RADP_DFE_FXTAP6_15
  • RADP_DFE_FXTAP6_16
  • RADP_DFE_FXTAP6_17
  • RADP_DFE_FXTAP6_18
  • RADP_DFE_FXTAP6_19
  • RADP_DFE_FXTAP6_1
  • RADP_DFE_FXTAP6_20
  • RADP_DFE_FXTAP6_21
  • RADP_DFE_FXTAP6_22
  • RADP_DFE_FXTAP6_23
  • RADP_DFE_FXTAP6_24
  • RADP_DFE_FXTAP6_25
  • RADP_DFE_FXTAP6_26
  • RADP_DFE_FXTAP6_27
  • RADP_DFE_FXTAP6_28
  • RADP_DFE_FXTAP6_29
  • RADP_DFE_FXTAP6_2
  • RADP_DFE_FXTAP6_30
  • RADP_DFE_FXTAP6_31
  • RADP_DFE_FXTAP6_3
  • RADP_DFE_FXTAP6_4
  • RADP_DFE_FXTAP6_5
  • RADP_DFE_FXTAP6_6
  • RADP_DFE_FXTAP6_7
  • RADP_DFE_FXTAP6_8
  • RADP_DFE_FXTAP6_9
  • RADP_DFE_FXTAP6_SGN_0
  • RADP_DFE_FXTAP6_SGN_1
  • RADP_DFE_FXTAP7_0
  • RADP_DFE_FXTAP7_10
  • RADP_DFE_FXTAP7_11
  • RADP_DFE_FXTAP7_12
  • RADP_DFE_FXTAP7_13
  • RADP_DFE_FXTAP7_14
  • RADP_DFE_FXTAP7_15
  • RADP_DFE_FXTAP7_16
  • RADP_DFE_FXTAP7_17
  • RADP_DFE_FXTAP7_18
  • RADP_DFE_FXTAP7_19
  • RADP_DFE_FXTAP7_1
  • RADP_DFE_FXTAP7_20
  • RADP_DFE_FXTAP7_21
  • RADP_DFE_FXTAP7_22
  • RADP_DFE_FXTAP7_23
  • RADP_DFE_FXTAP7_24
  • RADP_DFE_FXTAP7_25
  • RADP_DFE_FXTAP7_26
  • RADP_DFE_FXTAP7_27
  • RADP_DFE_FXTAP7_28
  • RADP_DFE_FXTAP7_29
  • RADP_DFE_FXTAP7_2
  • RADP_DFE_FXTAP7_30
  • RADP_DFE_FXTAP7_31
  • RADP_DFE_FXTAP7_3
  • RADP_DFE_FXTAP7_4
  • RADP_DFE_FXTAP7_5
  • RADP_DFE_FXTAP7_6
  • RADP_DFE_FXTAP7_7
  • RADP_DFE_FXTAP7_8
  • RADP_DFE_FXTAP7_9
  • RADP_DFE_FXTAP7_SGN_0
  • RADP_DFE_FXTAP7_SGN_1
  • RADP_DFE_FXTAP8_0
  • RADP_DFE_FXTAP8_10
  • RADP_DFE_FXTAP8_11
  • RADP_DFE_FXTAP8_12
  • RADP_DFE_FXTAP8_13
  • RADP_DFE_FXTAP8_14
  • RADP_DFE_FXTAP8_15
  • RADP_DFE_FXTAP8_16
  • RADP_DFE_FXTAP8_17
  • RADP_DFE_FXTAP8_18
  • RADP_DFE_FXTAP8_19
  • RADP_DFE_FXTAP8_1
  • RADP_DFE_FXTAP8_20
  • RADP_DFE_FXTAP8_21
  • RADP_DFE_FXTAP8_22
  • RADP_DFE_FXTAP8_23
  • RADP_DFE_FXTAP8_24
  • RADP_DFE_FXTAP8_25
  • RADP_DFE_FXTAP8_26
  • RADP_DFE_FXTAP8_27
  • RADP_DFE_FXTAP8_28
  • RADP_DFE_FXTAP8_29
  • RADP_DFE_FXTAP8_2
  • RADP_DFE_FXTAP8_30
  • RADP_DFE_FXTAP8_31
  • RADP_DFE_FXTAP8_32
  • RADP_DFE_FXTAP8_33
  • RADP_DFE_FXTAP8_34
  • RADP_DFE_FXTAP8_35
  • RADP_DFE_FXTAP8_36
  • RADP_DFE_FXTAP8_37
  • RADP_DFE_FXTAP8_38
  • RADP_DFE_FXTAP8_39
  • RADP_DFE_FXTAP8_3
  • RADP_DFE_FXTAP8_40
  • RADP_DFE_FXTAP8_41
  • RADP_DFE_FXTAP8_42
  • RADP_DFE_FXTAP8_43
  • RADP_DFE_FXTAP8_44
  • RADP_DFE_FXTAP8_45
  • RADP_DFE_FXTAP8_46
  • RADP_DFE_FXTAP8_47
  • RADP_DFE_FXTAP8_48
  • RADP_DFE_FXTAP8_49
  • RADP_DFE_FXTAP8_4
  • RADP_DFE_FXTAP8_50
  • RADP_DFE_FXTAP8_51
  • RADP_DFE_FXTAP8_52
  • RADP_DFE_FXTAP8_53
  • RADP_DFE_FXTAP8_54
  • RADP_DFE_FXTAP8_55
  • RADP_DFE_FXTAP8_56
  • RADP_DFE_FXTAP8_57
  • RADP_DFE_FXTAP8_58
  • RADP_DFE_FXTAP8_59
  • RADP_DFE_FXTAP8_5
  • RADP_DFE_FXTAP8_60
  • RADP_DFE_FXTAP8_61
  • RADP_DFE_FXTAP8_62
  • RADP_DFE_FXTAP8_63
  • RADP_DFE_FXTAP8_6
  • RADP_DFE_FXTAP8_7
  • RADP_DFE_FXTAP8_8
  • RADP_DFE_FXTAP8_9
  • RADP_DFE_FXTAP8_SGN_0
  • RADP_DFE_FXTAP8_SGN_1
  • RADP_DFE_FXTAP9_0
  • RADP_DFE_FXTAP9_10
  • RADP_DFE_FXTAP9_11
  • RADP_DFE_FXTAP9_12
  • RADP_DFE_FXTAP9_13
  • RADP_DFE_FXTAP9_14
  • RADP_DFE_FXTAP9_15
  • RADP_DFE_FXTAP9_16
  • RADP_DFE_FXTAP9_17
  • RADP_DFE_FXTAP9_18
  • RADP_DFE_FXTAP9_19
  • RADP_DFE_FXTAP9_1
  • RADP_DFE_FXTAP9_20
  • RADP_DFE_FXTAP9_21
  • RADP_DFE_FXTAP9_22
  • RADP_DFE_FXTAP9_23
  • RADP_DFE_FXTAP9_24
  • RADP_DFE_FXTAP9_25
  • RADP_DFE_FXTAP9_26
  • RADP_DFE_FXTAP9_27
  • RADP_DFE_FXTAP9_28
  • RADP_DFE_FXTAP9_29
  • RADP_DFE_FXTAP9_2
  • RADP_DFE_FXTAP9_30
  • RADP_DFE_FXTAP9_31
  • RADP_DFE_FXTAP9_32
  • RADP_DFE_FXTAP9_33
  • RADP_DFE_FXTAP9_34
  • RADP_DFE_FXTAP9_35
  • RADP_DFE_FXTAP9_36
  • RADP_DFE_FXTAP9_37
  • RADP_DFE_FXTAP9_38
  • RADP_DFE_FXTAP9_39
  • RADP_DFE_FXTAP9_3
  • RADP_DFE_FXTAP9_40
  • RADP_DFE_FXTAP9_41
  • RADP_DFE_FXTAP9_42
  • RADP_DFE_FXTAP9_43
  • RADP_DFE_FXTAP9_44
  • RADP_DFE_FXTAP9_45
  • RADP_DFE_FXTAP9_46
  • RADP_DFE_FXTAP9_47
  • RADP_DFE_FXTAP9_48
  • RADP_DFE_FXTAP9_49
  • RADP_DFE_FXTAP9_4
  • RADP_DFE_FXTAP9_50
  • RADP_DFE_FXTAP9_51
  • RADP_DFE_FXTAP9_52
  • RADP_DFE_FXTAP9_53
  • RADP_DFE_FXTAP9_54
  • RADP_DFE_FXTAP9_55
  • RADP_DFE_FXTAP9_56
  • RADP_DFE_FXTAP9_57
  • RADP_DFE_FXTAP9_58
  • RADP_DFE_FXTAP9_59
  • RADP_DFE_FXTAP9_5
  • RADP_DFE_FXTAP9_60
  • RADP_DFE_FXTAP9_61
  • RADP_DFE_FXTAP9_62
  • RADP_DFE_FXTAP9_63
  • RADP_DFE_FXTAP9_6
  • RADP_DFE_FXTAP9_7
  • RADP_DFE_FXTAP9_8
  • RADP_DFE_FXTAP9_9
  • RADP_DFE_FXTAP9_SGN_0
  • RADP_DFE_FXTAP9_SGN_1
  • RADP_LFEQ_FB_SEL_0
  • RADP_LFEQ_FB_SEL_1
  • RADP_LFEQ_FB_SEL_2
  • RADP_LFEQ_FB_SEL_3
  • RADP_LFEQ_FB_SEL_4
  • RADP_LFEQ_FB_SEL_5
  • RADP_LFEQ_FB_SEL_6
  • RADP_LFEQ_FB_SEL_7
  • RADP_ONETIME_DFE_0
  • RADP_ONETIME_DFE_1
  • RADP_VGA_SEL_0
  • RADP_VGA_SEL_1
  • RADP_VGA_SEL_2
  • RADP_VGA_SEL_3
  • RADP_VGA_SEL_4
  • RADP_VGA_SEL_5
  • RADP_VGA_SEL_6
  • RADP_VGA_SEL_7
  • RADP_VREF_SEL_0
  • RADP_VREF_SEL_10
  • RADP_VREF_SEL_11
  • RADP_VREF_SEL_12
  • RADP_VREF_SEL_13
  • RADP_VREF_SEL_14
  • RADP_VREF_SEL_15
  • RADP_VREF_SEL_16
  • RADP_VREF_SEL_17
  • RADP_VREF_SEL_18
  • RADP_VREF_SEL_19
  • RADP_VREF_SEL_1
  • RADP_VREF_SEL_20
  • RADP_VREF_SEL_21
  • RADP_VREF_SEL_22
  • RADP_VREF_SEL_23
  • RADP_VREF_SEL_24
  • RADP_VREF_SEL_25
  • RADP_VREF_SEL_26
  • RADP_VREF_SEL_27
  • RADP_VREF_SEL_28
  • RADP_VREF_SEL_29
  • RADP_VREF_SEL_2
  • RADP_VREF_SEL_30
  • RADP_VREF_SEL_31
  • RADP_VREF_SEL_3
  • RADP_VREF_SEL_4
  • RADP_VREF_SEL_5
  • RADP_VREF_SEL_6
  • RADP_VREF_SEL_7
  • RADP_VREF_SEL_8
  • RADP_VREF_SEL_9
  • RAM_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY
  • RAM_CTL
  • RAM_REGISTER_DUPLICATION
  • RAMSTYLE_ATTRIBUTE
  • RAM_USE_DCD
  • RANDOM
  • RANDOM_PIN
  • RANDOM_PIN_SEED
  • RAPID_RECOMPILE_ASSIGNMENT_CHECKING
  • RAPID_RECOMPILE_MODE
  • RAPID_RECOMPILE_SYNTHESIS_MODE
  • RAW_BINARY_FILE
  • RBCGEN_CRITICAL_WARNING_TO_ERROR
  • RDYNBUSY_RESERVED
  • READ
  • READ_OR_WRITE_IN_BYTE_ADDRESS
  • REALISTIC
  • RECOMPILE_QUESTION
  • RECONFIGURABLE
  • RECONFIGURABLE_REVISION
  • REFCLK_COUNTER_OUT
  • REFCLK_COUPLING_OCT
  • REGENERATE_IP_IF_HDL_QSYS_MISMATCH
  • REGISTER_LOCATION_TYPE
  • REGISTER_PACKING_ARMSTRONG
  • REGISTER_PACKING_TSUNAMI
  • REGISTERS_ONLY
  • RELATIVE_NEUTRON_FLUX
  • RELEASE_CLEARS_BEFORE_TRI
  • RELEASE_CLEARS_BEFORE_TRI_STATES
  • REMOTE
  • REMOVE_DUPLICATE_LOGIC
  • REMOVE_DUPLICATE_REGISTERS
  • REMOVE_FANOUT_FREE_REGISTERS
  • REMOVE
  • REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS
  • REMOVE_REDUNDANT_LOGIC_CELLS
  • REMOVE_REDUNDANT_USER_CELLS
  • REPLACE_CONFLICTING
  • REPORT_AS_DQS
  • REPORT_CONNECTIVITY_CHECKS
  • REPORT_DELAY
  • REPORT_IO_PATHS_SEPARATELY
  • REPORT_PARAMETER_SETTINGS
  • REPORT_PARAMETER_SETTINGS_PRO
  • REPORT_SOURCE_ASSIGNMENTS
  • REPORT_SOURCE_ASSIGNMENTS_PRO
  • REQUIRED_DUTY_CYCLE
  • REQUIRED_FMAX
  • RESERVE_ALL_UNUSED_PINS
  • RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND
  • RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP
  • RESERVE_ASDO_AFTER_CONFIGURATION
  • RESERVE_AVST_CLK_AFTER_CONFIGURATION
  • RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION
  • RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION
  • RESERVE_AVST_VALID_AFTER_CONFIGURATION
  • RESERVED1
  • RESERVED2
  • RESERVED3
  • RESERVED_ALL_UNUSED_PINS
  • RESERVED_ALL_UNUSED_PINS_NO_OUTPUT_GND
  • RESERVE_DATA0_AFTER_CONFIGURATION
  • RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION
  • RESERVE_DATA1_AFTER_CONFIGURATION
  • RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION
  • RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION
  • RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION
  • RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION
  • RESERVE_DCLK_AFTER_CONFIGURATION
  • RESERVED_PIN
  • RESERVE_FLASH_NCE_AFTER_CONFIGURATION
  • RESERVE_FLEXIBLE_CLOCK_NETWORK
  • RESERVE_NCEO_AFTER_CONFIGURATION
  • RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION
  • RESERVE_OTHER_APF_PINS_AFTER_CONFIGURATION
  • RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION
  • RESERVE_PIN
  • RESERVE_PLACE_REGION
  • RESERVE_PR_PINS
  • RESERVE_RDYNBUSY_AFTER_CONFIGURATION
  • RESERVE_ROUTING_OUTPUT_FLEXIBILITY
  • RESERVE_SDO_AFTER_CONFIGURATION
  • RESET_CAT
  • RESET_RULE_ALL
  • RESET_RULE_COMB_ASYNCH_RESET
  • RESET_RULE_IMSYNCH_ASYNCH_DOMAIN
  • RESET_RULE_IMSYNCH_EXRESET
  • RESET_RULE_INPINS_RESETNET
  • RESET_RULE_REG_ASNYCH
  • RESET_RULE_UNSYNCH_ASYNCH_DOMAIN
  • RESET_RULE_UNSYNCH_EXRESET
  • RESOLVE_FILENAME
  • RESOURCE_ALLOCATION
  • RESYNTHESIS_EXTRA_DEBUGGING_INFORMATION
  • RESYNTHESIS_OPTIMIZATION_EFFORT
  • RESYNTHESIS_PHYSICAL_SYNTHESIS
  • RESYNTHESIS_RETIMING
  • RETAIN_COMB_LOGIC_OUTSIDE_CLOUD
  • RETIMER_ASSIGNMENT
  • RETIMER_FAST_FORWARD_ASSIGNMENT
  • REVISION_BASED_FILE_NAME
  • REVISION_CONTROL_DIR
  • REVISION_CONTROL_SYSTEM
  • REVISION_CONTROL_TCL
  • REVISION_CONTROL_TCL_SCRIPT
  • REVISION_TYPE
  • R_EXT0
  • RISE
  • ROOT
  • ROUTER_CLOCKING_TOPOLOGY_ANALYSIS
  • ROUTER_EFFORT_MULTIPLIER
  • ROUTE_REGION
  • ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION
  • ROUTER_REGISTER_DUPLICATION
  • ROUTER_TIMING_OPTIMIZATION_LEVEL
  • ROUTING_BACK_ANNOTATE
  • ROUTING_BACK_ANNOTATION_FILE
  • ROUTING_BACK_ANNOTATION_MODE
  • ROW_GLOBAL_SIGNAL
  • R_R1
  • R_R2
  • RR_HYBRID
  • RTERM_CODE0
  • RTERM_CODE10
  • RTERM_CODE11
  • RTERM_CODE12
  • RTERM_CODE13
  • RTERM_CODE14
  • RTERM_CODE15
  • RTERM_CODE1
  • RTERM_CODE2
  • RTERM_CODE3
  • RTERM_CODE4
  • RTERM_CODE5
  • RTERM_CODE6
  • RTERM_CODE7
  • RTERM_CODE8
  • RTERM_CODE9
  • RTLV_GROUP_COMB_LOGIC_IN_CLOUD
  • RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV
  • RTLV_GROUP_RELATED_NODES
  • RTLV_GROUP_RELATED_NODES_TMV
  • RTLV_PRESERVED_HANGING_NODES
  • RTLV_REMOVE_FANOUT_FREE_REGISTERS
  • RTLV_RETAIN_COMB_LOGIC_OUTSIDE_CLOUD
  • RTLV_SIMPLIFIED_LOGIC
  • RUN_ALL_TIMING_ANALYSES
  • RUN_CLOCK_TAN
  • RUN_COMPARISON_ON_EVERY_COMPILE
  • RUN_DRC_DURING_COMPILATION
  • RUN_FITTER_IN_SIGNALPROBE_MODE
  • RUN_FULL_COMPILE_ON_DEVICE_CHANGE
  • RUN_P2P_TAN
  • RUN_TAN
  • RUN_TIMING_ANALYSES
  • RUN_TIMING_ANALYSES_ONLY_FOR_TIMING_ASSIGNMENTS
  • RX_DET_OFF
  • RX_DET_ON
  • RX_DET_PCIE_OUT
  • RX_DET_QPI_OUT
  • RZQ_GROUP
  • S0L9
  • SAFE_STATE_MACHINE
  • SAME_AS_MULTICYCLE
  • SAMPLE_AND_SUSTAIN
  • SAP_NAME
  • SATA1_I
  • SATA1_M
  • SATA1_X
  • SATA2_I
  • SATA2_M
  • SATA2_X
  • SAVE_DISK_SPACE
  • SAVE_INTERMEDIATE_FITTING_RESULTS
  • SAVE_MIGRATION_INFO_DURING_COMPILATION
  • SBI_FILE
  • SCE_PIN
  • SDC_ENTITY_FILE
  • SDC_ENTITY_HELPER_FILE
  • SDC_STATEMENT
  • SDC_UNIQUIFIED_STATEMENT
  • SDI_1485_HD
  • SDI_270_SD
  • SDI_2970_3G
  • SDLV_0
  • SDLV_10
  • SDLV_11
  • SDLV_12
  • SDLV_13
  • SDLV_14
  • SDLV_15
  • SDLV_1
  • SDLV_2
  • SDLV_3
  • SDLV_4
  • SDLV_5
  • SDLV_6
  • SDLV_7
  • SDLV_8
  • SDLV_9
  • SDO_PIN
  • SDO_RESERVED
  • SEARCH_PATH
  • SECTION_COLUMN
  • SECURITY_BIT
  • SELECTED_EDGE
  • SEQUENTIAL
  • SERIAL_BITSTREAM_FILE
  • SERIAL_LITE_III_16400
  • SERIAL_LITE_III_17400
  • SERIAL_VECTOR_FILE
  • SERIES_25_OHMS
  • SERIES_25_OHMS_WITH_CALIBRATION
  • SERIES_25_OHMS_WITHOUT_CALIBRATION
  • SERIES_50_OHMS
  • SERIES_50_OHMS_WITH_CALIBRATION
  • SERIES_50_OHMS_WITHOUT_CALIBRATION
  • SET_PULSE_WIDTH
  • SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED
  • SETUP_HOLD_DETECTION
  • SETUP_HOLD_TIME_VIOLATION_DETECTION
  • SETUP_RELATIONSHIP
  • SEU_FIT_REPORT
  • SFCU
  • SFI_S_6250
  • SFIS
  • SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL
  • SHOW_ALL_TAN_PANELS
  • SHOW_PARAMETER_SETTINGS_TABLES_IN_SYNTHESIS_REPORT
  • SHOW_REGISTRATION_MESSAGE
  • SHOW_TIMING_MODEL_CHANGE_MESSAGE
  • SIGNAL_ACTIVITY_FILE
  • SIGNAL_INTEGRITY_ASSIGNMENT
  • SIGNAL_INTEGRITY_WILDCARDS
  • SIGNALPROBE_ALLOW_OVERUSE
  • SIGNALPROBE_ASSIGNMENT
  • SIGNALPROBE_CLOCK
  • SIGNALPROBE_DURING_NORMAL_COMPILATION
  • SIGNAL_PROBE_ENABLE
  • SIGNALPROBE_ENABLE
  • SIGNALPROBE_NUM_REGISTERS
  • SIGNALRACE_CAT
  • SIGNALRACE_RULE_ASYNCHPIN_SYNCH_CLKPIN
  • SIGNALRACE_RULE_CLK_PORT_RACE
  • SIGNALRACE_RULE_RESET_RACE
  • SIGNALRACE_RULE_SECOND_SIGNAL_RACE
  • SIGNALRACE_RULE_TRISTATE
  • SIGNALTAP_ASSIGNMENTS
  • SIGNALTAP_LOGIC_ANALYZER_PROJECT_FILES
  • SIGNALTAP_LOGIC_ANALYZER_SETTINGS
  • SIGNOFF_ONLY
  • SIM_AUTO_USE_GLITCH_FILTERING
  • SIM_BEHAVIOR_SIMULATION
  • SIM_BUS_CHANNEL_GROUPING
  • SIM_CELL_DELAY_MODEL_TYPE
  • SIM_COMPARE_SIGNAL
  • SIM_COMPILE_HDL_FILES
  • SIM_DEFAULT_VECTOR_COMPARE_TOLERANCE
  • SIM_DELAY_MODEL_TYPE
  • SIM_ENABLE_SIMULATION_NETLIST_VIEWER
  • SIMGEN_ARBITRARY_BLACKBOX
  • SIMGEN_BLACKBOX_FILE
  • SIMGEN_PARAMETER
  • SIM_HDL_TOP_MODULE_NAME
  • SIM_INTERCONNECT_DELAY_MODEL_TYPE
  • SIM_NO_DELAYS
  • SIM_OUTPUT_POWERPLAY_VCD
  • SIM_OUTPUT_POWERPLAY_VCD_NAME
  • SIM_OUTPUT_SAF
  • SIM_OUTPUT_SAF_NAME
  • SIM_OVERWRITE_WAVEFORM_INPUTS
  • SIMPLE_18_BIT_MULTIPLIERS
  • SIMPLE_MULTIPLIERS
  • SIMPLE_MULT
  • SIMPLE_MULT_UPGRADE_WIDTH
  • SIM_POWERPLAY_VCD_END_TIME
  • SIM_POWERPLAY_VCD_START_TIME
  • SIM_PVT_TIMING_MODEL_TYPE
  • SIM_SET_NO_DELAYS_VIRTUAL_IO
  • SIM_SIGNAL_ACTIVITY_END_TIME
  • SIM_SIGNAL_ACTIVITY_START_TIME
  • SIM_SIGNAL_COMPARE_TOLERANCE
  • SIM_SIGNAL_TRIGGER_VECTOR_COMPARE
  • SIM_SIMULATION_DEBUGGER
  • SIM_TAP_REGISTER_D_Q_PORTS
  • SIMULATION_ASSIGNMENT
  • SIMULATION_BUS_CHANNEL_GROUPING
  • SIMULATION_CELL_DELAY_MODEL_TYPE
  • SIMULATION_COMPARE_SIGNAL
  • SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL
  • SIMULATION_COVERAGE
  • SIMULATION_DEFAULT_VECTOR_COMPARE_TOLERANCE
  • SIMULATION_DELAY_MODEL_TYPE
  • SIMULATION_INCREMENTAL_TIME_INPUT
  • SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE
  • SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL
  • SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL
  • SIMULATION_MODE
  • SIMULATION_NETLIST_VIEWER
  • SIMULATION_SIGNAL_COMPARE_TOLERANCE
  • SIMULATION_TYPE
  • SIMULATION_VDB_RESULT_FLUSH
  • SIMULATION_VECTOR_COMPARE_BEGIN_TIME
  • SIMULATION_VECTOR_COMPARE_END_TIME
  • SIMULATION_VECTOR_COMPARE_RULE_FOR_0
  • SIMULATION_VECTOR_COMPARE_RULE_FOR_1
  • SIMULATION_VECTOR_COMPARE_RULE_FOR_DC
  • SIMULATION_VECTOR_COMPARE_RULE_FOR_H
  • SIMULATION_VECTOR_COMPARE_RULE_FOR_L
  • SIMULATION_VECTOR_COMPARE_RULE_FOR_U
  • SIMULATION_VECTOR_COMPARE_RULE_FOR_W
  • SIMULATION_VECTOR_COMPARE_RULE_FOR_X
  • SIMULATION_VECTOR_COMPARE_RULE_FOR_Z
  • SIMULATION_WITH_AUTO_GLITCH_FILTERING
  • SIMULATION_WITH_GLITCH_FILTERING_IN_NORMAL_FLOW
  • SIMULATION_WITH_GLITCH_FILTERING
  • SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF
  • SIMULATOR_ACTION_POINTS
  • SIMULATOR_GENERATE_POWERPLAY_VCD_FILE
  • SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE
  • SIMULATOR_POWERPLAY_VCD_FILE_END_TIME
  • SIMULATOR_POWERPLAY_VCD_FILE_OUTPUT_DESTINATION
  • SIMULATOR_POWERPLAY_VCD_FILE_START_TIME
  • SIMULATOR_PVT_TIMING_MODEL_TYPE
  • SIMULATOR_SETTINGS
  • SIMULATOR_SETTINGS_LIST
  • SIMULATOR_SIGNAL_ACTIVITY_FILE_END_TIME
  • SIMULATOR_SIGNAL_ACTIVITY_FILE_OUTPUT_DESTINATION
  • SIMULATOR_SIGNAL_ACTIVITY_FILE_START_TIME
  • SIMULATOR_TCL_SCRIPT_FILE
  • SIM_USE_FAST_TIMING_MODEL
  • SIM_USE_GLITCH_FILTERING
  • SIM_USE_GLITCH_FILTERING_WHEN_GENERATING_SAF
  • SIM_USE_PDB_NETLIST
  • SIM_VDB_RESULT_FLUSH
  • SIM_VECTOR_COMPARE_BEGIN_TIME
  • SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE
  • SIM_VECTOR_COMPARED_CLOCK_OFFSET
  • SIM_VECTOR_COMPARED_CLOCK_PERIOD
  • SIM_VECTOR_COMPARE_END_TIME
  • SIM_VECTOR_COMPARE_RULE_FOR_0
  • SIM_VECTOR_COMPARE_RULE_FOR_1
  • SIM_VECTOR_COMPARE_RULE_FOR_DC
  • SIM_VECTOR_COMPARE_RULE_FOR_H
  • SIM_VECTOR_COMPARE_RULE_FOR_L
  • SIM_VECTOR_COMPARE_RULE_FOR_U
  • SIM_VECTOR_COMPARE_RULE_FOR_W
  • SIM_VECTOR_COMPARE_RULE_FOR_X
  • SIM_VECTOR_COMPARE_RULE_FOR_Z
  • SIM_VECTOR_COMPARE_TRIGGER_CLOCK
  • SIM_VECTOR_COMPARE_TRIGGER_MODE
  • SIM_VECTOR_COMPARE_TRIGGER_SIGNAL
  • SIM_VECTOR_OUTPUT_FILE
  • SIM_VECTOR_OUTPUT_FORMAT
  • SINGLE_COMP_IMAGE
  • SINGLE_COMP_IMAGE_WITH_ERAM
  • SINGLE_IMAGE
  • SINGLE_IMAGE_WITH_ERAM
  • SINGLE_PIN
  • SIP_FILE
  • SKIP_ATOM_SWEEPER
  • SKIP_CONFLICTING
  • SKIP_CRC_CHECK_IN_HC
  • SKIP_REGENERATING_IP_IF_HDL_MODIFIED
  • SLD_BIDIR_PIN_CONNECT_FROM_PORT
  • SLD_FABRIC_PARTITION
  • SLD_FILE
  • SLD_INCR_NODE_CREATOR_ID
  • SLD_INCR_NODE_ENTITY_NAME
  • SLD_INCR_NODE_PARAMETER_ASSIGNMENT
  • SLD_INCR_NODE_SOURCE_FILE
  • SLD_INFO
  • SLD_NODE_CONNECT_FROM_PORT
  • SLD_NODE_CONNECT_TO_PORT
  • SLD_NODE_CREATOR_ID
  • SLD_NODE_ENTITY_NAME
  • SLD_NODE_PARAMETER_ASSIGNMENT
  • SLD_NODE_SOURCE_FILE
  • SLD_PARAMETER_ASSIGNMENT
  • SLD_PARAMETER_COMPATIBILITY_STRING
  • SLD_PIN_CONNECT_FROM_PORT
  • SLD_PIN_CONNECT_TO_PORT
  • SLD_PRE_SYN_COMPATIBILITY_STRING
  • SLEW_R0
  • SLEW_R1
  • SLEW_R2
  • SLEW_R3
  • SLEW_R4
  • SLEW_R5
  • SLEW_R6
  • SLEW_R7
  • SLOW_POR_DELAY
  • SLOW_SLEW_RATE
  • SMALL
  • SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES
  • SMART_RECOMPILE
  • SMF_FILE
  • SMP_PROCESS_TYPE
  • SOFTWARE_ACTION_POINTS
  • SOFTWARE_LIBRARY_FILE
  • SOFTWARE_SETTINGS
  • SOFTWARE_SETTINGS_LIST
  • SONET
  • SONET_OC12_622
  • SONET_OC192_9953
  • SONET_OC3_155
  • SONET_OC48_2488
  • SOPC_BUILDER_SIGNATURE_ID
  • SOPC_FILE
  • SOPCINFO_FILE
  • SOURCES_PER_DESTINATION_INCLUDE_COUNT
  • SOURCE_SYNCHRONOUS
  • SOURCE_TCL_SCRIPT_FILE
  • SOURCE_TCL_SCRIPT
  • SPARSE_AUTO
  • SPARSE
  • SPAUI_6250
  • SPD_FILE
  • SPECTRAQ_PHYSICAL_SYNTHESIS
  • SPEED_DISK_USAGE_TRADEOFF
  • SPEED
  • SRECORDS_FILE
  • SRIO_1250_LR
  • SRIO_1250_SR
  • SRIO_2500_LR
  • SRIO_2500_SR
  • SRIO_3125_LR
  • SRIO_3125_SR
  • SRIO_5000_LR
  • SRIO_5000_MR
  • SRIO_5000_SR
  • SRIO_6250_LR
  • SRIO_6250_MR
  • SRIO_6250_SR
  • SRIO
  • STA_IGNORED_EMBEDDED_SDC_STATEMENT
  • STA_MODE
  • STANDARD_DELAY_FORMAT_OUTPUT_FILE
  • STANDARD_FIT
  • STANDARD_PARTITION
  • STATE_MACHINE_PROCESSING
  • STD_ONLY
  • STG1_GAIN7
  • STG2_GAIN7
  • STG3_GAIN7
  • STG4_GAIN7
  • STOP
  • STP_FILE
  • STP_INCREMENTAL_SOURCE
  • STP_SIGNAL_PROBE_SOURCE
  • STP_SIGNALPROBE_SOURCE
  • STP_VIRTUAL_PIN_CLK_SOURCE
  • STP_VIRTUAL_PIN
  • STRATIX_CARRY_CHAIN_LENGTH
  • STRATIX_CONFIG_DEVICE_JTAG_USER_CODE
  • STRATIX_CONFIGURATION_DEVICE
  • STRATIX_CONFIGURATION_SCHEME
  • STRATIX_CRC_ERROR_CHECKING
  • STRATIX_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
  • STRATIX_DEVICE_IO_STANDARD
  • STRATIX_FAST_PLL_INCREASE_LOCK_WINDOW
  • STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET
  • STRATIXGX_ALLOW_DEDICATED_CLOCK_FANOUT_WITH_ANALOG_RESET
  • STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE
  • STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE
  • STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER
  • STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B
  • STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE
  • STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE
  • STRATIXGX_ALLOW_POST8B10B_LOOPBACK
  • STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK
  • STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE
  • STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS
  • STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE
  • STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER
  • STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE
  • STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT
  • STRATIXGX_OCT_VALUE
  • STRATIXGX_TERMINATION_VALUE
  • STRATIXII_ALLOW_DUAL_PORT_DUAL_CLOCK_MRAM_USAGE
  • STRATIXII_CARRY_CHAIN_LENGTH
  • STRATIX_II_CONFIGURATION_DEVICE
  • STRATIXII_CONFIGURATION_DEVICE
  • STRATIX_II_CONFIGURATION_SCHEME
  • STRATIXII_CONFIGURATION_SCHEME
  • STRATIXII_EP2S60ES_ALLOW_MRAM_USAGE
  • STRATIXIIGX_OCT_VALUE
  • STRATIXIIGX_TERMINATION_VALUE
  • STRATIXIII_CONFIGURATION_SCHEME
  • STRATIXIII_LUTAB_SLOWDOWN
  • STRATIXIII_MRAM_COMPATIBILITY
  • STRATIXIII_OUTPUT_DUTY_CYCLE_DELAY
  • STRATIXIII_UPDATE_MODE
  • STRATIXII_MRAM_COMPATIBILITY
  • STRATIXII_OPTIMIZATION_TECHNIQUE
  • STRATIXII_OUTPUT_DUTY_CYCLE_CONTROL
  • STRATIXII_SILICON_VERSION
  • STRATIXII_TERMINATION
  • STRATIXIV_CONFIGURATION_SCHEME
  • STRATIX_JTAG_USER_CODE
  • STRATIX_OPTIMIZATION_TECHNIQUE
  • STRATIX_TECHNOLOGY_MAPPER
  • STRATIX_UPDATE_MODE
  • STRATIXV_CONFIGURATION_SCHEME
  • STRICT_POST_FIT
  • STRICT_RAM_RECOGNITION
  • STRIPE_TO_PLD_BRIDGE_EPXA4_10
  • STRIPE_TO_PLD_INTERRUPTS_EPXA4_10
  • SUBCLIQUE_OF
  • SUPPRESS_DA_RULE_INTERNAL
  • SUPPRESS_REG_MINIMIZATION_MSG
  • SYMBOL_FILE
  • SYM_FILE
  • SYNCHRONIZATION_REGISTER_CHAIN_LENGTH
  • SYNCHRONIZER_IDENTIFICATION
  • SYNCHRONIZER_TOGGLE_RATE
  • SYNCHRONOUS_GROUP
  • SYNTH_CHECK_PORT_CONNECTIONS
  • SYNTH_CLOCK_MUX_PROTECTION
  • SYNTH_CRITICAL_CLOCK
  • SYNTH_CRITICAL_CLOCK_TO_OUTPUT
  • SYNTH_CRITICAL_ENABLE
  • SYNTH_CRITICAL_INPUT_TO_CLOCK
  • SYNTH_CRITICAL_PIN
  • SYNTHESIS_FITTING_SETTINGS
  • SYNTHESIS_KEEP_SYNCH_CLEAR_PRESET_BEHAVIOR_IN_UNMAPPER
  • SYNTHESIS_ON_ATOMS
  • SYNTHESIS_ONLY
  • SYNTHESIS_ONLY_QIP
  • SYNTHESIS_S10_MIGRATION_CHECKS
  • SYNTHESIS_SEED
  • SYNTHESIS_WILDCARDS
  • SYNTH_GATED_CLOCK_CONVERSION
  • SYNTH_MESSAGE_LEVEL
  • SYNTH_PROTECT_SDC_CONSTRAINT
  • SYNTH_REPORT_SOURCE_ASSIGNMENTS
  • SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM
  • SYNTH_RPT_SHOW_PARAMS_PER_ENTITY_INSTANCE
  • SYNTH_TIMING_DRIVEN_BALANCED_MAPPING
  • SYNTH_TIMING_DRIVEN_REGISTER_DUPLICATION
  • SYNTH_TIMING_DRIVEN_SYNTHESIS
  • SYSTEMVERILOG_2005
  • SYSTEMVERILOG_FILE
  • T10_DELAY
  • T10_FINE_DELAY
  • T10_OCT_DELAY
  • T10_OE_DELAY
  • T10_OE_FINE_DELAY
  • T11_0_DELAY
  • T11_1_DELAY
  • T11_DELAY
  • T11_FINE_DELAY
  • T1_DELAY
  • T1_FINE_DELAY
  • T2_DELAY
  • T3_DELAY
  • T4_DELAY
  • T7_DELAY
  • T7_FINE_DELAY
  • T8_DELAY0
  • T8_DELAY1
  • T9_DELAY
  • T9_FINE_DELAY
  • T9_OCT_DELAY
  • T9_OE_DELAY
  • TAN_SCRIPT_FILE
  • TAO_FILE
  • TAO_FILE_NAME
  • TBFF_PULSE_WIDTH
  • TCL_ENTITY_FILE
  • TCL_FILE
  • TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT
  • TDC_CCPP_TRADEOFF_TOLERANCE
  • TDO_DUMP_FILE
  • TECH_MAPPER_APEX20K
  • TECH_MAPPER_DALI
  • TECH_MAPPER_FLEX10K
  • TECH_MAPPER_FLEX6K
  • TECH_MAPPER
  • TECH_MAPPER_MAX7000
  • TECH_MAPPER_YEAGER
  • TECHNOLOGY_MAPPER_DALI
  • TECHNOLOGY_MAPPER_FLEX6K
  • TEMPLATE_FILE
  • TENG_1588
  • TENG_BASER
  • TENG_KR_10312
  • TENG_SDI
  • TERMINATION_CONTROL_BLOCK
  • TEST_BENCH_MODE
  • TESTING_BOOL
  • TESTING_ENUM
  • TESTING_FILE
  • TESTING_INT_GLOBAL_DISALLOWED_IN_QIP
  • TESTING_INT
  • TESTING_SINGLE_ABSOLUTE_NODE_ENTITY_INT
  • TESTING_SINGLE_BOOL
  • TESTING_SINGLE_ENUM
  • TESTING_SINGLE_INT
  • TESTING_SINGLE_RELATIVE_BOOL
  • TESTING_SINGLE_RELATIVE_ENTITY_INT
  • TESTING_SINGLE_RELATIVE_NODE_ENTITY_BOOL
  • TESTING_SINGLE_RELATIVE_NODE_ENTITY_INT
  • TESTING_SINGLE_RELATIVE_NODE_INT
  • TESTING_SINGLE_STRING
  • TESTING_STRING
  • TEXT_FORMAT_REPORT_FILE
  • THIRD_PARTY_EDA_TOOLS
  • THREE
  • TH_REQUIREMENT
  • THR_THREAD_MAIN_ID
  • TIMEGROUP_EXCEPTION
  • TIMEGROUP_MEMBER
  • TIMEQUEST2
  • TIMEQUEST_CCPP_TRADEOFF_TOLERANCE
  • TIMEQUEST_DO_CCPP_REMOVAL
  • TIMEQUEST_DO_REPORT_TIMING
  • TIMEQUEST_MULTICORNER_ANALYSIS
  • TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS
  • TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS
  • TIMEQUEST_REPORT_SCRIPT
  • TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS
  • TIMEQUEST_SPECTRA_Q
  • TIMING_ANALYSIS_OUTPUT_FILE
  • TIMING_ASSIGNMENT
  • TIMING_CAT
  • TIMING_DERATING_FILE
  • TIMING_RULE_COIN_CLKEDGE
  • TIMING_RULE_HIGH_FANOUTS
  • TIMING_RULE_SHIFT_REG
  • TIMING_USING_FAST_TIMING_MODEL
  • TOOLSET
  • TOP_LEVEL_ENTITY
  • TOP_PARTITION_PIN
  • TRANSPORT
  • TREAT_BIDIR_AS_OUTPUT
  • TRI_CONVERTED_FROM_DIRECTIONAL_BUFFER
  • TRIGGER_EQUATION
  • TRIGGER_VECTOR_COMPARE_ON_SIGNAL
  • TRISTATE1
  • TRISTATED1
  • TRI_STATE
  • TRISTATE_OFF
  • TRISTATE_ON
  • TRI_STATE_SPI_PINS
  • TRUE
  • TRUE_WYSIWYG_FLOW
  • TSUNAMI_OPTIMIZATION_TECHNIQUE
  • TSU_REQUIREMENT
  • TXPMA_SLEW_RATE
  • TYPICAL
  • UC_DCD_CAL_OFF
  • UC_DCD_CAL_ON
  • UC_RO_CAL_OFF
  • UC_RO_CAL_ON
  • UC_RX_DFE_CAL_OFF
  • UC_RX_DFE_CAL_ON
  • UC_SKEW_CAL_OFF
  • UC_SKEW_CAL_ON
  • UC_TX_VOD_CAL_CONT_OFF
  • UC_TX_VOD_CAL_CONT_ON
  • UC_TX_VOD_CAL_OFF
  • UC_TX_VOD_CAL_ON
  • UI_DEFAULT_ASSEMBLER_SETTING
  • UI_DEFAULT_COMP_PROCESS_SETTING
  • UI_DEFAULT_EDA_NATIVELINK_SETTING
  • UI_DEFAULT_EDA_SIMULATION_SETTING
  • UI_DEFAULT_FITTER_SETTING
  • UI_DEFAULT_HYPERFLEX_SETTING
  • UI_DEFAULT_OPTIMIZATION_SETTING
  • UI_DEFAULT_SIMULATOR_SETTING
  • UI_DEFAULT_SYNTHESIS_SETTING
  • UI_DEFAULT_TIMING_SETTING
  • UNFORCE_MERGE_PLL
  • UNFORCE_MERGE_PLL_OUTPUT_COUNTER
  • UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE
  • UNIPHY_TEMP_VER_CODE
  • UNNAMED_POOL
  • UNSECURED
  • UNUSED_RXCLK_BTI_MITIGATION
  • UNUSED_RXTXCLK_BTI_MITIGATION
  • UNUSED_TSD_PINS_GND
  • UPCORE_TRANSACTION_MODEL_FILE
  • UPDATE_ASE_FEATURE_TIME_WHEN_CHANGED
  • UPDATE_ASSIGNMENT_GROUP_FEATURE_TIME_WHEN_CHANGED
  • UPDATE_CHIP_EDITOR_FEATURE_TIME_WHEN_CHANGED
  • UPDATE_CONFLICTING
  • UPDATE_ECMC_FEATURE_TIME_WHEN_CHANGED
  • UPDATE_FLOORPLAN_EDITOR_FEATURE_TIME_WHEN_CHANGED
  • UPDATE_MODE_INTERNAL_FLASH
  • UPDATE_MODE_TITAN
  • UPDATE_MODE_YEAGER
  • UPDATE_PAT_FEATURE_TIME_WHEN_CHANGED
  • UPDATE_PIN_PLANNER_FEATURE_TIME_WHEN_CHANGED
  • UPDATE_SIM_FEATURE_TIME_WHEN_CHANGED
  • UPDATE_SSN_FEATURE_TIME_WHEN_CHANGED
  • UPDATE_TAN_FEATURE_TIME_WHEN_CHANGED
  • USE_ADVANCED_DETAILED_LAB_LEGALITY
  • USE_AS_PROGRAMMING_PIN
  • USE_AS_REGULAR_IO
  • USE_CAP
  • USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT
  • USE_CHECKSUM_AS_USERCODE
  • USE_CHECKSUM_AS_USERCODE_MAX7000
  • USE_CLK_FOR_VIRTUAL_PIN
  • USE_CLOCK
  • USE_CLOCK_SETTINGS
  • USE_COMPILER_SETTINGS
  • USE_CONF_DONE
  • USE_CONFIGURATION_DEVICE
  • USE_CONFIGURATION_DEVICE_NAME_APEX20K
  • USE_CONFIGURATION_DEVICE_NAME_ARMSTRONG
  • USE_CONFIGURATION_DEVICE_NAME_CUDA
  • USE_CONFIGURATION_DEVICE_NAME_CYCLONE
  • USE_CONFIGURATION_DEVICE_NAME_DALI
  • USE_CONFIGURATION_DEVICE_NAME_EXCALIBUR
  • USE_CONFIGURATION_DEVICE_NAME_FLEX10K
  • USE_CONFIGURATION_DEVICE_NAME_FLEX6K
  • USE_CONFIGURATION_DEVICE_NAME
  • USE_CONFIGURATION_DEVICE_NAME_YEAGER
  • USE_CONFIGURATION_DEVICE_OPTIONS
  • USE_C_PREPROCESSOR_FOR_GNU_ASM_FILES
  • USE_CVP_CONFDONE
  • USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN
  • USE_DMF
  • USE_GENERATED_PHYSICAL_CONSTRAINTS
  • USE_GLOBAL_SETTINGS
  • USE_HIGH_SPEED_ADDER
  • USE_INIT_DONE
  • USE_LOCAL_APEX20K
  • USE_LOCAL_FLEX6K
  • USE_LOCAL
  • USE_LOGIC_ANALYZER_INTERFACE_FILE
  • USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING
  • USE_LPM_FOR_AHDL_OPERATORS
  • USE_MULTITAP_FILE
  • USE_NEW_TEXT_REPORT_TABLE_FORMAT
  • USE_PWRMGT_ALERT
  • USE_PWRMGT_SCL
  • USE_PWRMGT_SDA
  • USER_CUSTOM
  • USER_ENABLED
  • USER_ENCODED
  • USER_FILES_NEW_EXTRACTOR
  • USER_JTAG_CODE_APEX20K
  • USER_JTAG_CODE_DALI
  • USER_JTAG_CODE_FLEX10K
  • USER_JTAG_CODE_FLEX6K
  • USER_JTAG_CODE_MAX7000
  • USER_JTAG_CODE_MAX7000S
  • USER_JTAG_CODE_YEAGER
  • USER_LIBRARIES
  • USER_MESSAGE
  • USER_START_UP_CLOCK
  • USER_VALUE
  • USE_SEU_ERROR
  • USE_SIGNALTAP_FILE
  • USE_TCL_PROC
  • USE_TIMEQUEST_TIMING_ANALYZER
  • USE_TIMING_DRIVEN_COMPILATION
  • USE_VPACK
  • USE_VPR
  • USE_VQM_INSTEAD_OF_SOURCE
  • V0P00
  • V0P58
  • V0P64
  • V0P67
  • V0P70
  • V0P75
  • V0P81
  • V0P86
  • V0P87
  • V0P93
  • V0P96
  • V1P00
  • V1P04
  • V1P13
  • V1P22
  • V1P30
  • V1P39
  • VALUE_IS_NODE
  • VARIABLE_VALUE_CANNOT_BE_CHANGED
  • VCCAUX_SHARED_USER_VOLTAGE
  • VCCELA_0P85V
  • VCCELA_0P9V
  • VCCELA_1P0V
  • VCCELA_1P1V
  • VCCER
  • VCCIO_45
  • VCCIO_50
  • VCCIO_55
  • VCCIO_65
  • VCCIO_70
  • VCCIO_75
  • VCCIO_CURRENT_1PT8V
  • VCCIO_CURRENT_2PT5V
  • VCCIO_CURRENT_GTL
  • VCCIO_CURRENT_GTL_PLUS
  • VCCIO_CURRENT_LVCMOS
  • VCCIO_CURRENT_LVTTL
  • VCCIO_CURRENT_PCI
  • VCCIO_CURRENT_SSTL2_CLASS1
  • VCCIO_CURRENT_SSTL2_CLASS2
  • VCCIO_CURRENT_SSTL3_CLASS1
  • VCCIO_CURRENT_SSTL3_CLASS2
  • VCCIO_IOBANK1_MAX7000B
  • VCCIO_IOBANK2_MAX7000B
  • VCCIOREF_HPS_USER_VOLTAGE
  • VCCPD_VOLTAGE
  • VCCRSTCLK_HPS_USER_VOLTAGE
  • VCC_SETTING0
  • VCC_SETTING1
  • VCC_SETTING2
  • VCC_SETTING3
  • VCD_FILE
  • VCM_CURRENT_1
  • VCM_CURRENT_2
  • VCM_CURRENT_3
  • VCM_CURRENT_DEFAULT
  • VCM_SETTING_00
  • VCM_SETTING_01
  • VCM_SETTING_02
  • VCM_SETTING_03
  • VCM_SETTING_04
  • VCM_SETTING_05
  • VCM_SETTING_06
  • VCM_SETTING_07
  • VCM_SETTING_08
  • VCM_SETTING_09
  • VCM_SETTING_10
  • VCM_SETTING_11
  • VCM_SETTING_12
  • VCM_SETTING_13
  • VCM_SETTING_14
  • VCM_SETTING_15
  • VECTOR_COMPARE_TRIGGER_MODE
  • VECTOR_INPUT_SOURCE
  • VECTOR_OUTPUT_DESTINATION
  • VECTOR_SOURCE_FILE
  • VECTOR_TABLE_OUTPUT_FILE
  • VECTOR_TEXT_FILE
  • VER_COMPATIBLE_DB_DIR
  • VERILOG_1995
  • VERILOG_2001
  • VERILOG_CONSTANT_LOOP_LIMIT
  • VERILOG_CU_MODE
  • VERILOG_INCLUDE_FILE
  • VERILOG_INPUT_VERSION
  • VERILOG_LMF_FILE
  • VERILOG_MACRO
  • VERILOG_NON_CONSTANT_LOOP_LIMIT
  • VERILOG_OUTPUT_FILE
  • VERILOG_SHOW_LMF_MAPPING_MESSAGES
  • VERILOG_SHOW_LMF_MAPPING_MSGS
  • VERILOG_TEST_BENCH_FILE
  • VERILOG_VH_FILE
  • VHDL_1987
  • VHDL_1993
  • VHDL_2008
  • VHDL87
  • VHDL93
  • VHDL_FILE
  • VHDL_INPUT_LIBRARY
  • VHDL_INPUT_VERSION
  • VHDL_LMF_FILE
  • VHDL_OUTPUT_FILE
  • VHDL_SHOW_LMF_MAPPING_MESSAGES
  • VHDL_SHOW_LMF_MAPPING_MSGS
  • VHDL_TEST_BENCH_FILE
  • VID_OPERATION_MODE
  • VIRTUAL_CLOCK_REFERENCE
  • VIRTUAL_IO_DRIVES_CLOCK_PORT
  • VOLT_0MV
  • VOLT_0P35V
  • VOLT_0P50V
  • VOLT_0P55V
  • VOLT_0P60V
  • VOLT_0P65V
  • VOLT_0P70V
  • VOLT_0P75V
  • VOLT_0P80V
  • VPACK_ONLY
  • VQM_FILE
  • VREF_VOLT_0
  • VREF_VOLT_0P5
  • VREF_VOLT_0P75
  • VREF_VOLT_1P0
  • VTT_0P35V
  • VTT_0P50V
  • VTT_0P55V
  • VTT_0P60V
  • VTT_0P65V
  • VTT_0P70V
  • VTT_0P75V
  • VTT_0P80V
  • VTT_PDN_STRONG
  • VTT_PDN_WEAK
  • VTT_PUP_STRONG
  • VTT_PUP_WEAK
  • VTT_VCMOFF0
  • VTT_VCMOFF1
  • VTT_VCMOFF2
  • VTT_VCMOFF3
  • VTT_VCMOFF4
  • VTT_VCMOFF5
  • VTT_VCMOFF6
  • VTT_VCMOFF7
  • WAIT_1_MS
  • WAIT_2_MS
  • WAIT_4_MS
  • WAIT_50_MS
  • WAIT_8_MS
  • WEAK_PULL_UP
  • WEAK_PULL_UP_RESISTOR
  • WHEN_TSU_AND_TPD_CONSTRAINTS_PERMIT
  • WIDTH_18_BIT_MULTIPLIERS
  • WIDTH_3
  • WRITE
  • X1_PLL_FREQUENCY
  • XACTO_INCREMENTAL_COMPILE_ASSIGNMENT
  • XACTO_INCREMENTAL_COMPILE_FILE
  • XACTO_REGION
  • XACTO_VQM_FILES
  • XAUI_3125
  • XAUI
  • XCVR_A10_CDR_PLL_ANALOG_MODE
  • XCVR_A10_CDR_PLL_POWER_MODE
  • XCVR_A10_CDR_PLL_REQUIRES_GT_CAPABLE_CHANNEL
  • XCVR_A10_CDR_PLL_UC_RO_CAL
  • XCVR_A10_CMU_FPLL_ANALOG_MODE
  • XCVR_A10_CMU_FPLL_PLL_DPRIO_CLK_VREG_BOOST
  • XCVR_A10_CMU_FPLL_PLL_DPRIO_FPLL_VREG1_BOOST
  • XCVR_A10_CMU_FPLL_PLL_DPRIO_FPLL_VREG_BOOST
  • XCVR_A10_CMU_FPLL_PLL_DPRIO_STATUS_SELECT
  • XCVR_A10_CMU_FPLL_POWER_MODE
  • XCVR_A10_LC_PLL_ANALOG_MODE
  • XCVR_A10_LC_PLL_POWER_MODE
  • XCVR_A10_PM_UC_CLKDIV_SEL
  • XCVR_A10_PM_UC_CLKSEL_CORE
  • XCVR_A10_PM_UC_CLKSEL_OSC
  • XCVR_A10_REFCLK_TERM_TRISTATE
  • XCVR_A10_RX_ADAPT_DFE_CONTROL_SEL
  • XCVR_A10_RX_ADAPT_DFE_SEL
  • XCVR_A10_RX_ADAPT_VGA_SEL
  • XCVR_A10_RX_ADAPT_VREF_SEL
  • XCVR_A10_RX_ADP_CTLE_ACGAIN_4S
  • XCVR_A10_RX_ADP_CTLE_EQZ_1S_SEL
  • XCVR_A10_RX_ADP_DFE_FLTAP_POSITION
  • XCVR_A10_RX_ADP_DFE_FXTAP10
  • XCVR_A10_RX_ADP_DFE_FXTAP10_SGN
  • XCVR_A10_RX_ADP_DFE_FXTAP11
  • XCVR_A10_RX_ADP_DFE_FXTAP11_SGN
  • XCVR_A10_RX_ADP_DFE_FXTAP1
  • XCVR_A10_RX_ADP_DFE_FXTAP2
  • XCVR_A10_RX_ADP_DFE_FXTAP2_SGN
  • XCVR_A10_RX_ADP_DFE_FXTAP3
  • XCVR_A10_RX_ADP_DFE_FXTAP3_SGN
  • XCVR_A10_RX_ADP_DFE_FXTAP4
  • XCVR_A10_RX_ADP_DFE_FXTAP4_SGN
  • XCVR_A10_RX_ADP_DFE_FXTAP5
  • XCVR_A10_RX_ADP_DFE_FXTAP5_SGN
  • XCVR_A10_RX_ADP_DFE_FXTAP6
  • XCVR_A10_RX_ADP_DFE_FXTAP6_SGN
  • XCVR_A10_RX_ADP_DFE_FXTAP7
  • XCVR_A10_RX_ADP_DFE_FXTAP7_SGN
  • XCVR_A10_RX_ADP_DFE_FXTAP8
  • XCVR_A10_RX_ADP_DFE_FXTAP8_SGN
  • XCVR_A10_RX_ADP_DFE_FXTAP9
  • XCVR_A10_RX_ADP_DFE_FXTAP9_SGN
  • XCVR_A10_RX_ADP_LFEQ_FB_SEL
  • XCVR_A10_RX_ADP_ONETIME_DFE
  • XCVR_A10_RX_ADP_VGA_SEL
  • XCVR_A10_RX_ADP_VREF_SEL
  • XCVR_A10_RX_BYPASS_EQZ_STAGES_234
  • XCVR_A10_RX_EQ_BW_SEL
  • XCVR_A10_RX_EQ_DC_GAIN_TRIM
  • XCVR_A10_RX_INPUT_VCM_SEL
  • XCVR_A10_RX_LINK
  • XCVR_A10_RX_OFFSET_CANCELLATION_CTRL
  • XCVR_A10_RX_ONE_STAGE_ENABLE
  • XCVR_A10_RX_POWER_MODE
  • XCVR_A10_RX_QPI_ENABLE
  • XCVR_A10_RX_RX_SEL_BIAS_SOURCE
  • XCVR_A10_RX_SD_OUTPUT_OFF
  • XCVR_A10_RX_SD_OUTPUT_ON
  • XCVR_A10_RX_SD_THRESHOLD
  • XCVR_A10_RX_TERM_SEL
  • XCVR_A10_RX_TERM_TRI_ENABLE
  • XCVR_A10_RX_UC_RX_DFE_CAL
  • XCVR_A10_RX_VCCELA_SUPPLY_VOLTAGE
  • XCVR_A10_RX_VCM_CURRENT_ADD
  • XCVR_A10_RX_VCM_SEL
  • XCVR_A10_RX_XRX_PATH_ANALOG_MODE
  • XCVR_A10_TX_COMPENSATION_EN
  • XCVR_A10_TX_DCD_DETECTION_EN
  • XCVR_A10_TX_DPRIO_CGB_VREG_BOOST
  • XCVR_A10_TX_LINK
  • XCVR_A10_TX_LOW_POWER_EN
  • XCVR_A10_TX_POWER_MODE
  • XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP
  • XCVR_A10_TX_PRE_EMP_SIGN_2ND_POST_TAP
  • XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_1T
  • XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_2T
  • XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP
  • XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP
  • XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T
  • XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T
  • XCVR_A10_TX_RES_CAL_LOCAL
  • XCVR_A10_TX_RX_DET
  • XCVR_A10_TX_RX_DET_OUTPUT_SEL
  • XCVR_A10_TX_RX_DET_PDB
  • XCVR_A10_TX_SLEW_RATE_CTRL
  • XCVR_A10_TX_TERM_CODE
  • XCVR_A10_TX_TERM_SEL
  • XCVR_A10_TX_UC_DCD_CAL
  • XCVR_A10_TX_UC_GEN3
  • XCVR_A10_TX_UC_GEN4
  • XCVR_A10_TX_UC_SKEW_CAL
  • XCVR_A10_TX_UC_TXVOD_CAL_CONT
  • XCVR_A10_TX_UC_TXVOD_CAL
  • XCVR_A10_TX_UC_VCC_SETTING
  • XCVR_A10_TX_USER_FIR_COEFF_CTRL_SEL
  • XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL
  • XCVR_A10_TX_XTX_PATH_ANALOG_MODE
  • XCVR_ANALOG_SETTINGS_PROTOCOL
  • XCVR_FAST_LOCK_MODE
  • XCVR_GT_IO_PIN_TERMINATION
  • XCVR_GT_RX_COMMON_MODE_VOLTAGE
  • XCVR_GT_RX_CTLE
  • XCVR_GT_RX_DC_GAIN
  • XCVR_GT_RX_FORCE_VCO_CONST
  • XCVR_GT_TX_COMMON_MODE_VOLTAGE
  • XCVR_GT_TX_PRE_EMP_1ST_POST_TAP
  • XCVR_GT_TX_PRE_EMP_INV_PRE_TAP
  • XCVR_GT_TX_PRE_EMP_PRE_TAP
  • XCVR_GT_TX_VOD_MAIN_TAP
  • XCVR_IO_PIN_TERMINATION
  • XCVR_RECONFIG_AVMM_GROUP
  • XCVR_RECONFIG_GROUP
  • XCVR_REFCLK_PIN_TERMINATION
  • XCVR_RX_ACGAIN_A
  • XCVR_RX_ACGAIN_V
  • XCVR_RX_ADCE_HSF_HFBW
  • XCVR_RX_ADCE_RGEN_BW
  • XCVR_RX_ADCE_RGEN_MODE
  • XCVR_RX_BYPASS_EQ_STAGES_234
  • XCVR_RX_COMMON_MODE_VOLTAGE
  • XCVR_RX_DC_GAIN
  • XCVR_RX_DFE_PI_BW
  • XCVR_RX_ENABLE_LINEAR_EQUALIZER_PCIEMODE
  • XCVR_RX_EQ_BW_SEL
  • XCVR_RX_EYEQ_BANDWIDTH
  • XCVR_RX_INPUT_VCM_SEL
  • XCVR_RX_LINEAR_EQUALIZER_CONTROL
  • XCVR_RX_PMOS_GAIN_PEAK
  • XCVR_RX_QPI_ENABLE
  • XCVR_RX_SD_ENABLE
  • XCVR_RX_SD_OFF
  • XCVR_RX_SD_ON
  • XCVR_RX_SD_THRESHOLD
  • XCVR_RX_SEL_BIAS_SOURCE
  • XCVR_RX_SEL_HALF_BW
  • XCVR_RX_VCM_DRIVE_STRENGTH
  • XCVR_TX_COMMON_MODE_VOLTAGE
  • XCVR_TX_DRIVER_RESOLUTION_CTRL
  • XCVR_TX_LOCAL_IB_CTL
  • XCVR_TX_PLL_RECONFIG_GROUP
  • XCVR_TX_PRE_EMP_1ST_POST_TAP
  • XCVR_TX_PRE_EMP_2ND_POST_TAP
  • XCVR_TX_PRE_EMP_2ND_POST_TAP_USER
  • XCVR_TX_PRE_EMP_INV_2ND_TAP
  • XCVR_TX_PRE_EMP_INV_PRE_TAP
  • XCVR_TX_PRE_EMP_PRE_TAP
  • XCVR_TX_PRE_EMP_PRE_TAP_USER
  • XCVR_TX_QPI_EN
  • XCVR_TX_RX_DET_ENABLE
  • XCVR_TX_RX_DET_MODE
  • XCVR_TX_RX_DET_OUTPUT_SEL
  • XCVR_TX_SLEW_RATE_CTRL
  • XCVR_TX_SWING_BOOST
  • XCVR_TX_VCM_CTRL_SRC
  • XCVR_TX_VCM_DRIVE_STRENGTH
  • XCVR_TX_VOD_BOOST
  • XCVR_TX_VOD
  • XCVR_TX_VOD_PRE_EMP_CTRL_SRC
  • XCVR_VCCA_VOLTAGE
  • XCVR_VCCR_VCCT_VOLTAGE
  • X_ON_VIOLATION_OPTION
  • XOR_SYNTHESIS
  • XR_AUTO_SIZE
  • XR_CORE_ONLY
  • XR_EXCLUDE
  • XR_HEIGHT
  • XR_MEMBER_OF
  • XR_MEMBER_OPTION
  • XR_MEMBER_RESOURCE_EXCLUDE
  • XR_MEMBER_STATE
  • XR_NODE_LOCATION
  • XR_ORIGIN
  • XR_PARENT
  • XR_PATH_EXCLUDE
  • XR_PATH_INCLUDE
  • XR_PRIORITY
  • XR_RESERVE
  • XR_ROOT_REGION
  • XR_ROUGH
  • XR_SOFT
  • XR_STATE
  • XR_WIDTH
  • XSTL_INPUT_ALLOW_SE_BUFFER
  • YEAGER_CONFIGURATION_DEVICE
  • YEAGER_CRC_ERROR_CHECKING
  • YEAGER_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
  • YEAGER_DEVICE_IO_STANDARD
  • YEAGER_OCT_AND_IMPEDANCE_MATCHING
  • YEAGER_OPTIMIZATION_TECHNIQUE
  • YEAGER_TECHNOLOGY_MAPPER
  • YEAGER_UPDATE_MODE
  • ZBT_OE_FALLING_EDGE_DELAY
  • ZERO_DELAY_BUFFER
  • ZIP_VECTOR_CHANNEL_FILE
  • ZIP_VECTOR_WAVEFORM_FILE
  • ZL8800
  • ZL9117M
]]> https://billauer.se/blog/2021/10/quartus-qsf-list/feed/ 0 Reverse engineering Cyclone 10 transceiver’s attributes https://billauer.se/blog/2021/10/arria-cyclone-10-signal-detect-oob/ https://billauer.se/blog/2021/10/arria-cyclone-10-signal-detect-oob/#comments Thu, 14 Oct 2021 15:01:55 +0000 eli https://billauer.se/blog/?p=6415 Introduction

This post summarizes some scattered findings I made while trying to make a Cyclone 10′s signal detect feature work properly for detecting a SuperSpeed USB LFPS signal. As it turned out, Cyclone 10′s transceiver isn’t capable of this, as explained below.

But since the documentation on this issue was lacking, I resorted to reverse engineering Quartus in the attempt to find a solution. So this post is a bit about the transceiver and more about the reverse engineering efforts, which might be relevant in completely different contexts.

I should mention that everything on this page relates to Cyclone 10, even though the output from the tools keep naming different logic elements with “a10″, as if it was Arria 10. Clearly, the transceivers for the two FPGA families are the same.

Software: Quartus Pro 17.1 running on a 64-bit Linux machine (Mint 19).

Cyclone 10′s signal detect is rubbish

The purpose of the signal detector is to tell whether the differential wires are in an electrical idle state, or if there’s some activity on these. This is used by several protocols to wake up the link partners from a low power state: A PCIe link can be awaken by an upstream facing link partner (typically the device waking up the host) from a L2 state by virtue of a beacon, which consists of toggling the polarity at a rate of 30 kHz — 500 MHz. A SATA link can be awaken by one of the link partners transmitting a special data pattern. The USB 3.x protocol also uses out-of-band (OOB) signals if this sort, for various purposes, and calls them LFPS (Low Frequency Pulse Signaling). The toggling rate is defined between 10 — 50 MHz.

The first, relatively simple obstacle, was to turn on the signal detector. The Cyclone 10 GX Transceiver PHY User Guide says in Table 67, regarding rx_std_signaldetect:

When enabled, the signal threshold detection circuitry senses whether the signal level present at the RX input buffer is above the signal detect threshold voltage. You can specify the signal detect threshold using a Quartus Prime Settings File (.qsf) assignment. This signal is required for the PCI Express, SATA and SAS protocols.

Similar notes are made in other places in that guide. However it doesn’t mention that if the transceiver is configured in “basic” mode (as opposed to SATA mode, as well as PCIe mode, I suppose), rx_std_signaldetect is stuck on logic ’1′, so enabling this signal alone isn’t enough.

But the real problem is that the signal detector is probably not good for anything but detecting SATA’s OOB: When I selected SATA mode, I did get some response on rx_std_signaldetect, but it was clearly not detecting the LFPS activity in a useful way. Unlike Cyclone V’s signal detector, Cyclone 10′s detector barely responded at all to a 31.25 MHz LFPS, and the detections occurred with pretty arbitrary timing, often with a pulse when the LFPS signal stopped, and some other random pulses as the wires went into electrical idle. In short, far from the desired assertion when the LFPS signals starts and deassertion when it stops.

Things got better as the toggling frequency increased, and around 125 MHz the assertion of the signal detect was steadily aligned with the onset of the LFPS toggling, however the deassertion was often delayed after the LFPS stopped. So even if the LFPS signal could be guaranteed to be at this frequency (it can’t, as it’s produced by the USB 3.x link partner, and 125 MHz is above maximum) the issue with the deassertion makes it impossible to use it with LFPS, which is extremely sensitive to the timing of onset and release of the toggling.

In fact, it’s probably useless for PCIe as well, as a PCIe beacon is allowed between 30 kHz – 500 MHz. This might explain why recent version of user guides for PCIe block for Cyclone V, Arria V, Cyclone 10 and Arria 10, had this sentence added:

These IP cores also do not support the in-band beacon or sideband WAKE# signal, which are mechanisms to signal a wake-up event to the upstream device.

The problem was probably not spotted for a while because the beacon is rarely used: The PCIe spec utilizes beacon transmission only from a device towards the host (upstream) for the sake of bringing up the link from a low power state. So signal detection by an FPGA for the sake of PCIe is only required when the FPGA acts as a host, and low-power modes are supported. In short, practically never.

What’s left? SATA. That will probably work, because the differential wires toggle rapidly, and it doesn’t matter so much if the detection is a bit off-beat.

So I resorted to detecting the LFPS bursts directly from uncoded received data, rather than using the signal detect feature. The rest of this post relates to my attempts before I gave up.

The options are limited

Quartus is going a long way to be “helpful” by verifying that the parameter assignments make sense with regards to the intended protocol (e.g. SATA, PCIe etc), as reflected by the “prot_mode” parameter. This often means that the fitter throws an error when one tries to alter a parameter from its default. It’s like someone said nope, if you’re using the transceiver for SATA, these and these are the correct analog parameters for the PMA, and if you try otherwise, the fitter will kick your bottom for your own protection.

Or maybe it’s a gentle way of telling us users not to try anything but the protocols for which the transceiver is directly intended for.

The fitter may also ignore assignments because they were assinged an unrelated entity (e.g. to gtx_tx instead of the positive-signal’s name, gtx_txp). So be always sure to look in the fitter report’s “Ignored Assignments” section.

One could speculate that this nanny-like behavior can be disabled by setting one of the pma_*_sup_mode parameters to “engineering_mode” rather than the default “user_mode”, but see below on this.

QSF

I expected to solve this by turning the parameters of the signal detector like I’ve previously done with Cyclone V: By virtue of assignments of QSF file.

So here’s the catch: The User Guide also says that the signal detect threshold can be set by virtue of .qsf assignments, but none such are documented in the it (as of the version for Quartus 20.1), and the Assignment Editor offers no parameter of this sort.

For Cyclone V, it’s documented in the V-Series Transceiver PHY IP Core User Guide around page 20-31, and there are recommended values on this page. My anecdotal experiments seem to indicate that assigning XCVR_* attributes (without the C10 part) to a Cyclone 10 transceiver is accepted however ignored by Quartus. In other words, trying to use Cyclone-V QSF assignments won’t cut.

So let’s start the guesswork on the names of the QSF parameters.

Hint source I: The fitter report

The fitter report has a section called “Receiver Channel”, which shows the attributes of the transceiver’s components as applied de-facto. Among others, there’s a part saying

;             -- Name                                           ; frontend_ins|xcvr_inst|xcvr_native_a10_0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_sd.inst_twentynm_hssi_pma_rx_sd                               ;
;             -- Location                                       ; HSSIPMARXSD_1D4                                                                                                                                                                                                                                                       ;
;         -- Advanced Parameters                                ;                                                                                                                                                                                                                                                                       ;
;             -- link                                           ; mr                                                                                                                                                                                                                                                                    ;
;             -- power_mode                                     ; mid_power                                                                                                                                                                                                                                                             ;
;             -- prot_mode                                      ; sata_rx                                                                                                                                                                                                                                                               ;
;             -- sd_output_off                                  ; 1                                                                                                                                                                                                                                                                     ;
;             -- sd_output_on                                   ; 1                                                                                                                                                                                                                                                                     ;
;             -- sd_pdb                                         ; sd_on                                                                                                                                                                                                                                                                 ;
;             -- sd_threshold                                   ; sdlv_3

It’s actually recommended to go through this part in the fitter report in any case, to make sure it was set up as desired.

But this part allows guessing the names of the parameters for the QSF file. For example, the following assignments are perfectly legal (and match the setting shown above):

set_instance_assignment -name XCVR_C10_RX_SD_OUTPUT_OFF 1 -to gtx_rxp
set_instance_assignment -name XCVR_C10_RX_SD_OUTPUT_ON 1 -to gtx_rxp
set_instance_assignment -name XCVR_C10_RX_SD_THRESHOLD SDLV_3 -to gtx_rxp

It doesn’t take a cyber hacker to see the connection between the QSF parameter names and those appearing in the report. This works for some parameters, and not for other. But this is the easiest way to guess parameter names.

Hint source II: Read the sources

But what’s the allowed values that can be assigned to these parameters? Hints on that can be obtained from the System Verilog files generated for the IP, in particular the one named xcvr_xcvr_native_a10_0_altera_xcvr_native_a10_171_ev4uzpa.sv (the “ev4uzpa” suffix varies), which has a section going:

parameter pma_rx_sd_prot_mode = "basic_rx",//basic_kr_rx basic_rx cpri_rx gpon_rx pcie_gen1_rx pcie_gen2_rx pcie_gen3_rx pcie_gen4_rx qpi_rx sata_rx unused
parameter pma_rx_sd_sd_output_off = 1,//0:28
parameter pma_rx_sd_sd_output_on = 1,//0:15
parameter pma_rx_sd_sd_pdb = "sd_off",//sd_off sd_on
parameter pma_rx_sd_sd_threshold = 3,//0:15
parameter pma_rx_sd_sup_mode = "user_mode",//engineering_mode user_mode

Note the comments, saying which values are allowed for each parameter. On a good day, staying within these value ranges makes the tools accept the assignments, and on an even better day, the fitter won’t throw an error because it considers the values unsuitable.

It’s worth taking a look on the other modules as well, even though they’re likely to have the same comments.

As far as I’ve seen, these parameters are set by the toplevel module for the transceiver IP. QSF assignments, if present, override the former.

Hint source III: What do these assignments mean?

For this I suggest looking at ip/altera/alt_xcvr/alt_xcvr_core/nd/doc/PMA_RegMap.csv (or similar file name) under the root directory of the Quartus installation. Yes, we’re digging in Quartus’ backyard now. I found these files by searching for strings in all files of the Quartus installation. Reverse engineering, after all.

In fact, I’m not sure if this is the correct file to look at, or maybe CR2_PMA_RegMap.csv or whatever. Neither do I know what they mean exactly. It’s however quite evident that these CSV files (opens with your favorite spreadsheet application) were intended to document the register space of the PMA. But the table that shows has a “Attribute Description” column with a few meaningful words on each attribute as well as a column named “Attribute Encoding”, which may happen to be the value to use in a QSF assignment (may and may not work).

There’s also an official register map from Intel available for download, named c10-registermap-official.xlsx, which apparently contains complimentary information. But it’s not possible to deduce QSF names from this file.

Hint source IV: What assignments are legal, then?

I mentioned earlier that the fitter rejects certain value assignment because they apparently don’t make sense. The rules seem to be written as a Tcl script in ip/altera/alt_xcvr/alt_xcvr_core/nd/tcl/ct2_pma_rx_sd_simple.tcl (and similar). Once again, under the Quartus installation root. And yet once again, sometimes this helps, and sometimes it doesn’t.

Hint source V: The names of the QSF paramaters

Up to this point, the names of the parameters to assign in the QSF file were a matter of speculation, based upon similar names in other contexts.

It’s possible to harvest all possible names by searching for strings in one of Quartus’ installed binaries, as shown on this post for non-Pro Quartus 17.1, and this post for Quartus Pro 19.2.

For a complete list of allowed QSF assignment that relate to Cyclone 10 transceivers (or so I groundlessly believe), search for strings in libdb_acf.so, e.g.

$ strings ./quartus/linux64/libdb_acf.so | grep XCVR_C10 | sort
XCVR_C10_CDR_PLL_ANALOG_MODE
XCVR_C10_CDR_PLL_POWER_MODE
XCVR_C10_CDR_PLL_REQUIRES_GT_CAPABLE_CHANNEL
XCVR_C10_CDR_PLL_UC_RO_CAL
XCVR_C10_CMU_FPLL_ANALOG_MODE
XCVR_C10_CMU_FPLL_PLL_DPRIO_CLK_VREG_BOOST
XCVR_C10_CMU_FPLL_PLL_DPRIO_FPLL_VREG1_BOOST
XCVR_C10_CMU_FPLL_PLL_DPRIO_FPLL_VREG_BOOST
XCVR_C10_CMU_FPLL_PLL_DPRIO_STATUS_SELECT
XCVR_C10_CMU_FPLL_POWER_MODE
XCVR_C10_LC_PLL_ANALOG_MODE
XCVR_C10_LC_PLL_POWER_MODE
XCVR_C10_PM_UC_CLKDIV_SEL
XCVR_C10_PM_UC_CLKSEL_CORE
XCVR_C10_PM_UC_CLKSEL_OSC
XCVR_C10_REFCLK_TERM_TRISTATE
XCVR_C10_RX_ADAPT_DFE_CONTROL_SEL
XCVR_C10_RX_ADAPT_DFE_SEL
XCVR_C10_RX_ADAPT_VGA_SEL
XCVR_C10_RX_ADAPT_VREF_SEL
XCVR_C10_RX_ADP_CTLE_ACGAIN_4S
XCVR_C10_RX_ADP_CTLE_EQZ_1S_SEL
XCVR_C10_RX_ADP_DFE_FLTAP_POSITION
XCVR_C10_RX_ADP_DFE_FXTAP1
XCVR_C10_RX_ADP_DFE_FXTAP10
XCVR_C10_RX_ADP_DFE_FXTAP10_SGN
XCVR_C10_RX_ADP_DFE_FXTAP11
XCVR_C10_RX_ADP_DFE_FXTAP11_SGN
XCVR_C10_RX_ADP_DFE_FXTAP2
XCVR_C10_RX_ADP_DFE_FXTAP2_SGN
XCVR_C10_RX_ADP_DFE_FXTAP3
XCVR_C10_RX_ADP_DFE_FXTAP3_SGN
XCVR_C10_RX_ADP_DFE_FXTAP4
XCVR_C10_RX_ADP_DFE_FXTAP4_SGN
XCVR_C10_RX_ADP_DFE_FXTAP5
XCVR_C10_RX_ADP_DFE_FXTAP5_SGN
XCVR_C10_RX_ADP_DFE_FXTAP6
XCVR_C10_RX_ADP_DFE_FXTAP6_SGN
XCVR_C10_RX_ADP_DFE_FXTAP7
XCVR_C10_RX_ADP_DFE_FXTAP7_SGN
XCVR_C10_RX_ADP_DFE_FXTAP8
XCVR_C10_RX_ADP_DFE_FXTAP8_SGN
XCVR_C10_RX_ADP_DFE_FXTAP9
XCVR_C10_RX_ADP_DFE_FXTAP9_SGN
XCVR_C10_RX_ADP_LFEQ_FB_SEL
XCVR_C10_RX_ADP_ONETIME_DFE
XCVR_C10_RX_ADP_VGA_SEL
XCVR_C10_RX_ADP_VREF_SEL
XCVR_C10_RX_BYPASS_EQZ_STAGES_234
XCVR_C10_RX_EQ_BW_SEL
XCVR_C10_RX_EQ_DC_GAIN_TRIM
XCVR_C10_RX_INPUT_VCM_SEL
XCVR_C10_RX_LINK
XCVR_C10_RX_OFFSET_CANCELLATION_CTRL
XCVR_C10_RX_ONE_STAGE_ENABLE
XCVR_C10_RX_POWER_MODE
XCVR_C10_RX_QPI_ENABLE
XCVR_C10_RX_RX_SEL_BIAS_SOURCE
XCVR_C10_RX_SD_OUTPUT_OFF
XCVR_C10_RX_SD_OUTPUT_ON
XCVR_C10_RX_SD_THRESHOLD
XCVR_C10_RX_TERM_SEL
XCVR_C10_RX_TERM_TRI_ENABLE
XCVR_C10_RX_UC_RX_DFE_CAL
XCVR_C10_RX_VCCELA_SUPPLY_VOLTAGE
XCVR_C10_RX_VCM_CURRENT_ADD
XCVR_C10_RX_VCM_SEL
XCVR_C10_RX_XRX_PATH_ANALOG_MODE
XCVR_C10_TX_COMPENSATION_EN
XCVR_C10_TX_DCD_DETECTION_EN
XCVR_C10_TX_DPRIO_CGB_VREG_BOOST
XCVR_C10_TX_LINK
XCVR_C10_TX_LOW_POWER_EN
XCVR_C10_TX_POWER_MODE
XCVR_C10_TX_PRE_EMP_SIGN_1ST_POST_TAP
XCVR_C10_TX_PRE_EMP_SIGN_2ND_POST_TAP
XCVR_C10_TX_PRE_EMP_SIGN_PRE_TAP_1T
XCVR_C10_TX_PRE_EMP_SIGN_PRE_TAP_2T
XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP
XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP
XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T
XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T
XCVR_C10_TX_RES_CAL_LOCAL
XCVR_C10_TX_RX_DET
XCVR_C10_TX_RX_DET_OUTPUT_SEL
XCVR_C10_TX_RX_DET_PDB
XCVR_C10_TX_SLEW_RATE_CTRL
XCVR_C10_TX_TERM_CODE
XCVR_C10_TX_TERM_SEL
XCVR_C10_TX_UC_DCD_CAL
XCVR_C10_TX_UC_GEN3
XCVR_C10_TX_UC_GEN4
XCVR_C10_TX_UC_SKEW_CAL
XCVR_C10_TX_UC_TXVOD_CAL
XCVR_C10_TX_UC_TXVOD_CAL_CONT
XCVR_C10_TX_UC_VCC_SETTING
XCVR_C10_TX_USER_FIR_COEFF_CTRL_SEL
XCVR_C10_TX_VOD_OUTPUT_SWING_CTRL
XCVR_C10_TX_XTX_PATH_ANALOG_MODE

So yes, now we’re looking for strings in a binary file.

And yet, all this doesn’t necessarily help

With all these hints, there’s still some pure guesswork. For example, I tried

set_instance_assignment -name XCVR_C10_RX_SD_OUTPUT_ON 3 -to gtx_rxp

and the fitter gave me

    Error (15744): The settings must match one or more of these conditions:
    Error (15744): ( sup_mode == ENGINEERING_MODE ) OR ( prot_mode != SATA_RX ) OR ( sd_output_on == DATA_PULSE_6 )
    Error (15744): But the following assignments violate the above conditions:
    Error (15744): sup_mode = USER_MODE
    Error (15744): prot_mode = SATA_RX
    Error (15744): sd_output_on = DATA_PULSE_10 -- Set by Pin Assignment "XCVR_A10_RX_SD_OUTPUT_ON" (QSF Name "XCVR_A10_RX_SD_OUTPUT_ON")

So first, let’s notice that it blames a XCVR_A10_* assignment, even though I used a XCVR_C10_* assignment in the QSF file. Really.

Also note the hint that setting sup_mode to ENGINEERING_MODE would have let us off the hook. More on that below (however don’t expect much).

But how did the assigning XCVR_C10_RX_SD_OUTPUT_ON with the integer 3 turn into DATA_PULSE_10? Maybe look in PMA_RegMap.csv, mentioned above? But no, DATA_PULSE_10 is assigned 5′b01110 as a value to write to a register, and it’s the 5th value listed, so no matter if you count from zero or one, 3 is not the answer.

Maybe ct2_pma_rx_sd_simple.tcl, also mentioned above? That helps even less, as there’s no sign there that DATA_PULSE_10 would be special. In short, just play with the integer value until hitting gold. Or even better, don’t assign anything, and use the default.

Likewise, setting

set_instance_assignment -name XCVR_C10_RX_SD_OUTPUT_OFF 6 -to gtx_rxp

yields

    Error (15744): In atom 'frontend_ins|xcvr_inst|xcvr_native_a10_0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_sd.inst_twentynm_hssi_pma_rx_sd'
    Error (15744): The settings must match one or more of these conditions:
    Error (15744): ( sup_mode == ENGINEERING_MODE ) OR ( prot_mode != SATA_RX ) OR ( sd_output_off == CLK_DIVRX_2 )
    Error (15744): But the following assignments violate the above conditions:
    Error (15744): sup_mode = USER_MODE
    Error (15744): prot_mode = SATA_RX
    Error (15744): sd_output_off = CLK_DIVRX_7 -- Set by Pin Assignment "XCVR_A10_RX_SD_OUTPUT_OFF" (QSF Name "XCVR_A10_RX_SD_OUTPUT_OFF")

Attempting to enable Engineering Mode

Since ENGINEERING_MODE is often mentioned in the fitter’s error messages, I thought maybe enabling it could silence these errors and allow wider options. For example, I attempted to enable the Electrical Idle state on the transmission wires on a non-PCIe transciever by editing one of the files generated by the transceiver IP tools (xcvr_xcvr_native_a10_0.v), changing the line saying

.hssi_tx_pcs_pma_interface_bypass_pma_txelecidle("true"),

to

.hssi_tx_pcs_pma_interface_bypass_pma_txelecidle("false"),

but the fitter threw the following error:

    Error (15744): In atom 'xcvr_inst|xcvr_native_a10_0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pcs_pma_interface.inst_twentynm_hssi_tx_pcs_pma_interface'
    Error (15744): The settings must match one or more of these conditions:
    Error (15744): ( sup_mode == ENGINEERING_MODE ) OR ( bypass_pma_txelecidle == TRUE ) OR ( pcie_sub_prot_mode_tx != OTHER_PROT_MODE )
    Error (15744): But the following assignments violate the above conditions:
    Error (15744): sup_mode = USER_MODE
    Error (15744): bypass_pma_txelecidle = FALSE
    Error (15744): pcie_sub_prot_mode_tx = OTHER_PROT_MODE

So it tells me that if I want bypass_pma_txelecidle as “false” I have to either set pcie_sub_prot_mode_tx to one of the PCIe modes, or set sup_mode to ENGINEERING_MODE. Changing pcie_sub_prot_mode_tx is out of the question, because the only way to settle the conflicts reported by the fitter is to turn the entire transceiver to follow the predefined PCIe settings. Had I been able to go that path, I would have done that long ago.

So switch to Engineering Mode, whatever that means, by editing the same file, changing

.hssi_tx_pcs_pma_interface_sup_mode("user_mode"),

to

.hssi_tx_pcs_pma_interface_sup_mode("engineering_mode"),

but the fitter really didn’t like that:

    Error (15744): In atom 'xcvr_inst|xcvr_native_a10_0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pcs_pma_interface.inst_twentynm_hssi_tx_pcs_pma_interface'
    Error (15744): The settings must match one or more of these conditions:
    Error (15744): ( sup_mode OR ( sup_mode == USER_MODE )
    Error (15744): But the following assignments violate the above conditions:
    Error (15744): sup_mode = ENGINEERING_MODE

This is somewhat cryptic, because it implies that sup_mode could just evaluate “true” in some way. Anyhow, selecting ENGINEERING_MODE was rejected flat, so that’s not an option for us regular people. There’s probably some secret sauce method to allow this, but that goes beyond what is sensible to work around the tools’ restrictions.

Conclusion

Setting up a Cyclone 10 transceiver for a use other than specifically intended by the FPGA’s vendor is a visit to nomansland. Reverse engineering Quartus does help to some extent, but some issues are left to guessing.

And the transceiver itself appears to be a step backwards compared with the series-V FPGAs. It may reach higher rates, but that came at a cost. Or maybe it’s related to the different silicon process. This way or another, it’s not all that impressive.

]]> https://billauer.se/blog/2021/10/arria-cyclone-10-signal-detect-oob/feed/ 0 Intel FPGA’s Stratix 10: My impressions and notes https://billauer.se/blog/2019/09/altera-intel-stratix-10/ https://billauer.se/blog/2019/09/altera-intel-stratix-10/#comments Thu, 26 Sep 2019 11:34:43 +0000 eli https://billauer.se/blog/?p=5879 Introduction

These are a few random things I wrote down as I worked with the Stratix 10 Development Kit, with focus on its PCIe interface. Quite obviously, it’s mostly about things I found noteworthy about this specific FPGA and its board, compared with previous hardware I’ve encountered.

Generally speaking, Stratix 10 is not for the faint-hearted: It has quite a few special issues that require attention when designing with it (some detailed below), and it’s clearly designed with the assumption that if you’re working with this king-sized beast, you’re most likely part of some high-end project, being far from a novice in the FPGA field.

Some National Geographic

Even though I discuss the development kit further below, I’ll start with a couple of images of the board’s front and back. This 200W piece of logic has a liquid cooler and an exceptionally noisy fan — none of which are shown in Intel’s official images I’ve seen. In other words, it’s not as innocent as it may appear from the official pics.

There are no earplugs in the kit itself, so it’s recommended to buy something of that sort along with it. One could only wish for a temperature controlled fan. I mean, measuring the temperature of the liquid would probably have done the job. Some silence when the device isn’t working hard.

So here’s what the board looks like out of the box (in particular DIP switches in the default positions). Click images to enlarge.

Front side of Stratix 10 Development Kit

Front side of Stratix 10 Development Kit

Back side of Stratix 10 Development Kit

Back side of Stratix 10 Development Kit

 

“Hyperflex”

The logic on the Stratix 10 FPGAs has been given this rather promising name, implying that there’s something groundbreaking about it. However synthesizing a real-life design for Stratix 10, I experienced no advantage over Cyclone 10: All of the hyper-something phases got their moment of glory during the project implementation (Quartus Pro 19.2), but frankly speaking, when the design got the slightest heavy (5% of the FPGA resources, but still a 256-bit wide bus everywhere on a 250 MHz clock), timing failed exactly as it would on a Cyclone 10.

Comparing with Xilinx, it feels a bit like Kintex-7 (mainline speed grade -2), in terms of the logic’s timing performance. Maybe if the logic design is tuned to fit the architecture, there’s a difference.

Assuming that this Hyperflex thing is more than just a marketing buzz, I imagine that the features of this architecture are taken advantage of in Intel’s own IP cores for certain tasks (with extensive pipelining?). Just don’t expect anything hyper to happen when implementing your own plain design.

PCIe, Transceivers and Tiles

It’s quite common to use the term “tiles” in the FPGA industry to describe sections on the silicon die that belong to a certain functionality. However the PCIe + transceiver tiles on a Stratix 10 are separate silicon dies on the package substrate, connected to the main logic fabric (“HyperFlex”) through Intel’s Embedded Multi-die Interconnect Bridge (EMIB) interface. Not that it really matters, but anyhow.

H, L and E tiles provide Gigabit transceivers. H and L tiles come with exactly one PCIe hard IP each, E-tiles with 100G Ethernet. There might be one or more of these tiles on a Stratix 10 device. It seems like the L tile will vanish with time, as it has weaker performance in almost all parameters.

All tiles have 24 Gigabit transceivers. Those not used by the hard IP are vacant for general purpose, even though some might become unusable, subject to certain rules (given in the relevant user guides).

And here comes the hard nut: PCIe has a minimal data interface of 256 bits with the application logic. The other possibility is 512 bits. This can be a significant burden when porting a design from earlier FPGA families, in particular if they were based upon a narrower data interface.

Xillybus supports the Stratix 10 device family, however.

PCIe unsupported request error

Quite interestingly, there were correctable (and hence practically harmless) errors on the PCIe link consistently when booting a PC with the official development kit, with a production grade (i.e. not ES) H-tile FPGA. This is what plain lspci -vv gave me, even before the application logic got a chance to do anything:

01:00.0 Unassigned class [ff00]: Altera Corporation Device ebeb (rev 01)
        Subsystem: Altera Corporation Device ebeb
        Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
        Interrupt: pin A routed to IRQ 16
        Region 0: Memory at d0100000 (64-bit, prefetchable) [size=256]
        Capabilities: [40] Power Management version 3
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
                Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
        Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit-
                Address: 00000000  Data: 0000
                Masking: 00000000  Pending: 00000000
        Capabilities: [70] Express (v2) Endpoint, MSI 00
                DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us
                        ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset+
                DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
                        RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop- FLReset-
                        MaxPayload 256 bytes, MaxReadReq 512 bytes
                DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend-
                LnkCap: Port #1, Speed 5GT/s, Width x16, ASPM not supported, Exit Latency L0s <64ns, L1 <1us
                        ClockPM- Surprise- LLActRep- BwNot-
                LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk-
                        ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
                LnkSta: Speed 5GT/s, Width x16, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt-
                DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR-, OBFF Not Supported
                DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
                LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
                         Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
                         Compliance De-emphasis: -6dB
                LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
                         EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
        Capabilities: [100 v2] Advanced Error Reporting
                UESta:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
                UEMsk:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
                UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
                CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
                CEMsk:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
                AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-

As highlighted above, Unsupported Request correctable errors took place on the link. Even though this is harmless, it’s nevertheless nothing that should happen on a properly working PCIe link.

Note that I ran the PCIe link on Gen2 only, even though it supports Gen3. Not that it should matter.

Reset release IP

According to Intel’s Configuration Guide for Stratix 10 for Quartus Design Suite 19.2, one can’t rely on the device’s consistent wakeup, but the nINIT_DONE signal must be used to reset all logic:

“The entire device does not enter user mode simultaneously. Intel requires you to include the Intel Stratix 10 Reset Release IP on page 22 to hold your application logic in the reset state until the entire FPGA fabric is in user mode. Failure to include this IP in your design may result in intermittent application logic failures.”

Note nINIT_DONE is asserted (low) when it’s fine to run the logic, so it’s effective an active HIGH reset. It’s so easy to get confused, as the “n” prefix triggers the “active low reset” part of an FPGA designer’s brain.

Failing to have the Reset Release IP included in the project results the following critical warning during synthesis (Quartus Pro 19.2):

Critical Warning (20615): Use the Reset Release IP in Intel Stratix 10 designs to ensure a successful configuration. For more information about the Reset Release IP, refer to the Intel Stratix 10 Configuration User Guide.

The IP just exposes the nINIT_DONE signal as an output and has no parameters. It boils down to the following:

wire ninit_done;
altera_s10_user_rst_clkgate init_reset(.ninit_done(ninit_done));

One could instantiate this directly, but it’s not clear if this is Quartus forward compatible, and it won’t silence the critical warning.

However Quartus Pro 18.0 doesn’t issue any warning if the Reset Release IP is missing, and neither is this issue mentioned in the related configuration guide. Actually, the required IP isn’t available on Quartus Pro 18.0. This issue obviously evolved with time.

Variable core voltage (SmartVID)

Another ramp-up in the usage complexity is the core voltage supply. The good old practice is to set the power supply to whatever voltage the datasheet requires, but no, Stratix 10 FPGAs need to control the power supply, in order to achieve the exact voltage that is required for each specific device. So there’s now a Power Management User Guide to tackle this issue.

This has a reason: As the transistors get smaller, so does the tolerance of the process get a larger impact. To compensate for these tolerances, and not take a hit on the timing performance, each device has its own ideal core voltage. So if you’ve gone as far as using a Stratix 10 FPGA, what’s connecting a few I2C wires to the power supply and let it pick its favorite voltage?

The impact on the FPGA design is the need to inform the tools which pins to use for this purpose, what I2C address to use, which power supply to expect on the other end, and other parameters. This takes the form of a few extra lines, as shown below for the Stratix 10 Development Kit:

set_global_assignment -name USE_PWRMGT_SCL SDM_IO14
set_global_assignment -name USE_PWRMGT_SDA SDM_IO11
set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER"
set_global_assignment -name PWRMGT_BUS_SPEED_MODE "400 KHZ"
set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE LTM4677
set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 4F
set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 00
set_global_assignment -name PWRMGT_PAGE_COMMAND_ENABLE ON
set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "AUTO DISCOVERY"
set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS

It’s among the things that are easy when they work, but when designing your own board and something goes wrong with the I2C bus, well, well.

“Self service licensing”

The Stratix 10 Development Kit includes a one-year license for Quartus Pro, which is activated on Intel’s website. It’s recommended to start this process as soon as possible, as it has a potential of getting tangled and time consuming. In particular, be sure to know which email address was reported to Intel along with the purchase of the Kit, and that you have a fully verified account for that email address on Intel’s website.

That’s because the self-service licensing procedure is possible only from the Intel account that is registered with a specific email address. This email address is the one that the distributor reported when forwarding the order for the development kit to Intel. In my case, they used an address they had on record from a previous purchase I made from the same distributor, and it didn’t even cross my mind to try it.

Be sure to fill in the detailed registration form and to confirm the email address. Access to the licensing area is denied otherwise. It continues to be denied for a few days after filling in the details. Probably a matter of validation by a human.

The serial number that needs to be fed in (or does it? see below) is the one that appears virtually everywhere (on the PCB itself, on the package, on the outer box with which the package arrived), and has the form of e.g. 10SHTPCIe0001234. However the instructions said it should be “printed on the side of the development kit box below the bottom bar code”. Well, there is nothing printed under the bottom bar code. It’s not so difficult to find it, as it says “serial number”, but when the registration fails, this misleading direction adds a level of confusion.

Since the serial number is so out in the open, it’s quite clear why another form of authentication is needed. Too bad that the email issue wasn’t mentioned in the instructions.

In my case, there was no need to feed any serial number. Once the Intel account was validated (a few days after filling in the registration details), the license simply appeared on the self-service licensing page. As I contacted Intel’s licensing support twice throughout the process, it’s possible that someone at Intel’s support took care of pairing the serial number  with my account.

Development kit’s power supplies

I put this section last, because it’s the one that is quite pointless reading, frankly speaking. The bottom line is simple, exactly like the user guide says: If you use the board stand-alone, use the power supply that came along with it. If the board goes into the PCIe slot, connect both J26 and J27 to the computer’s ATX power supply, or the board will not power up.

J27 is a plain PCIe power connector (6 pins), and J26 is an 8-pin power connector. On my plain ATX power supply there was a PCIe power connector with a pair of extra pins attached with a cable tie (8 pins total). It fit in nicely into J26, it worked, no smoke came out, so I guess that’s the way it should be done. See pictures below, click to enlarge.

ATX power supply connected to Stratix 10 Development Kit, front side

ATX power supply connected to Stratix 10 Development Kit, front side

ATX power supply connected to Stratix 10 Development Kit, back side

ATX power supply connected to Stratix 10 Development Kit, back side

Now to the part you can safely skip:

As the board is rated at 240 W and may draw up to 20A from its internal +12V power supply, it might be interesting understand how the power load is distributed among the different sources. However the gory details have little practical importance, as the board won’t power up when plugged in as a PCIe card unless power is applied both to J26 and J27 (the power-up is sequencer set up this way, I guess). So this is just a little bit of theory.

There are three power groups, each having a separate 12V power rail: 12V_GROUP1, 12V_GROUP2 and 12V_GROUP3.

12V_GROUP2 will feed 12V_GROUP1 and 12V_GROUP3 with current if their voltage is lower than its own, by virtue of an emulated ideal diode. It’s as if there was two ideal diodes connected with their anodes on 12V_GROUP2 and one diode’s cathode on 12V_GROUP1, and cathode on 12V_GROUP3.

These voltage rails are in turn fed by external connectors, through emulated ideal diodes as follows:

  • J26 (8-pin aux voltage) feeds 12V_GROUP1
  • J27 (6-pin PCIe / power brick) feeds 12V_GROUP2
  • The PCIe slot’s 12V supply feeds 12V_GROUP3

The PCIe slot’s 3.3V supply is not used by the board.

This arrangement makes sense: If the board is used standalone, the brick power supply is connected to J27, and feeds all three groups. When used in a PCIe slot, the slot itself can only power 12V_GROUP3, so by itself, the board can’t power up. Theoretically speaking, J27 needs to be connected to the computer’s power supply through a PCIe power connector, at the very least. For the higher power applications, J26 should be connected as well to the power supply, to allow for the higher current flow. In practice, J27 alone won’t power the board up, probably as a safety measure.

The FPGA’s core voltage is S10_VCC, which is generated from 12V_GROUP1 — this is the heavy lifting, and it’s not surprising that it’s connected to J26, which is intended for the higher currents.

The ideal diode emulation is done with LTC4357 devices, which measure the voltage between the emulated diode’s anode and cathode. If this voltage is slightly positive, the device opens a external power FET by applying voltage to its gate. This FET’s drain and source pins are connected to the emulated diode’s anode and cathode pins, so all in all, when there’s a positive voltage across it, current flows. This reduces the voltage drop considerably, allowing efficient power supply OR-ing, as done extensively on this development kit.

The board’s user guide advises against connecting the brick power supply to J27 when the board is in a PCIe slot, but also mentions the ideal diode mechanism (once again, it won’t power up at all this way). This is understandable, as doing so will cause current to be drawn from the PCIe slot’s 12V supply when its voltage is higher that the one supplied by J27, even momentarily. With the voltage turbulence that is typical to switching power supplies, the currents may end up swinging quite a lot in an unfortunate combination of power supplies.

So even though it’s often more comfortable to control the power of the board separately from the hosting computer’s power, or to connect J27 only if the board is expected to draw less than 75W, both possibilities are eliminated. Both the noisy fan and the board’s refusal to power up unless fed properly prepare the board for the worst case power consumption scenario.

]]> https://billauer.se/blog/2019/09/altera-intel-stratix-10/feed/ 0 Intel Stratix 10 PCIe IP: Building it only appears to be stuck https://billauer.se/blog/2019/08/stratix-10-pcie-qsys-generate-infinite-loop/ https://billauer.se/blog/2019/08/stratix-10-pcie-qsys-generate-infinite-loop/#comments Sat, 17 Aug 2019 15:17:01 +0000 eli https://billauer.se/blog/?p=5824 These are a few notes when implementing an FPGA design for Stratix 10 with a Makefile flow (i.e. command-line utilities) with Quartus 19.2.

So I wanted was to implement a design including the PCIe 16x block for Stratix 10. I added a line going

set_global_assignment -name IP_FILE pcie_s10_16x.ip

in the relevant QSF file. And by the way: Don’t add a Verilog black box module on behalf of this IP in the the design. It will override the IP, and implement an empty module.

Anyhow, attempting to synthesize with quartus_syn failed, saying the RTL files haven’t been generated:

Error (16556): The synthesis RTL for pcie_s10_16x.ip has not been generated. Generate the synthesis RTL from within Platform Designer.

Which was a bit odd. I’m quite used to adding IP files like this, and well, good old quartus_map used to take care of this gracefully. But no.

OK, so I went for building the IP manually. Changed to the relevant directory, and

$ qsys-generate  --synthesis pcie_s10_16x.ip

but that appeared to be stuck. Or more like in some kind of infinite loop. And taking ~ 11 GB of virtual memory with some Java process apparently running forever. But it wasn’t forever. Actually, on a rather strong machine, it eventually ended:

$ time qsys-generate  --synthesis pcie_s10_16x.ip

[ ... ]

real	7m28.275s
user	10m8.443s
sys	0m34.967s

There’s a lot of output there in the middle, but the bottom line is 7 and a half minutes for generating the sources for a PCIe block. Quite amazing. The full transcript is given at the end of this post, for reference.

What apparently seems to take a lot of time is that some preparations are made for each of the PCIe lanes, and there is 16 of them.

Actually, use quartus_ipgenerate instead

This isn’t directly related, but it’s probably better to go something like

$ quartus_ipgenerate --run_default_mode_op projname -c projname

instead of qsys-generate (where projname is the name of the project, i.e. the prefix to the .qsf file). This generates all .qsys and .ip files mentioned in the QSF file, and skips generating them if the already exist. The –run_default_mode_op flag is a shortcut for “do the right thing” but isn’t documented, so it may not work on future versions of Quartus Pro. In that case, go something like:

$ quartus_ipgenerate --clear_ip_generation_dirs --generate_project_ip_files --synthesis=verilog projname

This is actually somewhat different, because it clears the directories, and hence always rebuilds the HDL files.

This way or another, quartus_ipgenerate runs qsys-generate to do the actual work. The former just comes handier in scripts, since it’s something one can (and should) put just before the call to quartus_syn. It doesn’t hurt if there are no IPs in the project, but it makes sure they are generated if they are.

And yet another unrelated fact: If an included QSYS file is referred to, all the sub-IPs must be listed in the QSF file explicitly as well (possibly as QSYS_FILE), or the quartus_syn will not find them.

The output

So this is what a full session looks like. I’ve cut out the parts that are just repetitions.

$ time qsys-generate  --synthesis pcie_s10_16x.ip
2019.08.16.15:11:30 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.
2019.08.16.15:11:40 Info: Saving generation log to /home/user/try/pcie_s10_16x/pcie_s10_16x_generation.rpt
2019.08.16.15:11:40 Info: Generated by version: 19.2 build 57
2019.08.16.15:11:40 Info: Starting: Create HDL design files for synthesis
2019.08.16.15:11:40 Info: qsys-generate /home/user/try/pcie_s10_16x.ip --synthesis=VERILOG --output-directory=/home/user/try/pcie_s10_16x --family="Stratix 10" --part=1SG280HU2F50E2VG
2019.08.16.15:11:41 Warning: pcie_s10_hip_ast_0: Used altera_pcie_s10_hip_ast 20.0.0 (instead of 18.0)
2019.08.16.15:11:45 Info: pcie_s10_16x.pcie_s10_hip_ast_0: Gen2 (5.0 Gbps) x16 256-bit
2019.08.16.15:11:45 Warning: pcie_s10_16x.pcie_s10_hip_ast_0.rx_st: The empty signal width should be 1 bits.
2019.08.16.15:12:10 Info: pcie_s10_hip_ast_0.fpll_g1g2xn: For the selected device(1SG280HU2F50E2VG), PLL speed grade is 2.
2019.08.16.15:12:11 Info: phy_g2x16.altera_xcvr_pcie_hip_channel_s10_ch0: The TX PCS-Core Interface FIFO is operating in full-rate transfer mode.
2019.08.16.15:12:11 Info: phy_g2x16.altera_xcvr_pcie_hip_channel_s10_ch0: The RX PCS-Core Interface FIFO is operating in full-rate transfer mode.
2019.08.16.15:12:11 Info: phy_g2x16.altera_xcvr_pcie_hip_channel_s10_ch0: For the selected device(1SG280HU2F50E2VG), transceiver speed grade is 2 and core speed grade is 2.
2019.08.16.15:12:11 Info: phy_g2x16.altera_xcvr_pcie_hip_channel_s10_ch0: For current configuration, TX PCS FIFO depth is "16" and TX Core FIFO depth is "16".
2019.08.16.15:12:11 Info: phy_g2x16.altera_xcvr_pcie_hip_channel_s10_ch0: For current configuration, RX PCS FIFO depth is "16" and RX Core FIFO depth is "32".
2019.08.16.15:12:11 Info: phy_g2x16.altera_xcvr_pcie_hip_channel_s10_ch0: "PCS clkout" (pcs_clkout) is selected to drive tx_clkout port and the clock frequency is 0.0 MHz.
2019.08.16.15:12:11 Info: phy_g2x16.altera_xcvr_pcie_hip_channel_s10_ch0: "PCS clkout x2" (pcs_x2_clkout) is selected to drive tx_clkout2 port and the clock frequency is 0.0 MHz.
2019.08.16.15:12:11 Info: phy_g2x16.altera_xcvr_pcie_hip_channel_s10_ch0: "PCS clkout" (pcs_clkout) is selected to drive rx_clkout port and the clock frequency is 0.0 MHz.
2019.08.16.15:12:11 Info: phy_g2x16.altera_xcvr_pcie_hip_channel_s10_ch0: A design example cannot be generated for "Tx PLL reference clock frequency"=="125.0" && "Selected CDR reference clock frequency"=="100.000"
2019.08.16.15:12:11 Info: phy_g2x16.altera_xcvr_pcie_hip_channel_s10_ch0: Design example cannot be generated for the current configuration. Please check under Design Example tab and system message below for more detailed information.
2019.08.16.15:12:11 Info: phy_g2x16.altera_xcvr_pcie_hip_channel_s10_ch0: Note - The external TX PLL IP must be configured with an output clock frequency of 2500.0 MHz.
2019.08.16.15:12:11 Info: phy_g2x16.altera_xcvr_pcie_hip_channel_s10_ch1: The TX PCS-Core Interface FIFO is operating in full-rate transfer mode.
2019.08.16.15:12:11 Info: phy_g2x16.altera_xcvr_pcie_hip_channel_s10_ch1: The RX PCS-Core Interface FIFO is operating in full-rate transfer mode.
2019.08.16.15:12:11 Info: phy_g2x16.altera_xcvr_pcie_hip_channel_s10_ch1: For the selected device(1SG280HU2F50E2VG), transceiver speed grade is 2 and core speed grade is 2.
2019.08.16.15:12:11 Info: phy_g2x16.altera_xcvr_pcie_hip_channel_s10_ch1: For current configuration, TX PCS FIFO depth is "16" and TX Core FIFO depth is "16".
2019.08.16.15:12:11 Info: phy_g2x16.altera_xcvr_pcie_hip_channel_s10_ch1: For current configuration, RX PCS FIFO depth is "16" and RX Core FIFO depth is "32".
2019.08.16.15:12:11 Info: phy_g2x16.altera_xcvr_pcie_hip_channel_s10_ch1: "PCS clkout" (pcs_clkout) is selected to drive tx_clkout port and the clock frequency is 0.0 MHz.
2019.08.16.15:12:11 Info: phy_g2x16.altera_xcvr_pcie_hip_channel_s10_ch1: "PCS clkout x2" (pcs_x2_clkout) is selected to drive tx_clkout2 port and the clock frequency is 0.0 MHz.
2019.08.16.15:12:11 Info: phy_g2x16.altera_xcvr_pcie_hip_channel_s10_ch1: "PCS clkout" (pcs_clkout) is selected to drive rx_clkout port and the clock frequency is 0.0 MHz.
2019.08.16.15:12:11 Info: phy_g2x16.altera_xcvr_pcie_hip_channel_s10_ch1: A design example cannot be generated for "Tx PLL reference clock frequency"=="125.0" && "Selected CDR reference clock frequency"=="100.000"
2019.08.16.15:12:11 Info: phy_g2x16.altera_xcvr_pcie_hip_channel_s10_ch1: Design example cannot be generated for the current configuration. Please check under Design Example tab and system message below for more detailed information.

[ The same over and over again... ]

2019.08.16.15:12:24 Info: phy_g2x16.altera_xcvr_pcie_hip_channel_s10_ch15: The TX PCS-Core Interface FIFO is operating in half-rate transfer mode.
2019.08.16.15:12:24 Info: phy_g2x16.altera_xcvr_pcie_hip_channel_s10_ch15: The RX PCS-Core Interface FIFO is operating in half-rate transfer mode.
2019.08.16.15:12:24 Info: phy_g2x16.altera_xcvr_pcie_hip_channel_s10_ch15: For the selected device(1SG280HU2F50E2VG), transceiver speed grade is 2 and core speed grade is 2.
2019.08.16.15:12:24 Info: phy_g2x16.altera_xcvr_pcie_hip_channel_s10_ch15: For current configuration, TX PCS FIFO depth is "8" and TX Core FIFO depth is "8".
2019.08.16.15:12:24 Info: phy_g2x16.altera_xcvr_pcie_hip_channel_s10_ch15: For current configuration, RX PCS FIFO depth is "8" and RX Core FIFO depth is "16".
2019.08.16.15:12:24 Info: phy_g2x16.altera_xcvr_pcie_hip_channel_s10_ch15: "PCS clkout" (pcs_clkout) is selected to drive tx_clkout port and the clock frequency is 0.0 MHz.
2019.08.16.15:12:24 Info: phy_g2x16.altera_xcvr_pcie_hip_channel_s10_ch15: "PCS clkout x2" (pcs_x2_clkout) is selected to drive tx_clkout2 port and the clock frequency is 0.0 MHz.
2019.08.16.15:12:24 Info: phy_g2x16.altera_xcvr_pcie_hip_channel_s10_ch15: "PCS clkout" (pcs_clkout) is selected to drive rx_clkout port and the clock frequency is 0.0 MHz.
2019.08.16.15:12:24 Info: phy_g2x16.altera_xcvr_pcie_hip_channel_s10_ch15: A design example cannot be generated for "Tx PLL reference clock frequency"=="125.0" && "Selected CDR reference clock frequency"=="100.000"
2019.08.16.15:12:24 Info: phy_g2x16.altera_xcvr_pcie_hip_channel_s10_ch15: Design example cannot be generated for the current configuration. Please check under Design Example tab and system message below for more detailed information.
2019.08.16.15:12:24 Info: phy_g2x16.altera_xcvr_pcie_hip_channel_s10_ch15: Note - The external TX PLL IP must be configured with an output clock frequency of 2500.0 MHz.
2019.08.16.15:12:24 Info: pcie_s10_16x: "Transforming system: pcie_s10_16x"
2019.08.16.15:12:24 Info: pcie_s10_16x: "Naming system components in system: pcie_s10_16x"
2019.08.16.15:12:24 Info: pcie_s10_16x: "Processing generation queue"
2019.08.16.15:12:24 Info: pcie_s10_16x: "Generating: pcie_s10_16x"
2019.08.16.15:12:24 Info: pcie_s10_16x: "Generating: altera_pcie_s10_hip_ast"
2019.08.16.15:12:24 Info: phy_g2x16: "Generating: phy_g2x16"
2019.08.16.15:12:24 Info: fpll_g1g2xn: "Generating: fpll_g1g2xn"
2019.08.16.15:12:24 Info: pcie_s10_16x: "Generating: phy_g2x16"
2019.08.16.15:12:24 Info: pcie_s10_16x: "Generating: fpll_g1g2xn"
2019.08.16.15:12:25 Info: pcie_s10_16x: "Generating: pcie_s10_16x_altera_xcvr_pcie_hip_native_s10_191_wqso57y"
2019.08.16.15:12:25 Info: altera_xcvr_pcie_hip_channel_s10_ch0: "Generating: altera_xcvr_pcie_hip_channel_s10_ch0"
2019.08.16.15:12:25 Info: altera_xcvr_pcie_hip_channel_s10_ch1: "Generating: altera_xcvr_pcie_hip_channel_s10_ch1"
2019.08.16.15:12:25 Info: altera_xcvr_pcie_hip_channel_s10_ch2: "Generating: altera_xcvr_pcie_hip_channel_s10_ch2"
2019.08.16.15:12:25 Info: altera_xcvr_pcie_hip_channel_s10_ch3: "Generating: altera_xcvr_pcie_hip_channel_s10_ch3"
2019.08.16.15:12:25 Info: altera_xcvr_pcie_hip_channel_s10_ch4: "Generating: altera_xcvr_pcie_hip_channel_s10_ch4"
2019.08.16.15:12:25 Info: altera_xcvr_pcie_hip_channel_s10_ch5: "Generating: altera_xcvr_pcie_hip_channel_s10_ch5"
2019.08.16.15:12:25 Info: altera_xcvr_pcie_hip_channel_s10_ch6: "Generating: altera_xcvr_pcie_hip_channel_s10_ch6"
2019.08.16.15:12:25 Info: altera_xcvr_pcie_hip_channel_s10_ch7: "Generating: altera_xcvr_pcie_hip_channel_s10_ch7"
2019.08.16.15:12:25 Info: altera_xcvr_pcie_hip_channel_s10_ch8: "Generating: altera_xcvr_pcie_hip_channel_s10_ch8"
2019.08.16.15:12:25 Info: altera_xcvr_pcie_hip_channel_s10_ch9: "Generating: altera_xcvr_pcie_hip_channel_s10_ch9"
2019.08.16.15:12:25 Info: altera_xcvr_pcie_hip_channel_s10_ch10: "Generating: altera_xcvr_pcie_hip_channel_s10_ch10"
2019.08.16.15:12:25 Info: altera_xcvr_pcie_hip_channel_s10_ch11: "Generating: altera_xcvr_pcie_hip_channel_s10_ch11"
2019.08.16.15:12:25 Info: altera_xcvr_pcie_hip_channel_s10_ch12: "Generating: altera_xcvr_pcie_hip_channel_s10_ch12"
2019.08.16.15:12:25 Info: altera_xcvr_pcie_hip_channel_s10_ch13: "Generating: altera_xcvr_pcie_hip_channel_s10_ch13"
2019.08.16.15:12:25 Info: altera_xcvr_pcie_hip_channel_s10_ch14: "Generating: altera_xcvr_pcie_hip_channel_s10_ch14"
2019.08.16.15:12:25 Info: altera_xcvr_pcie_hip_channel_s10_ch15: "Generating: altera_xcvr_pcie_hip_channel_s10_ch15"
2019.08.16.15:12:25 Info: pcie_s10_16x: "Generating: pcie_s10_16x_altera_xcvr_fpll_s10_htile_1911_xs4xrjq"
2019.08.16.15:12:25 Info: fpll_g1g2xn: add_fileset_file ./altera_std_synchronizer_nocut.v VERILOG PATH ../../../../primitives/altera_std_synchronizer/altera_std_synchronizer_nocut.v
2019.08.16.15:12:25 Info: fpll_g1g2xn: add_fileset_file ./s10_avmm_h.sv SYSTEM_VERILOG PATH ../../../altera_xcvr_native_phy/altera_xcvr_native_s10/source/s10_avmm_h.sv
2019.08.16.15:12:25 Info: fpll_g1g2xn: add_fileset_file ./altera_xcvr_native_s10_functions_h.sv SYSTEM_VERILOG PATH ../../../altera_xcvr_native_phy/altera_xcvr_native_s10/source/altera_xcvr_native_s10_functions_h.sv
2019.08.16.15:12:25 Info: fpll_g1g2xn: add_fileset_file ./alt_xcvr_native_anlg_reset_seq.sv SYSTEM_VERILOG PATH ../../../altera_xcvr_native_phy/altera_xcvr_native_s10/source/alt_xcvr_native_anlg_reset_seq.sv
2019.08.16.15:12:25 Info: fpll_g1g2xn: add_fileset_file ./alt_xcvr_pll_rcfg_arb.sv SYSTEM_VERILOG PATH ../../common/alt_xcvr_pll_rcfg_arb.sv
2019.08.16.15:12:25 Info: fpll_g1g2xn: add_fileset_file ./alt_xcvr_pll_embedded_debug.sv SYSTEM_VERILOG PATH ../../common/alt_xcvr_pll_embedded_debug.sv
2019.08.16.15:12:25 Info: fpll_g1g2xn: add_fileset_file ./alt_xcvr_pll_avmm_csr.sv SYSTEM_VERILOG PATH ../../common/alt_xcvr_pll_avmm_csr.sv
2019.08.16.15:12:25 Info: fpll_g1g2xn: add_fileset_file ./alt_xcvr_resync.sv SYSTEM_VERILOG PATH ../../../../altera_xcvr_generic/ctrl/alt_xcvr_resync.sv
2019.08.16.15:12:25 Info: fpll_g1g2xn: add_fileset_file ./alt_xcvr_arbiter.sv SYSTEM_VERILOG PATH ../../../../altera_xcvr_generic/ctrl/alt_xcvr_arbiter.sv
2019.08.16.15:12:25 Info: fpll_g1g2xn: Building configuration data for reconfiguration profile 0
2019.08.16.15:12:25 Info: pcie_s10_16x: "Generating: pcie_s10_16x_altera_xcvr_pcie_hip_native_s10_191_3e57toy"
2019.08.16.15:12:25 Info: pcie_s10_16x: "Generating: pcie_s10_16x_altera_xcvr_pcie_hip_native_s10_191_zj3agaa"
2019.08.16.15:12:25 Info: pcie_s10_16x: "Generating: pcie_s10_16x_altera_xcvr_pcie_hip_native_s10_191_prgcfha"
2019.08.16.15:12:25 Info: pcie_s10_16x: "Generating: pcie_s10_16x_altera_xcvr_pcie_hip_native_s10_191_jgm5cfa"
2019.08.16.15:12:25 Info: pcie_s10_16x: "Generating: pcie_s10_16x_altera_xcvr_pcie_hip_native_s10_191_ykdbt6y"
2019.08.16.15:12:25 Info: pcie_s10_16x: "Generating: pcie_s10_16x_altera_xcvr_pcie_hip_native_s10_191_lzoehjq"
2019.08.16.15:12:25 Info: pcie_s10_16x: "Generating: pcie_s10_16x_altera_xcvr_pcie_hip_native_s10_191_r73nlzi"
2019.08.16.15:12:25 Info: pcie_s10_16x: "Generating: pcie_s10_16x_altera_xcvr_pcie_hip_native_s10_191_3qbzhci"
2019.08.16.15:12:25 Info: pcie_s10_16x: "Generating: pcie_s10_16x_altera_xcvr_pcie_hip_native_s10_191_4b2ohhy"
2019.08.16.15:12:25 Info: pcie_s10_16x: "Generating: pcie_s10_16x_altera_xcvr_pcie_hip_native_s10_191_45l4xnq"
2019.08.16.15:12:25 Info: pcie_s10_16x: "Generating: pcie_s10_16x_altera_xcvr_pcie_hip_native_s10_191_ipejypi"
2019.08.16.15:12:25 Info: pcie_s10_16x: "Generating: pcie_s10_16x_altera_xcvr_pcie_hip_native_s10_191_jtr36ma"
2019.08.16.15:12:25 Info: pcie_s10_16x: "Generating: pcie_s10_16x_altera_xcvr_pcie_hip_native_s10_191_dfssemq"
2019.08.16.15:12:25 Info: pcie_s10_16x: "Generating: pcie_s10_16x_altera_xcvr_pcie_hip_native_s10_191_dtiglpy"
2019.08.16.15:12:25 Info: pcie_s10_16x: "Generating: pcie_s10_16x_altera_xcvr_pcie_hip_native_s10_191_lh3sg5q"
2019.08.16.15:12:25 Info: pcie_s10_16x: "Generating: pcie_s10_16x_altera_xcvr_pcie_hip_native_s10_191_zgzdh3a"
2019.08.16.15:12:25 Info: pcie_s10_16x: "Generating: pcie_s10_16x_altera_xcvr_native_s10_htile_1920_3nhmcmq"
2019.08.16.15:12:25 Info: altera_xcvr_pcie_hip_channel_s10_ch0: add_fileset_file ./alt_xcvr_arbiter.sv SYSTEM_VERILOG PATH ../../../../altera_xcvr_generic/ctrl/alt_xcvr_arbiter.sv
2019.08.16.15:12:25 Info: altera_xcvr_pcie_hip_channel_s10_ch0: add_fileset_file ./altera_std_synchronizer_nocut.v VERILOG PATH ../../../../primitives/altera_std_synchronizer/altera_std_synchronizer_nocut.v
2019.08.16.15:12:25 Info: altera_xcvr_pcie_hip_channel_s10_ch0: add_fileset_file ./alt_xcvr_resync_std.sv SYSTEM_VERILOG PATH ../../../alt_xcvr_generic/alt_xcvr_resync_std.sv
2019.08.16.15:12:25 Info: altera_xcvr_pcie_hip_channel_s10_ch0: add_fileset_file ./alt_xcvr_reset_counter_s10.sv SYSTEM_VERILOG PATH ../../../altera_xcvr_reset_control_s10/alt_xcvr_reset_counter_s10.sv
2019.08.16.15:12:25 Info: altera_xcvr_pcie_hip_channel_s10_ch0: add_fileset_file ./altera_xcvr_native_s10_functions_h.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/altera_xcvr_native_s10_functions_h.sv
2019.08.16.15:12:25 Info: altera_xcvr_pcie_hip_channel_s10_ch0: add_fileset_file ./s10_avmm_h.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/s10_avmm_h.sv
2019.08.16.15:12:25 Info: altera_xcvr_pcie_hip_channel_s10_ch0: add_fileset_file ./alt_xcvr_native_avmm_csr.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_avmm_csr.sv
2019.08.16.15:12:25 Info: altera_xcvr_pcie_hip_channel_s10_ch0: add_fileset_file ./alt_xcvr_native_prbs_accum.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_prbs_accum.sv
2019.08.16.15:12:25 Info: altera_xcvr_pcie_hip_channel_s10_ch0: add_fileset_file ./alt_xcvr_native_odi_accel.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_odi_accel.sv
2019.08.16.15:12:25 Info: altera_xcvr_pcie_hip_channel_s10_ch0: add_fileset_file ./alt_xcvr_native_rcfg_arb.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_rcfg_arb.sv
2019.08.16.15:12:25 Info: altera_xcvr_pcie_hip_channel_s10_ch0: add_fileset_file ./alt_xcvr_early_spd_chng_s10_htile.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_early_spd_chng_s10_htile.sv
2019.08.16.15:12:25 Info: altera_xcvr_pcie_hip_channel_s10_ch0: add_fileset_file ./alt_xcvr_native_anlg_reset_seq.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_anlg_reset_seq.sv
2019.08.16.15:12:25 Info: altera_xcvr_pcie_hip_channel_s10_ch0: add_fileset_file ./alt_xcvr_native_dig_reset_seq.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_dig_reset_seq.sv
2019.08.16.15:12:25 Info: altera_xcvr_pcie_hip_channel_s10_ch0: add_fileset_file ./alt_xcvr_native_reset_seq.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_reset_seq.sv
2019.08.16.15:12:25 Info: altera_xcvr_pcie_hip_channel_s10_ch0: add_fileset_file ./alt_xcvr_native_anlg_reset_seq_wrapper.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_anlg_reset_seq_wrapper.sv
2019.08.16.15:12:25 Info: altera_xcvr_pcie_hip_channel_s10_ch0: add_fileset_file ./alt_xcvr_native_re_cal_chnl.v VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_re_cal_chnl.v
2019.08.16.15:12:25 Info: altera_xcvr_pcie_hip_channel_s10_ch0: add_fileset_file ./alt_xcvr_pcie_rx_eios_prot.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_pcie_rx_eios_prot.sv
2019.08.16.15:12:25 Info: altera_xcvr_pcie_hip_channel_s10_ch0: add_fileset_file ./alt_xcvr_native_rx_maib_wa.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_rx_maib_wa.sv
2019.08.16.15:12:26 Info: altera_xcvr_pcie_hip_channel_s10_ch0: Building configuration data for reconfiguration profile 0
ip-deploy --component-name=altera_xcvr_native_s10_htile --output-name=pcie_s10_16x_altera_xcvr_native_s10_htile_1920_3nhmcmq --output-directory=/tmp/alt8124_4770953449535589358.dir/0005_altera_xcvr_pcie_hip_channel_s10_ch0_gen --component-param=rcfg_enable=1 --component-param=device=1SG280HU2F50E2VG --component-param=base_device=ND5U {--component-param=device_die_types=HSSI_CRETE2E MAIN_ND5} {--component-param=device_die_revisions=HSSI_CRETE2E_REVB MAIN_ND5_REVC} --component-param=protocol_mode=pipe_g2 --component-param=set_data_rate=5000 --component-param=bonded_mode=pma_pcs --component-param=pcs_reset_sequencing_mode=bonded --component-param=enable_manual_bonding_settings=1 --component-param=manual_pcs_bonding_mode=ctrl_slave_blw --component-param=manual_pcs_bonding_comp_cnt=2 --component-param=manual_tx_hssi_aib_bonding_mode=ctrl_master_bot --component-param=manual_tx_hssi_aib_bonding_comp_cnt=6 --component-param=manual_tx_core_aib_bonding_mode=ctrl_master_bot --component-param=manual_tx_core_aib_bonding_comp_cnt=6 --component-param=manual_tx_hssi_aib_indv=indv_dis --component-param=manual_tx_core_aib_indv=indv_dis --component-param=set_cdr_refclk_freq=100.000 --component-param=enable_hip=1 --component-param=enable_hard_reset=1 --component-param=set_hip_cal_en=1 --component-param=hip_mode=user_chnl --component-param=hip_prot_mode=gen2 --component-param=hip_channels=x16 {--component-param=std_tx_byte_ser_mode=Serialize x4} {--component-param=std_rx_byte_deser_mode=Deserialize x4} --component-param=std_tx_8b10b_enable=1 --component-param=std_tx_8b10b_disp_ctrl_enable=1 --component-param=std_rx_8b10b_enable=1 --component-param=std_rx_rmfifo_mode=pipe --component-param=std_rx_rmfifo_pattern_n=192892 --component-param=std_rx_rmfifo_pattern_p=855683 {--component-param=std_rx_word_aligner_mode=synchronous state machine} --component-param=std_rx_word_aligner_pattern_len=10 --component-param=std_rx_word_aligner_pattern=380 --component-param=std_rx_word_aligner_renumber=16 --component-param=std_rx_word_aligner_rgnumber=15 --component-param=enable_ports_pipe_sw=1 --component-param=enable_ports_pipe_rx_elecidle=1 --component-param=enable_ports_pipe_hclk=1 --component-param=tx_fifo_pfull=10 --component-param=rx_fifo_pfull=10 --component-param=enable_port_tx_clkout2=1 --component-param=tx_clkout2_sel=pcs_x2_clkout --component-param=qsf_assignments_enable=1 --component-param=rx_pma_term_sel=r_r4
***************************************************************
Quartus is a registered trademark of Intel Corporation in the
US and other countries.  Portions of the Quartus Prime software
code, and other portions of the code included in this download
or on this DVD, are licensed to Intel Corporation and are the
copyrighted property of third parties. For license details,
refer to the End User License Agreement at

http://fpgasoftware.intel.com/eula.

***************************************************************

2019.08.16.15:12:48 Info: pcie_s10_16x_altera_xcvr_native_s10_htile_1920_3nhmcmq.pcie_s10_16x_altera_xcvr_native_s10_htile_1920_3nhmcmq: The TX PCS-Core Interface FIFO is operating in full-rate transfer mode.
2019.08.16.15:12:48 Info: pcie_s10_16x_altera_xcvr_native_s10_htile_1920_3nhmcmq.pcie_s10_16x_altera_xcvr_native_s10_htile_1920_3nhmcmq: The RX PCS-Core Interface FIFO is operating in full-rate transfer mode.
2019.08.16.15:12:48 Info: pcie_s10_16x_altera_xcvr_native_s10_htile_1920_3nhmcmq.pcie_s10_16x_altera_xcvr_native_s10_htile_1920_3nhmcmq: For the selected device(1SG280HU2F50E2VG), transceiver speed grade is 2 and core speed grade is 2.
2019.08.16.15:12:48 Info: pcie_s10_16x_altera_xcvr_native_s10_htile_1920_3nhmcmq.pcie_s10_16x_altera_xcvr_native_s10_htile_1920_3nhmcmq: For current configuration, TX PCS FIFO depth is "16" and TX Core FIFO depth is "16".
2019.08.16.15:12:48 Info: pcie_s10_16x_altera_xcvr_native_s10_htile_1920_3nhmcmq.pcie_s10_16x_altera_xcvr_native_s10_htile_1920_3nhmcmq: For current configuration, RX PCS FIFO depth is "16" and RX Core FIFO depth is "32".
2019.08.16.15:12:48 Info: pcie_s10_16x_altera_xcvr_native_s10_htile_1920_3nhmcmq.pcie_s10_16x_altera_xcvr_native_s10_htile_1920_3nhmcmq: "PCS clkout" (pcs_clkout) is selected to drive tx_clkout port and the clock frequency is 0.0 MHz.
2019.08.16.15:12:48 Info: pcie_s10_16x_altera_xcvr_native_s10_htile_1920_3nhmcmq.pcie_s10_16x_altera_xcvr_native_s10_htile_1920_3nhmcmq: "PCS clkout x2" (pcs_x2_clkout) is selected to drive tx_clkout2 port and the clock frequency is 0.0 MHz.
2019.08.16.15:12:48 Info: pcie_s10_16x_altera_xcvr_native_s10_htile_1920_3nhmcmq.pcie_s10_16x_altera_xcvr_native_s10_htile_1920_3nhmcmq: "PCS clkout" (pcs_clkout) is selected to drive rx_clkout port and the clock frequency is 0.0 MHz.
2019.08.16.15:12:48 Info: pcie_s10_16x_altera_xcvr_native_s10_htile_1920_3nhmcmq.pcie_s10_16x_altera_xcvr_native_s10_htile_1920_3nhmcmq: A design example cannot be generated for "Tx PLL reference clock frequency"=="125.0" && "Selected CDR reference clock frequency"=="100.000"
2019.08.16.15:12:48 Info: pcie_s10_16x_altera_xcvr_native_s10_htile_1920_3nhmcmq.pcie_s10_16x_altera_xcvr_native_s10_htile_1920_3nhmcmq: Design example cannot be generated for the current configuration. Please check under Design Example tab and system message below for more detailed information.
2019.08.16.15:12:48 Info: pcie_s10_16x_altera_xcvr_native_s10_htile_1920_3nhmcmq.pcie_s10_16x_altera_xcvr_native_s10_htile_1920_3nhmcmq: Note - The external TX PLL IP must be configured with an output clock frequency of 2500.0 MHz.
2019.08.16.15:12:48 Info: Deploying pcie_s10_16x_altera_xcvr_native_s10_htile_1920_3nhmcmq to /tmp/alt8124_4770953449535589358.dir/0005_altera_xcvr_pcie_hip_channel_s10_ch0_gen/pcie_s10_16x_altera_xcvr_native_s10_htile_1920_3nhmcmq.ip
2019.08.16.15:12:49 Info: pcie_s10_16x: "Generating: pcie_s10_16x_altera_xcvr_native_s10_htile_1920_prfyb7y"
2019.08.16.15:12:49 Info: altera_xcvr_pcie_hip_channel_s10_ch1: add_fileset_file ./alt_xcvr_arbiter.sv SYSTEM_VERILOG PATH ../../../../altera_xcvr_generic/ctrl/alt_xcvr_arbiter.sv
2019.08.16.15:12:49 Info: altera_xcvr_pcie_hip_channel_s10_ch1: add_fileset_file ./altera_std_synchronizer_nocut.v VERILOG PATH ../../../../primitives/altera_std_synchronizer/altera_std_synchronizer_nocut.v
2019.08.16.15:12:49 Info: altera_xcvr_pcie_hip_channel_s10_ch1: add_fileset_file ./alt_xcvr_resync_std.sv SYSTEM_VERILOG PATH ../../../alt_xcvr_generic/alt_xcvr_resync_std.sv
2019.08.16.15:12:49 Info: altera_xcvr_pcie_hip_channel_s10_ch1: add_fileset_file ./alt_xcvr_reset_counter_s10.sv SYSTEM_VERILOG PATH ../../../altera_xcvr_reset_control_s10/alt_xcvr_reset_counter_s10.sv
2019.08.16.15:12:49 Info: altera_xcvr_pcie_hip_channel_s10_ch1: add_fileset_file ./altera_xcvr_native_s10_functions_h.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/altera_xcvr_native_s10_functions_h.sv
2019.08.16.15:12:49 Info: altera_xcvr_pcie_hip_channel_s10_ch1: add_fileset_file ./s10_avmm_h.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/s10_avmm_h.sv
2019.08.16.15:12:49 Info: altera_xcvr_pcie_hip_channel_s10_ch1: add_fileset_file ./alt_xcvr_native_avmm_csr.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_avmm_csr.sv
2019.08.16.15:12:49 Info: altera_xcvr_pcie_hip_channel_s10_ch1: add_fileset_file ./alt_xcvr_native_prbs_accum.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_prbs_accum.sv
2019.08.16.15:12:49 Info: altera_xcvr_pcie_hip_channel_s10_ch1: add_fileset_file ./alt_xcvr_native_odi_accel.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_odi_accel.sv
2019.08.16.15:12:49 Info: altera_xcvr_pcie_hip_channel_s10_ch1: add_fileset_file ./alt_xcvr_native_rcfg_arb.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_rcfg_arb.sv
2019.08.16.15:12:49 Info: altera_xcvr_pcie_hip_channel_s10_ch1: add_fileset_file ./alt_xcvr_early_spd_chng_s10_htile.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_early_spd_chng_s10_htile.sv
2019.08.16.15:12:49 Info: altera_xcvr_pcie_hip_channel_s10_ch1: add_fileset_file ./alt_xcvr_native_anlg_reset_seq.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_anlg_reset_seq.sv
2019.08.16.15:12:49 Info: altera_xcvr_pcie_hip_channel_s10_ch1: add_fileset_file ./alt_xcvr_native_dig_reset_seq.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_dig_reset_seq.sv
2019.08.16.15:12:49 Info: altera_xcvr_pcie_hip_channel_s10_ch1: add_fileset_file ./alt_xcvr_native_reset_seq.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_reset_seq.sv
2019.08.16.15:12:49 Info: altera_xcvr_pcie_hip_channel_s10_ch1: add_fileset_file ./alt_xcvr_native_anlg_reset_seq_wrapper.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_anlg_reset_seq_wrapper.sv
2019.08.16.15:12:49 Info: altera_xcvr_pcie_hip_channel_s10_ch1: add_fileset_file ./alt_xcvr_native_re_cal_chnl.v VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_re_cal_chnl.v
2019.08.16.15:12:49 Info: altera_xcvr_pcie_hip_channel_s10_ch1: add_fileset_file ./alt_xcvr_pcie_rx_eios_prot.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_pcie_rx_eios_prot.sv
2019.08.16.15:12:49 Info: altera_xcvr_pcie_hip_channel_s10_ch1: add_fileset_file ./alt_xcvr_native_rx_maib_wa.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_rx_maib_wa.sv
2019.08.16.15:12:49 Info: altera_xcvr_pcie_hip_channel_s10_ch1: Building configuration data for reconfiguration profile 0
ip-deploy --component-name=altera_xcvr_native_s10_htile --output-name=pcie_s10_16x_altera_xcvr_native_s10_htile_1920_prfyb7y --output-directory=/tmp/alt8124_4770953449535589358.dir/0006_altera_xcvr_pcie_hip_channel_s10_ch1_gen --component-param=rcfg_enable=1 --component-param=device=1SG280HU2F50E2VG --component-param=base_device=ND5U {--component-param=device_die_types=HSSI_CRETE2E MAIN_ND5} {--component-param=device_die_revisions=HSSI_CRETE2E_REVB MAIN_ND5_REVC} --component-param=protocol_mode=pipe_g2 --component-param=set_data_rate=5000 --component-param=bonded_mode=pma_pcs --component-param=pcs_reset_sequencing_mode=bonded --component-param=enable_manual_bonding_settings=1 --component-param=manual_pcs_bonding_mode=ctrl_slave_blw --component-param=manual_pcs_bonding_comp_cnt=4 --component-param=manual_tx_hssi_aib_bonding_mode=ctrl_slave_abv --component-param=manual_tx_hssi_aib_bonding_comp_cnt=4 --component-param=manual_tx_core_aib_bonding_mode=ctrl_slave_abv --component-param=manual_tx_core_aib_bonding_comp_cnt=4 --component-param=manual_tx_hssi_aib_indv=indv_dis --component-param=manual_tx_core_aib_indv=indv_dis --component-param=set_cdr_refclk_freq=100.000 --component-param=enable_hip=1 --component-param=enable_hard_reset=1 --component-param=set_hip_cal_en=1 --component-param=hip_mode=user_chnl --component-param=hip_prot_mode=gen2 --component-param=hip_channels=x16 {--component-param=std_tx_byte_ser_mode=Serialize x4} {--component-param=std_rx_byte_deser_mode=Deserialize x4} --component-param=std_tx_8b10b_enable=1 --component-param=std_tx_8b10b_disp_ctrl_enable=1 --component-param=std_rx_8b10b_enable=1 --component-param=std_rx_rmfifo_mode=pipe --component-param=std_rx_rmfifo_pattern_n=192892 --component-param=std_rx_rmfifo_pattern_p=855683 {--component-param=std_rx_word_aligner_mode=synchronous state machine} --component-param=std_rx_word_aligner_pattern_len=10 --component-param=std_rx_word_aligner_pattern=380 --component-param=std_rx_word_aligner_renumber=16 --component-param=std_rx_word_aligner_rgnumber=15 --component-param=enable_ports_pipe_sw=1 --component-param=enable_ports_pipe_rx_elecidle=1 --component-param=enable_ports_pipe_hclk=1 --component-param=tx_fifo_pfull=10 --component-param=rx_fifo_pfull=10 --component-param=enable_port_tx_clkout2=1 --component-param=tx_clkout2_sel=pcs_x2_clkout --component-param=qsf_assignments_enable=1 --component-param=rx_pma_term_sel=r_r4
***************************************************************
Quartus is a registered trademark of Intel Corporation in the
US and other countries.  Portions of the Quartus Prime software
code, and other portions of the code included in this download
or on this DVD, are licensed to Intel Corporation and are the
copyrighted property of third parties. For license details,
refer to the End User License Agreement at

http://fpgasoftware.intel.com/eula.

***************************************************************

2019.08.16.15:13:12 Info: pcie_s10_16x_altera_xcvr_native_s10_htile_1920_prfyb7y.pcie_s10_16x_altera_xcvr_native_s10_htile_1920_prfyb7y: The TX PCS-Core Interface FIFO is operating in full-rate transfer mode.
2019.08.16.15:13:12 Info: pcie_s10_16x_altera_xcvr_native_s10_htile_1920_prfyb7y.pcie_s10_16x_altera_xcvr_native_s10_htile_1920_prfyb7y: The RX PCS-Core Interface FIFO is operating in full-rate transfer mode.
2019.08.16.15:13:12 Info: pcie_s10_16x_altera_xcvr_native_s10_htile_1920_prfyb7y.pcie_s10_16x_altera_xcvr_native_s10_htile_1920_prfyb7y: For the selected device(1SG280HU2F50E2VG), transceiver speed grade is 2 and core speed grade is 2.
2019.08.16.15:13:12 Info: pcie_s10_16x_altera_xcvr_native_s10_htile_1920_prfyb7y.pcie_s10_16x_altera_xcvr_native_s10_htile_1920_prfyb7y: For current configuration, TX PCS FIFO depth is "16" and TX Core FIFO depth is "16".
2019.08.16.15:13:12 Info: pcie_s10_16x_altera_xcvr_native_s10_htile_1920_prfyb7y.pcie_s10_16x_altera_xcvr_native_s10_htile_1920_prfyb7y: For current configuration, RX PCS FIFO depth is "16" and RX Core FIFO depth is "32".
2019.08.16.15:13:12 Info: pcie_s10_16x_altera_xcvr_native_s10_htile_1920_prfyb7y.pcie_s10_16x_altera_xcvr_native_s10_htile_1920_prfyb7y: "PCS clkout" (pcs_clkout) is selected to drive tx_clkout port and the clock frequency is 0.0 MHz.
2019.08.16.15:13:12 Info: pcie_s10_16x_altera_xcvr_native_s10_htile_1920_prfyb7y.pcie_s10_16x_altera_xcvr_native_s10_htile_1920_prfyb7y: "PCS clkout x2" (pcs_x2_clkout) is selected to drive tx_clkout2 port and the clock frequency is 0.0 MHz.
2019.08.16.15:13:12 Info: pcie_s10_16x_altera_xcvr_native_s10_htile_1920_prfyb7y.pcie_s10_16x_altera_xcvr_native_s10_htile_1920_prfyb7y: "PCS clkout" (pcs_clkout) is selected to drive rx_clkout port and the clock frequency is 0.0 MHz.
2019.08.16.15:13:12 Info: pcie_s10_16x_altera_xcvr_native_s10_htile_1920_prfyb7y.pcie_s10_16x_altera_xcvr_native_s10_htile_1920_prfyb7y: A design example cannot be generated for "Tx PLL reference clock frequency"=="125.0" && "Selected CDR reference clock frequency"=="100.000"
2019.08.16.15:13:12 Info: pcie_s10_16x_altera_xcvr_native_s10_htile_1920_prfyb7y.pcie_s10_16x_altera_xcvr_native_s10_htile_1920_prfyb7y: Design example cannot be generated for the current configuration. Please check under Design Example tab and system message below for more detailed information.
2019.08.16.15:13:12 Info: pcie_s10_16x_altera_xcvr_native_s10_htile_1920_prfyb7y.pcie_s10_16x_altera_xcvr_native_s10_htile_1920_prfyb7y: Note - The external TX PLL IP must be configured with an output clock frequency of 2500.0 MHz.
2019.08.16.15:13:12 Info: Deploying pcie_s10_16x_altera_xcvr_native_s10_htile_1920_prfyb7y to /tmp/alt8124_4770953449535589358.dir/0006_altera_xcvr_pcie_hip_channel_s10_ch1_gen/pcie_s10_16x_altera_xcvr_native_s10_htile_1920_prfyb7y.ip
2019.08.16.15:13:13 Info: pcie_s10_16x: "Generating: pcie_s10_16x_altera_xcvr_native_s10_htile_1920_cqbemta"
2019.08.16.15:13:13 Info: altera_xcvr_pcie_hip_channel_s10_ch2: add_fileset_file ./alt_xcvr_arbiter.sv SYSTEM_VERILOG PATH ../../../../altera_xcvr_generic/ctrl/alt_xcvr_arbiter.sv
2019.08.16.15:13:13 Info: altera_xcvr_pcie_hip_channel_s10_ch2: add_fileset_file ./altera_std_synchronizer_nocut.v VERILOG PATH ../../../../primitives/altera_std_synchronizer/altera_std_synchronizer_nocut.v
2019.08.16.15:13:13 Info: altera_xcvr_pcie_hip_channel_s10_ch2: add_fileset_file ./alt_xcvr_resync_std.sv SYSTEM_VERILOG PATH ../../../alt_xcvr_generic/alt_xcvr_resync_std.sv
2019.08.16.15:13:13 Info: altera_xcvr_pcie_hip_channel_s10_ch2: add_fileset_file ./alt_xcvr_reset_counter_s10.sv SYSTEM_VERILOG PATH ../../../altera_xcvr_reset_control_s10/alt_xcvr_reset_counter_s10.sv
2019.08.16.15:13:13 Info: altera_xcvr_pcie_hip_channel_s10_ch2: add_fileset_file ./altera_xcvr_native_s10_functions_h.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/altera_xcvr_native_s10_functions_h.sv
2019.08.16.15:13:13 Info: altera_xcvr_pcie_hip_channel_s10_ch2: add_fileset_file ./s10_avmm_h.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/s10_avmm_h.sv
2019.08.16.15:13:13 Info: altera_xcvr_pcie_hip_channel_s10_ch2: add_fileset_file ./alt_xcvr_native_avmm_csr.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_avmm_csr.sv
2019.08.16.15:13:13 Info: altera_xcvr_pcie_hip_channel_s10_ch2: add_fileset_file ./alt_xcvr_native_prbs_accum.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_prbs_accum.sv
2019.08.16.15:13:13 Info: altera_xcvr_pcie_hip_channel_s10_ch2: add_fileset_file ./alt_xcvr_native_odi_accel.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_odi_accel.sv
2019.08.16.15:13:13 Info: altera_xcvr_pcie_hip_channel_s10_ch2: add_fileset_file ./alt_xcvr_native_rcfg_arb.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_rcfg_arb.sv
2019.08.16.15:13:13 Info: altera_xcvr_pcie_hip_channel_s10_ch2: add_fileset_file ./alt_xcvr_early_spd_chng_s10_htile.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_early_spd_chng_s10_htile.sv
2019.08.16.15:13:13 Info: altera_xcvr_pcie_hip_channel_s10_ch2: add_fileset_file ./alt_xcvr_native_anlg_reset_seq.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_anlg_reset_seq.sv
2019.08.16.15:13:13 Info: altera_xcvr_pcie_hip_channel_s10_ch2: add_fileset_file ./alt_xcvr_native_dig_reset_seq.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_dig_reset_seq.sv
2019.08.16.15:13:13 Info: altera_xcvr_pcie_hip_channel_s10_ch2: add_fileset_file ./alt_xcvr_native_reset_seq.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_reset_seq.sv
2019.08.16.15:13:13 Info: altera_xcvr_pcie_hip_channel_s10_ch2: add_fileset_file ./alt_xcvr_native_anlg_reset_seq_wrapper.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_anlg_reset_seq_wrapper.sv
2019.08.16.15:13:13 Info: altera_xcvr_pcie_hip_channel_s10_ch2: add_fileset_file ./alt_xcvr_native_re_cal_chnl.v VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_re_cal_chnl.v
2019.08.16.15:13:13 Info: altera_xcvr_pcie_hip_channel_s10_ch2: add_fileset_file ./alt_xcvr_pcie_rx_eios_prot.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_pcie_rx_eios_prot.sv
2019.08.16.15:13:13 Info: altera_xcvr_pcie_hip_channel_s10_ch2: add_fileset_file ./alt_xcvr_native_rx_maib_wa.sv SYSTEM_VERILOG PATH ../../altera_xcvr_native_s10/source/alt_xcvr_native_rx_maib_wa.sv
2019.08.16.15:13:13 Info: altera_xcvr_pcie_hip_channel_s10_ch2: Building configuration data for reconfiguration profile 0
ip-deploy --component-name=altera_xcvr_native_s10_htile --output-name=pcie_s10_16x_altera_xcvr_native_s10_htile_1920_cqbemta --output-directory=/tmp/alt8124_4770953449535589358.dir/0007_altera_xcvr_pcie_hip_channel_s10_ch2_gen --component-param=rcfg_enable=1 --component-param=device=1SG280HU2F50E2VG --component-param=base_device=ND5U {--component-param=device_die_types=HSSI_CRETE2E MAIN_ND5} {--component-param=device_die_revisions=HSSI_CRETE2E_REVB MAIN_ND5_REVC} --component-param=protocol_mode=pipe_g2 --component-param=set_data_rate=5000 --component-param=bonded_mode=pma_pcs --component-param=pcs_reset_sequencing_mode=bonded --component-param=enable_manual_bonding_settings=1 --component-param=manual_pcs_bonding_mode=ctrl_slave_blw --component-param=manual_pcs_bonding_comp_cnt=6 --component-param=manual_tx_hssi_aib_bonding_mode=ctrl_slave_abv --component-param=manual_tx_hssi_aib_bonding_comp_cnt=2 --component-param=manual_tx_core_aib_bonding_mode=ctrl_slave_abv --component-param=manual_tx_core_aib_bonding_comp_cnt=2 --component-param=manual_tx_hssi_aib_indv=indv_dis --component-param=manual_tx_core_aib_indv=indv_dis --component-param=set_cdr_refclk_freq=100.000 --component-param=enable_hip=1 --component-param=enable_hard_reset=1 --component-param=set_hip_cal_en=1 --component-param=hip_mode=user_chnl --component-param=hip_prot_mode=gen2 --component-param=hip_channels=x16 {--component-param=std_tx_byte_ser_mode=Serialize x4} {--component-param=std_rx_byte_deser_mode=Deserialize x4} --component-param=std_tx_8b10b_enable=1 --component-param=std_tx_8b10b_disp_ctrl_enable=1 --component-param=std_rx_8b10b_enable=1 --component-param=std_rx_rmfifo_mode=pipe --component-param=std_rx_rmfifo_pattern_n=192892 --component-param=std_rx_rmfifo_pattern_p=855683 {--component-param=std_rx_word_aligner_mode=synchronous state machine} --component-param=std_rx_word_aligner_pattern_len=10 --component-param=std_rx_word_aligner_pattern=380 --component-param=std_rx_word_aligner_renumber=16 --component-param=std_rx_word_aligner_rgnumber=15 --component-param=enable_ports_pipe_sw=1 --component-param=enable_ports_pipe_rx_elecidle=1 --component-param=enable_ports_pipe_hclk=1 --component-param=tx_fifo_pfull=10 --component-param=rx_fifo_pfull=10 --component-param=enable_port_tx_clkout2=1 --component-param=tx_clkout2_sel=pcs_x2_clkout --component-param=qsf_assignments_enable=1 --component-param=rx_pma_term_sel=r_r4

[ The same over and over again... ]

***************************************************************
Quartus is a registered trademark of Intel Corporation in the
US and other countries.  Portions of the Quartus Prime software
code, and other portions of the code included in this download
or on this DVD, are licensed to Intel Corporation and are the
copyrighted property of third parties. For license details,
refer to the End User License Agreement at

http://fpgasoftware.intel.com/eula.

***************************************************************

2019.08.16.15:18:55 Info: pcie_s10_16x_altera_xcvr_native_s10_htile_1920_esxl67i.pcie_s10_16x_altera_xcvr_native_s10_htile_1920_esxl67i: The TX PCS-Core Interface FIFO is operating in half-rate transfer mode.
2019.08.16.15:18:55 Info: pcie_s10_16x_altera_xcvr_native_s10_htile_1920_esxl67i.pcie_s10_16x_altera_xcvr_native_s10_htile_1920_esxl67i: The RX PCS-Core Interface FIFO is operating in half-rate transfer mode.
2019.08.16.15:18:55 Info: pcie_s10_16x_altera_xcvr_native_s10_htile_1920_esxl67i.pcie_s10_16x_altera_xcvr_native_s10_htile_1920_esxl67i: For the selected device(1SG280HU2F50E2VG), transceiver speed grade is 2 and core speed grade is 2.
2019.08.16.15:18:55 Info: pcie_s10_16x_altera_xcvr_native_s10_htile_1920_esxl67i.pcie_s10_16x_altera_xcvr_native_s10_htile_1920_esxl67i: For current configuration, TX PCS FIFO depth is "8" and TX Core FIFO depth is "8".
2019.08.16.15:18:55 Info: pcie_s10_16x_altera_xcvr_native_s10_htile_1920_esxl67i.pcie_s10_16x_altera_xcvr_native_s10_htile_1920_esxl67i: For current configuration, RX PCS FIFO depth is "8" and RX Core FIFO depth is "16".
2019.08.16.15:18:55 Info: pcie_s10_16x_altera_xcvr_native_s10_htile_1920_esxl67i.pcie_s10_16x_altera_xcvr_native_s10_htile_1920_esxl67i: "PCS clkout" (pcs_clkout) is selected to drive tx_clkout port and the clock frequency is 0.0 MHz.
2019.08.16.15:18:55 Info: pcie_s10_16x_altera_xcvr_native_s10_htile_1920_esxl67i.pcie_s10_16x_altera_xcvr_native_s10_htile_1920_esxl67i: "PCS clkout x2" (pcs_x2_clkout) is selected to drive tx_clkout2 port and the clock frequency is 0.0 MHz.
2019.08.16.15:18:55 Info: pcie_s10_16x_altera_xcvr_native_s10_htile_1920_esxl67i.pcie_s10_16x_altera_xcvr_native_s10_htile_1920_esxl67i: "PCS clkout" (pcs_clkout) is selected to drive rx_clkout port and the clock frequency is 0.0 MHz.
2019.08.16.15:18:55 Info: pcie_s10_16x_altera_xcvr_native_s10_htile_1920_esxl67i.pcie_s10_16x_altera_xcvr_native_s10_htile_1920_esxl67i: A design example cannot be generated for "Tx PLL reference clock frequency"=="125.0" && "Selected CDR reference clock frequency"=="100.000"
2019.08.16.15:18:55 Info: pcie_s10_16x_altera_xcvr_native_s10_htile_1920_esxl67i.pcie_s10_16x_altera_xcvr_native_s10_htile_1920_esxl67i: Design example cannot be generated for the current configuration. Please check under Design Example tab and system message below for more detailed information.
2019.08.16.15:18:55 Info: pcie_s10_16x_altera_xcvr_native_s10_htile_1920_esxl67i.pcie_s10_16x_altera_xcvr_native_s10_htile_1920_esxl67i: Note - The external TX PLL IP must be configured with an output clock frequency of 2500.0 MHz.
2019.08.16.15:18:55 Info: Deploying pcie_s10_16x_altera_xcvr_native_s10_htile_1920_esxl67i to /tmp/alt8124_4770953449535589358.dir/0020_altera_xcvr_pcie_hip_channel_s10_ch15_gen/pcie_s10_16x_altera_xcvr_native_s10_htile_1920_esxl67i.ip
2019.08.16.15:18:56 Info: pcie_s10_16x: Done "pcie_s10_16x" with 38 modules, 428 files
2019.08.16.15:18:57 Info: qsys-generate succeeded.
2019.08.16.15:18:57 Info: Finished: Create HDL design files for synthesis
***************************************************************
Quartus is a registered trademark of Intel Corporation in the
US and other countries.  Portions of the Quartus Prime software
code, and other portions of the code included in this download
or on this DVD, are licensed to Intel Corporation and are the
copyrighted property of third parties. For license details,
refer to the End User License Agreement at

http://fpgasoftware.intel.com/eula.

***************************************************************
real	7m28.275s
user	10m8.443s
sys	0m34.967s
]]> https://billauer.se/blog/2019/08/stratix-10-pcie-qsys-generate-infinite-loop/feed/ 0 Intel / Altera: Proper access of the Configuration Space Registers (tl_cfg_ctl) https://billauer.se/blog/2019/08/intel-fpga-configuration-space-registers/ https://billauer.se/blog/2019/08/intel-fpga-configuration-space-registers/#comments Sun, 04 Aug 2019 12:22:10 +0000 eli https://billauer.se/blog/?p=5820 Introduction

The PCIe blocks on Intel (formerly Altera) FPGAs have a somewhat peculiar, yet useful interface for exposing some of the interface’s configuration information, called “Transaction Layer Configuration”. For the purposes of this post, it consists of two output signals, tl_cfg_add[3:0] and tl_cfg_ctl[31:0]. Both are driven by the PCIe block, and clocked by the same clock. The documentation seems to be a bit confused on whether this clock is pld_clk or coreclkout_hip however (even in different versions of the same user guide).

Recall that coreclkout_hip is driven by the PCIe block, and pld_clk is an input to it. The straightforward choice is to connect the pld_clk input to coreclkout_hip, so the PCIe block, as well as the application logic, are both driven by the clock the PCIe block generates. It’s actually not clear to me why anyone would go for a different solution, but the user guide keeps this option open.

So I’ll assume pld_clk and coreclkout_hip are the same signal here. Hence the said confusion in the documentation makes no difference. However it may be hint to why Intel changed the guidelines to interacting with the tl_cfg_add / tl_cfg_ctl pair, probably around the release of Quartus 16.0.

The interface in brief

It’s more or less like a cyclic slide show: tl_cfg_add is incremented every 4th or 8th clock (i.e. pld_clk = coreclkout_hip), and tl_cfg_ctl contains a value that corresponds to the position in some register array, at the address shown in tl_cfg_add. Both change on the same rising edge of the same clock.

This register array appears in the relevant FPGA family’s user guide, has no relation to anything standard, and varies from one FPGA family to another. The data is packed into this 16-word register array in a creative manner at times. The information that can be obtained on an endpoint PCIe interface is in particular the bus address, Max_Payload_Size, Max_Read_Request_Size and if the RCB is 128 bytes. On post-Cyclone IV devices, the data for producing an MSI interrupt can be obtained from this interface as well.

The old API

In older revisions of the user guides (and even the current revision for Cyclone IV), the guideline is to treat tl_cfg_add and tl_cfg_ctl as synchronous signals, so it made perfect sense to go (on Cyclone 10 and several others)

always @(posedge pld_clk)
  case (tl_cfg_add)
    0: cfg_dcommand <= tl_cfg_ctl[31:16];
    2: cfg_lcommand <= tl_cfg_ctl[31:16];
  endcase

The fact that tl_cfg_add dwells a few clocks on each address makes no difference, as tl_cfg_ctl contains the same, correct, value on all of these clock cycles.

The update

In more recent user guides issued by Intel, in particular for Series V and Series 10 FPGAs, the guidelines have changed. Apparently, the timing constraints were not properly applied before Quartus 16.0.1, and one can’t treat tl_cfg_add and tl_cfg_ctl as synchronous signals anymore. Rather, the guidelines require that application logic detects the change in tl_cfg_add’s least significant bit, and then sample both signals with a safe time margin. Without saying it explicitly, the user guides treat these two as signals from an unrelated clock domain.

The fact that both signals remain constant for a fixed number of clock cycles makes it possible to write simple logic that ensures proper sampling.

From a practical point of view, I can testify that the old API works well regardless of the new, stricter, guidelines. It’s not clear whether the sampling mechanism is actually required for proper operation, or if it’s a leftover in the guidelines for Quartus revisions that didn’t enforce the timing constraints properly on the said signals. This way or another, if the user guide requires something, do it. Nevertheless, odds are that FPGA designs already out there, based upon the old API, are still fine.

The new guideline

In short, updated user guides require that the tl_cfg_add and tl_cfg_ctl are sampled in the middle of their time window with stable values. The beginning of each such time window is detected by the application logic by a change in the least significant bit of tl_cfg_add.

There are however a few things to note:

  • The user guides state that the said time window is either 4 clocks or 8 clocks, “depending on the parameterization”, but don’t say how to tell which one applies for a given design.
  • As tl_cfg_add is considered an asynchronous signal, detecting changes on its least significant bit must be done on a register that samples it on each clock, and not comparing directly with tl_cfg_add[0].
  • It’s not possible to sample in the middle of a time window consisting of an even number of clock cycles. In the user guide’s example, the sampling is timed at the clock cycle after the middle of the time window.

The user guide shows sample Verilog code for a clock window of 8 clocks, but doesn’t relate to the 4 clock case.

Verilog code

The following Verilog code can be used to implement the generation of the sampling strobe:

reg [3:0] tl_cfg_add0_d;
reg       strobe;
reg [3:0] counter, prev_counter;

always @(posedge pld_clk)
  begin
    tl_cfg_add0_d <= { tl_cfg_add0_d, tl_cfg_add[0] };

    if (prev_counter > 5)
      strobe <= (tl_cfg_add0_d[2] != tl_cfg_add0_d[3]);
    else
      strobe <= (tl_cfg_add0_d[0] != tl_cfg_add0_d[1]);

    if (tl_cfg_add0_d[0] == tl_cfg_add0_d[1])
      counter <= counter + 1;
    else
      begin
        prev_counter <= counter;
        counter <= 0;
      end
  end

and then this strobe can be used to sample the two signals:

always @(posedge pld_clk)
  if (strobe)
    begin
      tl_cfg_add_samp <= tl_cfg_add;
      tl_cfg_ctl_samp <= tl_cfg_ctl;
    end

The idea is to detect whether the time window is 4 or 8 clock cycles by counting them, and storing the value just before resetting the counter back to zero in prev_counter. For a 4 clock window, it’s expected to be 4, but may also turn out 3 or 5 due to momentary timing glitches. Likewise, prev_counter may turn out either 7, 8 or 9 when an 8 clock window is in effect.

prev_counter is used to select when to assert strobe: If it’s larger than 5, a timing suitable for an 8-clock window is selected. If not, the timing for a 4 clock window. Even though prev_counter may fluctuate from one window to another, it’s not expected to change in a way that alters the selection. Therefore, the fact that prev_counter was measured on one time window, and is used to time the sampling of a another, has no significance. It might as well have been measured on one time window and applied forever afterwards, but that would have required logic that determines when it’s valid.

The sampling instance for a 4-clock time window is two clocks after the change in tl_cfg_add[0], which is consistent with the guideline to sample at the middle of the window (actually, on the closest clock cycle after the middle). For an 8-clock cycle, the delay is 4 clocks, exactly as demonstrated in the examples in the user guides.

Finally, the sampled data can be consumed, e.g.

always @(posedge pld_clk)
  begin
    strobe_d <= strobe;

    if (strobe_d)
      case (tl_cfg_add_samp)
         0: cfg_dcommand <= tl_cfg_ctl_samp[31:16];
         2: cfg_lcommand <= tl_cfg_ctl_samp[31:16];
      endcase
  end

Note that strobe_d is used rather than strobe for consuming that sampled values (even though it would work likewise with strobe, just with a slight delay of the update).

]]> https://billauer.se/blog/2019/08/intel-fpga-configuration-space-registers/feed/ 0 Quartus: The importance of derive_pll_clocks in the SDC file https://billauer.se/blog/2018/09/altera-intel-fpga-derive-pll-clocks-pitfall/ https://billauer.se/blog/2018/09/altera-intel-fpga-derive-pll-clocks-pitfall/#comments Wed, 05 Sep 2018 15:18:54 +0000 eli https://billauer.se/blog/?p=5516 Introduction

Whenever a PLL is used in a design to generate one clock from another, it’s quite common to expect the timing tools to figure out the frequencies and timing relations between the different clocks.

With Intel’s Quartus tools, this isn’t the case by default. A derive_pll_clocks command is required in the SDC constraints file for this happen. And indeed, this command appears in virtually any SDC file that is generated automatically by the tools.

But here’s the scary thing: If derive_pll_clocks is omitted, one would expect that the PLL’s output clocks would not be timed at all, and that the relevant paths would be listed as unconstrained. Unfortunately, it’s different: As shown below, timing calculations are made for these paths, but with wrong figures. So one might get the impression that the timing constraints were met and all is fine, but in fact nothing is assured.

An example

Let’s say that the FPGA has an oscillator input of 48 MHz (hence a period of 20.833 ns), from which a PLL generates a 240 MHz clock (with a period of 4.166 ns).

First let’s take a simple, properly written, SDC file going:

create_clock -name root_clk -period 20.833 [get_ports {osc_clock}]

derive_pll_clocks
derive_clock_uncertainty

Note that the derive_pll_clocks command is there.

Now let’s look at the timing report for a path between two registers, which are clocked by the derived clock. The only interesting part is marked with red:

+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Data Arrival Path                                                                                                                               ;
+---------+----------+----+------+--------+------------------------+------------------------------------------------------------------------------+
; Total   ; Incr     ; RF ; Type ; Fanout ; Location               ; Element                                                                      ;
+---------+----------+----+------+--------+------------------------+------------------------------------------------------------------------------+
; 0.000   ; 0.000    ;    ;      ;        ;                        ; launch edge time                                                             ;
; 4.937   ; 4.937    ;    ;      ;        ;                        ; clock path                                                                   ;
;   0.000 ;   0.000  ;    ;      ;        ;                        ; source latency                                                               ;
;   0.000 ;   0.000  ;    ;      ; 1      ; PIN_B12                ; osc_clock                                                                    ;
;   0.000 ;   0.000  ; RR ; IC   ; 1      ; IOIBUF_X19_Y29_N8      ; osc_clock~input|i                                                            ;
;   0.667 ;   0.667  ; RR ; CELL ; 2      ; IOIBUF_X19_Y29_N8      ; osc_clock~input|o                                                            ;
;   2.833 ;   2.166  ; RR ; IC   ; 1      ; PLL_3                  ; clkrst_ins|altpll_component|auto_generated|pll1|inclk[0]                     ;
;   1.119 ;   -1.714 ; RR ; COMP ; 1      ; PLL_3                  ; clkrst_ins|altpll_component|auto_generated|pll1|observablevcoout             ;
;   1.119 ;   0.000  ; RR ; CELL ; 1      ; PLL_3                  ; clkrst_ins|altpll_component|auto_generated|pll1|clk[0]                       ;
;   3.274 ;   2.155  ; RR ; IC   ; 1      ; CLKCTRL_G13            ; clkrst_ins|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
;   3.274 ;   0.000  ; RR ; CELL ; 8      ; CLKCTRL_G13            ; clkrst_ins|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
;   4.336 ;   1.062  ; RR ; IC   ; 1      ; FF_X40_Y24_N27         ; clkrst_ins|main_state[0]|clk                                                 ;
;   4.937 ;   0.601  ; RR ; CELL ; 1      ; FF_X40_Y24_N27         ; clkrst:clkrst_ins|main_state[0]                                              ;
; 6.774   ; 1.837    ;    ;      ;        ;                        ; data path                                                                    ;
;   5.169 ;   0.232  ;    ; uTco ; 1      ; FF_X40_Y24_N27         ; clkrst:clkrst_ins|main_state[0]                                              ;
;   5.169 ;   0.000  ; FF ; CELL ; 5      ; FF_X40_Y24_N27         ; clkrst_ins|main_state[0]|q                                                   ;
;   5.591 ;   0.422  ; FF ; IC   ; 1      ; LCCOMB_X40_Y24_N24     ; clkrst_ins|Equal1~0|dataa                                                    ;
;   6.002 ;   0.411  ; FR ; CELL ; 1      ; LCCOMB_X40_Y24_N24     ; clkrst_ins|Equal1~0|combout                                                  ;
;   6.370 ;   0.368  ; RR ; IC   ; 1      ; DDIOOUTCELL_X41_Y24_N4 ; clkrst_ins|the_register|d                                                    ;
;   6.774 ;   0.404  ; RR ; CELL ; 1      ; DDIOOUTCELL_X41_Y24_N4 ; clkrst:clkrst_ins|the_register                                               ;
+---------+----------+----+------+--------+------------------------+------------------------------------------------------------------------------+

+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Data Required Path                                                                                                                              ;
+---------+----------+----+------+--------+------------------------+------------------------------------------------------------------------------+
; Total   ; Incr     ; RF ; Type ; Fanout ; Location               ; Element                                                                      ;
+---------+----------+----+------+--------+------------------------+------------------------------------------------------------------------------+
; 4.166   ; 4.166    ;    ;      ;        ;                        ; latch edge time                                                              ;
; 9.005   ; 4.839    ;    ;      ;        ;                        ; clock path                                                                   ;
;   4.166 ;   0.000  ;    ;      ;        ;                        ; source latency                                                               ;
;   4.166 ;   0.000  ;    ;      ; 1      ; PIN_B12                ; osc_clock                                                                    ;
;   4.166 ;   0.000  ; RR ; IC   ; 1      ; IOIBUF_X19_Y29_N8      ; osc_clock~input|i                                                            ;
;   4.833 ;   0.667  ; RR ; CELL ; 2      ; IOIBUF_X19_Y29_N8      ; osc_clock~input|o                                                            ;
;   6.912 ;   2.079  ; RR ; IC   ; 1      ; PLL_3                  ; clkrst_ins|altpll_component|auto_generated|pll1|inclk[0]                     ;
;   5.119 ;   -1.793 ; RR ; COMP ; 1      ; PLL_3                  ; clkrst_ins|altpll_component|auto_generated|pll1|observablevcoout             ;
;   5.119 ;   0.000  ; RR ; CELL ; 1      ; PLL_3                  ; clkrst_ins|altpll_component|auto_generated|pll1|clk[0]                       ;
;   7.187 ;   2.068  ; RR ; IC   ; 1      ; CLKCTRL_G13            ; clkrst_ins|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
;   7.187 ;   0.000  ; RR ; CELL ; 8      ; CLKCTRL_G13            ; clkrst_ins|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
;   8.199 ;   1.012  ; RR ; IC   ; 1      ; DDIOOUTCELL_X41_Y24_N4 ; clkrst_ins|the_register|clk                                                  ;
;   8.736 ;   0.537  ; RR ; CELL ; 1      ; DDIOOUTCELL_X41_Y24_N4 ; clkrst:clkrst_ins|the_register                                               ;
;   9.005 ;   0.269  ;    ;      ;        ;                        ; clock pessimism removed                                                      ;
; 8.985   ; -0.020   ;    ;      ;        ;                        ; clock uncertainty                                                            ;
; 8.890   ; -0.095   ;    ; uTsu ; 1      ; DDIOOUTCELL_X41_Y24_N4 ; clkrst:clkrst_ins|the_register                                               ;
+---------+----------+----+------+--------+------------------------+------------------------------------------------------------------------------+

Aside from all the mumbo-jumbo, there’s the “latch edge time” line, which is the time of the edge of the clock that will propagate through the clock network and become the latching clock on the receiving register. As this is the case of a plain register-to-register path, both clocked with the rising edge of the same clock, the “latch edge time” is simply the clock’s period. Indeed 4.166 ns. So far so good.

But then disaster

Let’s see what happens if the derive_pll_clocks command is omitted. In other words, the SDC file reads:

create_clock -name root_clk -period 20.833 [get_ports {osc_clock}]

derive_clock_uncertainty

For exactly the same path, the timing report reads:

+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Data Arrival Path                                                                                                                               ;
+---------+----------+----+------+--------+------------------------+------------------------------------------------------------------------------+
; Total   ; Incr     ; RF ; Type ; Fanout ; Location               ; Element                                                                      ;
+---------+----------+----+------+--------+------------------------+------------------------------------------------------------------------------+
; 0.000   ; 0.000    ;    ;      ;        ;                        ; launch edge time                                                             ;
; 4.937   ; 4.937    ;    ;      ;        ;                        ; clock path                                                                   ;
;   0.000 ;   0.000  ;    ;      ;        ;                        ; source latency                                                               ;
;   0.000 ;   0.000  ;    ;      ; 1      ; PIN_B12                ; osc_clock                                                                    ;
;   0.000 ;   0.000  ; RR ; IC   ; 1      ; IOIBUF_X19_Y29_N8      ; osc_clock~input|i                                                            ;
;   0.667 ;   0.667  ; RR ; CELL ; 2      ; IOIBUF_X19_Y29_N8      ; osc_clock~input|o                                                            ;
;   2.833 ;   2.166  ; RR ; IC   ; 1      ; PLL_3                  ; clkrst_ins|altpll_component|auto_generated|pll1|inclk[0]                     ;
;   1.119 ;   -1.714 ; RR ; COMP ; 1      ; PLL_3                  ; clkrst_ins|altpll_component|auto_generated|pll1|observablevcoout             ;
;   1.119 ;   0.000  ; RR ; CELL ; 1      ; PLL_3                  ; clkrst_ins|altpll_component|auto_generated|pll1|clk[0]                       ;
;   3.274 ;   2.155  ; RR ; IC   ; 1      ; CLKCTRL_G13            ; clkrst_ins|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
;   3.274 ;   0.000  ; RR ; CELL ; 8      ; CLKCTRL_G13            ; clkrst_ins|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
;   4.336 ;   1.062  ; RR ; IC   ; 1      ; FF_X40_Y24_N19         ; clkrst_ins|main_state[0]|clk                                                 ;
;   4.937 ;   0.601  ; RR ; CELL ; 1      ; FF_X40_Y24_N19         ; clkrst:clkrst_ins|main_state[0]                                              ;
; 6.765   ; 1.828    ;    ;      ;        ;                        ; data path                                                                    ;
;   5.169 ;   0.232  ;    ; uTco ; 1      ; FF_X40_Y24_N19         ; clkrst:clkrst_ins|main_state[0]                                              ;
;   5.169 ;   0.000  ; FF ; CELL ; 5      ; FF_X40_Y24_N19         ; clkrst_ins|main_state[0]|q                                                   ;
;   5.583 ;   0.414  ; FF ; IC   ; 1      ; LCCOMB_X40_Y24_N24     ; clkrst_ins|Equal1~0|datab                                                    ;
;   5.994 ;   0.411  ; FR ; CELL ; 1      ; LCCOMB_X40_Y24_N24     ; clkrst_ins|Equal1~0|combout                                                  ;
;   6.361 ;   0.367  ; RR ; IC   ; 1      ; DDIOOUTCELL_X41_Y24_N4 ; clkrst_ins|the_register|d                                                    ;
;   6.765 ;   0.404  ; RR ; CELL ; 1      ; DDIOOUTCELL_X41_Y24_N4 ; clkrst:clkrst_ins|the_register                                               ;
+---------+----------+----+------+--------+------------------------+------------------------------------------------------------------------------+

+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Data Required Path                                                                                                                               ;
+----------+----------+----+------+--------+------------------------+------------------------------------------------------------------------------+
; Total    ; Incr     ; RF ; Type ; Fanout ; Location               ; Element                                                                      ;
+----------+----------+----+------+--------+------------------------+------------------------------------------------------------------------------+
; 20.833   ; 20.833   ;    ;      ;        ;                        ; latch edge time                                                              ;
; 25.672   ; 4.839    ;    ;      ;        ;                        ; clock path                                                                   ;
;   20.833 ;   0.000  ;    ;      ;        ;                        ; source latency                                                               ;
;   20.833 ;   0.000  ;    ;      ; 1      ; PIN_B12                ; osc_clock                                                                    ;
;   20.833 ;   0.000  ; RR ; IC   ; 1      ; IOIBUF_X19_Y29_N8      ; osc_clock~input|i                                                            ;
;   21.500 ;   0.667  ; RR ; CELL ; 2      ; IOIBUF_X19_Y29_N8      ; osc_clock~input|o                                                            ;
;   23.579 ;   2.079  ; RR ; IC   ; 1      ; PLL_3                  ; clkrst_ins|altpll_component|auto_generated|pll1|inclk[0]                     ;
;   21.786 ;   -1.793 ; RR ; COMP ; 1      ; PLL_3                  ; clkrst_ins|altpll_component|auto_generated|pll1|observablevcoout             ;
;   21.786 ;   0.000  ; RR ; CELL ; 1      ; PLL_3                  ; clkrst_ins|altpll_component|auto_generated|pll1|clk[0]                       ;
;   23.855 ;   2.069  ; RR ; IC   ; 1      ; CLKCTRL_G13            ; clkrst_ins|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
;   23.855 ;   0.000  ; RR ; CELL ; 8      ; CLKCTRL_G13            ; clkrst_ins|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
;   24.867 ;   1.012  ; RR ; IC   ; 1      ; DDIOOUTCELL_X41_Y24_N4 ; clkrst_ins|the_register|clk                                                  ;
;   25.404 ;   0.537  ; RR ; CELL ; 1      ; DDIOOUTCELL_X41_Y24_N4 ; clkrst:clkrst_ins|the_register                                               ;
;   25.672 ;   0.268  ;    ;      ;        ;                        ; clock pessimism removed                                                      ;
; 25.572   ; -0.100   ;    ;      ;        ;                        ; clock uncertainty                                                            ;
; 25.477   ; -0.095   ;    ; uTsu ; 1      ; DDIOOUTCELL_X41_Y24_N4 ; clkrst:clkrst_ins|the_register                                               ;
+----------+----------+----+------+--------+------------------------+------------------------------------------------------------------------------+

So it’s exactly the same analysis, only assuming that the clock period is 20.833 ns (note the “latch edge time” again). Note that the analysis traverses the PLL, but simply ignores the fact that the PLL’s output has another frequency. It’s as if the tools were saying: You forgot the derive_pll_clocks constraint? No problem. We’ll play as if the PLL’s input clock went right through it.

Frankly, I can’t think about a single case where this behavior would make sense. Either don’t calculate the timing of paths of the derived clock, or do it correctly. But just throwing in the original clock’s period? These incorrectly constrained paths don’t appear in the unconstrained path summary, nor is there any other indication that the timing is horribly wrong.

To the tools’ defense, the timing analysis produces warnings on this matter, but none at a Critical level, so it’s easy to miss them in the sea of warnings that FPGA tools always generate.

Bottom line

  • Make sure your design has the derive_pll_clocks command if you have a PLL involved (unless you’ve added explicit constraints for the derived clocks)
  • Be sure to generate a timing report, to read and understand it.
  • Always test your constraints by requiring impossible values, and verify that the failing paths are calculated correctly
]]> https://billauer.se/blog/2018/09/altera-intel-fpga-derive-pll-clocks-pitfall/feed/ 1 PCIe on Cyclone 10 GX: Data loss on DMA writes by FPGA https://billauer.se/blog/2018/08/cyclone-10-gx-pcie-problems/ https://billauer.se/blog/2018/08/cyclone-10-gx-pcie-problems/#comments Wed, 15 Aug 2018 17:48:51 +0000 eli https://billauer.se/blog/?p=5495 TL;DR

DMA writes from a Cyclone 10 GX PCIe interface may be lost, probably due to a path that isn’t timed properly by the fitter. This has been observed with Quartus Prime Version 17.1.0 Build 240 SJ Pro Edition, and the official Cyclone 10 GX development board. A wider impact is likely, possibly on Arria 10 device as well (as its PCIe block is the same one).

The problem seems to be rare, and appears and disappears depending on how the fitter places the logic. It’s however fairly easy to diagnose if this specific problem is in effect (see “The smoking gun” below).

Computer hardware: Gigabyte GA-B150M-D2V motherboard (with an Intel B150 Chipset) + Intel i5-6400 CPU.

The story

It started with a routine data transport test (FPGA to host), which failed virtually immediately (that is, after a few kilobytes). It was apparent that some portions of data simply weren’t written into the DMA buffer by the FPGA.

So I tried a fix in my own code, and yep, it helped. Or so I thought. Actually, anything I changed seemed to fix the problem. In the end, I changed nothing, but just added

set_global_assignment -name SEED 2

to the QSF file. Which only changes the fitter’s initial placement of the logic elements, which eventually leads to an alternative placement and routing of the design. That should work exactly the same, of course. But it “solved the problem”.

This was consistent: One “magic” build that failed consistently, and any change whatsoever made the issue disappear.

The design was properly constrained, of course, as shown in the development board’s sample SDC file. In fact, there isn’t much to constrain: It’s just setting the main clock to 100 MHz, derive_pll_clocks and derive_clock_uncertainty. And a false path from the PERST pin.

So maybe my bad? Well, no. There were no unconstrained paths in the entire design (with these simple constraints), so one fitting of the design should be exactly like any other. Maybe my application logic? No again:

The smoking gun

The final nail in the coffin was when I noted errors in the PCIe Device Status Registers on both sides. I’ve discussed this topic in this and this other posts of mine, however in the current case no AER kernel messages were produced (unfortunately, and it’s not clear why).

And whatever the application code does, Intel / Altera’s PCIe block shouldn’t produce a link error, and neither it does normally. It’s a violation of the PCIe spec.

These are the steps for observing this issue on a Linux machine. First, find out who the link partners are:

$ lspci
00:00.0 Host bridge: Intel Corporation Device 191f (rev 07)
00:01.0 PCI bridge: Intel Corporation Device 1901 (rev 07)
[ ... ]
01:00.0 Unassigned class [ff00]: Altera Corporation Device ebeb

and then figuring out that the FPGA card is connected via the bridge at 00:01.0 with

$ lspci -t
-[0000:00]-+-00.0
           +-01.0-[01]----00.0

So it’s between 00:01.0 and 01:00.0. Then, following that post of mine, using setpci to read from the status register to tell an error had occurred.

First, what it should look like: With any bitstream except that specific faulty one, I got

# setpci -s 01:00.0 CAP_EXP+0xa.w
0000
# setpci -s 00:01.0 CAP_EXP+0xa.w
0000

any time and all the time, which says the obvious: No errors sensed on either side.

But with the bitstream that had data losses, before any communication had taken place (except for the driver being loaded):

# setpci -s 01:00.0 CAP_EXP+0xa.w
0009
# setpci -s 00:01.0 CAP_EXP+0xa.w
0000

Non-zero means error. So at this stage the FPGA’s PCIe interface was unhappy with something (more on that below), but the processor’s side had no complaints.

I have to admit that I’ve seen the 0009 status in a lot of other tests, in which communication went through perfectly. So even though reflects some kind of error, it doesn’t necessarily predict any functional fault. As elaborated below, the 0009 status consists of correctable errors. It’s just that such errors are normally never seen (i.e. with any PCIe card that works properly).

Anyhow, back to the bitstream that did have data errors. After some data had been written by the FPGA:

# setpci -s 01:00.0 CAP_EXP+0xa.w
0009
# setpci -s 00:01.0 CAP_EXP+0xa.w
000a

In this case, the FPGA card’s link partner complained. To save ourselves the meaning of these numbers (even though the’re listed in that post), use lspci -vv:

# lspci -vv
00:01.0 PCI bridge: Intel Corporation Device 1901 (rev 07) (prog-if 00 [Normal decode])
[ ... ]
        Capabilities: [a0] Express (v2) Root Port (Slot+), MSI 00
                DevCap: MaxPayload 256 bytes, PhantFunc 0
                        ExtTag- RBE+
                DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
                        RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
                        MaxPayload 256 bytes, MaxReadReq 128 bytes
                DevSta: CorrErr- UncorrErr+ FatalErr- UnsuppReq+ AuxPwr- TransPend-
[ ... ]

So the bridge complained about an uncorrectable and an unsupported request only after the data transmission, but the FPGA side:

01:00.0 Unassigned class [ff00]: Altera Corporation Device ebeb
[ ... ]
        Capabilities: [80] Express (v2) Endpoint, MSI 00
                DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us
                        ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
                DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
                        RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
                        MaxPayload 256 bytes, MaxReadReq 512 bytes
                DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend-

complained about a correctable error and an unsupported request (as seen above, that happened before any payload transmission).

Low-level errors. I couldn’t make this happen even if I wanted to.

Aftermath

The really bad news is that this problem isn’t in the logic itself, but in how it’s placed. It seems to be a rare and random occurrence of a poor job done by the fitter. Or maybe it’s not all that rare, if you let the FPGA heat up a bit. In my case a spinning fan kept an almost idle FPGA quite cool, I suppose.

The somewhat good news is that the data loss comes with these PCIe status errors, and maybe with the relevant kernel messages (not clear why I didn’t see any). So there’s something to hold on to.

And I should also mention that the offending PCIe interface was a Gen2 x 4 running with a 64-bit interface at 250 MHz. which a rather marginal frequency for Arria 10 / Cyclone 10. So going with the speculation that this is a timing issue that isn’t handled properly by the fitter, maybe sticking to 125 MHz interfaces on these devices is good enough to be safe against this issue.

Note to self: The outputs are kept in cyclone10-failure.tar.gz

]]> https://billauer.se/blog/2018/08/cyclone-10-gx-pcie-problems/feed/ 0 Quartus / Linux: Programming the FPGA with command-line https://billauer.se/blog/2018/08/altera-intel-fpga-command-line-jtag/ https://billauer.se/blog/2018/08/altera-intel-fpga-command-line-jtag/#comments Sun, 12 Aug 2018 18:57:26 +0000 eli https://billauer.se/blog/?p=5487 Command-line?

Yes, it much more convenient than the GUI programmer. Programming an FPGA is a repeated task, always the same file to the same FPGA on the same board connected to the computer. And somehow the GUI programming tools turn it into a daunting ceremony (and sometimes even a quiz, when it can’t tell exactly which device is connected, so I’m supposed to nail the exact one).

With command line its literally picking the command from bash history, and press Enter. And surprisingly enough, the command line tool doesn’t ask the silly questions that the GUI tool does.

First, some mucking about

Set up the environment:

$ /path/to/quartus/15.1/nios2eds/nios2_command_shell.sh

To list all devices found (cable auto-detected):

$ quartus_pgm --auto
Info: *******************************************************************
Info: Running Quartus Prime Programmer
    Info: Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition
    Info: Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
[ ... ]
    Info: agreement for further details.
    Info: Processing started: Sun May 27 15:06:22 2018
Info: Command: quartus_pgm --auto
Info (213045): Using programming cable "USB-BlasterII [2-5.1]"
1) USB-BlasterII [2-5.1]
  02B040DD   5CGTFD9(A5|C5|D5|E5)/..
  020A40DD   5M2210Z/EPM2210

[ ... ]

Note that listing the devices as shown above is not necessary for programming. It might be useful to tell the position of the FPGA in the JTAG chain, maybe. Really something that is done once to explore the board.

jtagd

It’s important to be aware of this deamon, which listens to TCP/IP port 1309: It’s responsible for talking with the JTAG adapter through the USB bus, so both the GUI and command line programmer utilities rely on it. If there’s no daemon running, both of these launch it.

But if you use multiple versions of Quartus, this may be a source of confusion, in particular if you make a first attempt to program an FPGA with an older version, and then try a newer one. That’s because the newer version of Quartus will keep using the older version of jtagd, possibly failing to work with recent devices. Bottom line: If wonky things happen, this won’t hurt:

$ killall jtagd

Programming

quartus_pgm displays most of its output in green. Generally speaking, if there’s no red text, all went fine.

$ quartus_pgm -m jtag -o "p;path/to/file.sof"

Or add the position in the JTAG explicitly (in particular if it’s not the first device). In this case it’s @1, meaning it’s the first device in the JTAG chain. If it’s the second device, pick @2 etc.

$ quartus_pgm -m jtag -o "p;path/to/file.sof@1"
Info: *******************************************************************
Info: Running Quartus Prime Programmer
    Info: Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition
    Info: Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
    Info: Your use of Altera Corporation's design tools, logic functions
    Info: and other software and tools, and its AMPP partner logic
    Info: functions, and any output files from any of the foregoing
    Info: (including device programming or simulation files), and any
    Info: associated documentation or information are expressly subject
    Info: to the terms and conditions of the Altera Program License
    Info: Subscription Agreement, the Altera Quartus Prime License Agreement,
    Info: the Altera MegaCore Function License Agreement, or other
    Info: applicable license agreement, including, without limitation,
    Info: that your use is for the sole purpose of programming logic
    Info: devices manufactured by Altera and sold by Altera or its
    Info: authorized distributors.  Please refer to the applicable
    Info: agreement for further details.
    Info: Processing started: Sun May 27 15:35:02 2018
Info: Command: quartus_pgm -m jtag -o p;path/to/file.sof@1
Info (213045): Using programming cable "USB-BlasterII [2-5.1]"
Info (213011): Using programming file p;path/to/file.sof@1 with checksum 0x061958E1 for device 5CGTFD9E5F35@1
Info (209060): Started Programmer operation at Sun May 27 15:35:05 2018
Info (209016): Configuring device index 1
Info (209017): Device 1 contains JTAG ID code 0x02B040DD
Info (209007): Configuration succeeded -- 1 device(s) configured
Info (209011): Successfully performed operation(s)
Info (209061): Ended Programmer operation at Sun May 27 15:35:09 2018
Info: Quartus Prime Programmer was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 432 megabytes
    Info: Processing ended: Sun May 27 15:35:09 2018
    Info: Elapsed time: 00:00:07
    Info: Total CPU time (on all processors): 00:00:03

If anything goes wrong — device mismatch, a failure to scan the JTAG chain or whatever, it will be hard to miss because of the errors written in red. The sweet thing with the command line interface is that every attempt starts from fresh, so just turn the board on (the usual reason for errors) and give it another go.

Cyclone 10 GX FPGA development kit

This board caused me some extra trouble, so a few words about it. When connected, it appears as 09fb:6810, however after attempting to program the FPGA (note the “@2″ in the end) with

$ quartus_pgm -m jtag -o "p;thecode.sof@2"
Error (213019): Can't scan JTAG chain. Error code 86.

it changes to 09fb:6010. So there’s clearly some reprogramming of firmware (the log shows a disconnection and reconnection with the new ID). The board is detected as GX0000406 by the Quartus GUI Programming Tool, but clicking “Auto Detect” yields “Unable to scan device chain. Hardware is not connected”.

OK, what about a scan?

$ quartus_pgm --auto
[ ... ]
Info (213045): Using programming cable "10CGX0000406 [1-5.1.2]"
1) 10CGX0000406 [1-5.1.2]
  Unable to read device chain - Hardware not attached

The problem in my case was apparently that the jtagd running was launched by an older version of Quartus, which didn’t recognize Cyclone 10 devices. So follow the advice above, and kill it. After that, programming with the command above worked with Quartus Pro 17.1:

$ quartus_pgm --auto
[...]
Info (213045): Using programming cable "USB-BlasterII [1-5.1.2]"
1) USB-BlasterII [1-5.1.2]
  031820DD   10M08SA(.|ES)/10M08SC
  02E120DD   10CX220Y
]]> https://billauer.se/blog/2018/08/altera-intel-fpga-command-line-jtag/feed/ 2 Quartus / sdc: Constraining I/O ports clocked by an internal clock https://billauer.se/blog/2018/08/quartus-sdc-constraining-pins-derived-clock/ https://billauer.se/blog/2018/08/quartus-sdc-constraining-pins-derived-clock/#comments Sun, 05 Aug 2018 07:37:09 +0000 eli https://billauer.se/blog/?p=5474 Introduction

This post is an expansion for another post of mine, which deals with register I/O packing. It’s recommended reading that one first.

Timing constraining of I/O ports is typically intended to ensure timing relations between an external clock and the timing of signals that are clocked by this clock (or derived from this clock, with the same frequency or a simple relation to it).

However in some cases the clock of the I/O registers is generated with an PLL within the FPGA, and is practically unrelated to the originating clock. There are still good reasons to constrain the timing of such ports, among others:

  • Even though the external clock source isn’t involved directly, the timing must still be under control. In particular, when the interface with an external device is bidirectional, the timing of the signals arriving from the device depend on those being generated by the FPGA going to it. Constraining the ports is part of ensuring that this timing loop is fast enough.
  • Ensuring that I/O registers are used. Tight constraints, which can only be met with I/O registers will fail if the tools don’t pack those registers as desired.
  • Ensuring that no delay is inserted by the tools between the input pad and the register.

Clearly, nobody at Altera thought that this kind of constraining was necessary. Consequently, getting this done in a fairly clean manner is nontrivial, to say the least (yours truly wasted a full week of work to figure this out). This post suggests a methodology which is hopefully the clean enough. This is the best I managed to work out, anyhow.

The relevant documentation:

The Intel / Altera toolset used is Quartus Prime 15.1 (Web Edition).

The goal

The naïve approach is to apply set_input_delay and set_output_delay to the output ports as usual, using the clock from the PLL in the -clock argument. Even so, the tools interpret this as constraining the timing relative to the external clock, which is inherently pointless, since this relation has no meaning. To make things worse, if the clock frequency relations aren’t a plain ratio, the timing requirements become unreal, as the closest clock edge relations between the two clocks are applied as the worst case. So this doesn’t work at all.

Ideally, we’d like to constrain only the path between the I/O pin and the register connected directly to it. It appears like there’s no way to do that exactly, as Quartus’ Timing Analyzer automatically mixes in the clock’s path delay when there’s a register involved.

So the goal is to define the delay between the external pin and the register that samples its state or vice versa, with as little interference as possible.

A sample set of constraints

This is the sdc file that worked for me. Each part is explained in detail afterwards.

create_clock -name root_clk -period 20.833 [get_ports {osc_clock}]

# The 60 MHz clock is defined on the global clock buffer's output pin:
create_clock -name main_clk -period 16.666 [get_pins {clkrst_ins|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk}]

set_clock_groups -asynchronous -group [ get_clocks root_clk ] \
    -group [ get_clocks main_clk ]

set_annotated_delay -from clkrst_ins|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk 0

derive_pll_clocks
derive_clock_uncertainty

set_false_path -hold -from [get_ports pixadc_*] -to [get_registers]
set_false_path -hold -from [get_registers] -to [get_ports pixadc_*]

set_max_delay -from [get_registers] -to [get_ports pixadc_*] 2.7
set_max_delay -from [get_ports pixadc_*] -to [get_registers] 0.7

create_clock assignments

In the relevant design, the external clock source runs at 48 MHz (20.833 ns period) and there’s a PLL on the FPGA generating a 60 MHz clock (16.666 ns period) based upon the external clock.

First and somewhat unrelated, note that neither the duty cycle nor the waveform attributes are given in these definitions. If the duty cycle is 50%, don’t add that rubbish. It’s the default anyhow, but is nevertheless added by the automatic constraint generator.

The definition of root_clk is quite standard. But pay attention to the way the derived clock, main_clk is defined. Not only isn’t it given as a derived clock from root_clk (or I could have relied on an automatic derivation made with “derive_pll_clocks”), but it’s assigned to the PLL’s output pin. It’s not a coincidence: That specific “get_pins” format is mandatory in the create_clock definition, or the PLL’s input-to-output delay is included (around 2 ns). For example, even

create_clock -name main_clk -period 16.666 clkrst_ins|altpll_component|auto_generated|wire_pll1_clk[0]

(which is what the tools would generate automatically with derive_pll_clocks) will include the delay from inclk[0], even though the identifier given in the constraint is the one of the PLL’s output net. This is also the case if the net is referred to with “get_nets”. Only being specific with get_pins on the PLL’s output pins clarifies that the clock delay should start at the output of the PLL.

A peculiar thing is that the fitter issues a warnings like

Warning (332049): Ignored create_clock at test.sdc: Argument <targets> is an empty collection File: ...
 Info (332050): create_clock -name main_clk -period 16.666 [get_pins {clkrst_ins|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk}] File: ...

and main_clk does indeed not appear in the list of clocks made by the fitter, even though the constraint’s effect is clear in the timing analysis made by the timing analyzer.

As shown below, the clock path is included in the timing calculation, no matter what. So this is one of the necessities for keeping that interference in the timing calculations minimal.

IMPORTANT: Setting the clock constraint on the PLL’s output pin as shown above, as well as the set_annotated_delay constraint, disrupt the constraining of register-to-register paths slightly, as the original, rigorous timing calculation assumes that the destination register receives the clock slightly earlier than the source register (presumably to represent a worst-case scenario involving global clock skew and other effects). It’s therefore recommended to compare the timing difference between the clock paths with the clock constraint made the classic way, and deduce this difference from the clock’s period, to ensure an accurate calculation. It should be no more than a few hundred picoseconds.

Ah, and another things I tried but lead nowhere: In the Handbook, it says that a virtual clock can be defined with something like

create_clock -name main_clk -period 16.666

In other words, this is a clock that can be mentioned in constraints, but has no signal in the FPGA related to it. My original thought that if this clock doesn’t relate to anything real, it won’t have any global clock delay in its timing calculations.

But trying it, constraining I/O pins with the virtual clock as the -clock argument, no timing calculations were made at all. The timing report ended up with “Nothing to report”. So the virtual clock concept didn’t help.

set_clock_groups

Nothing special about this. Just declaring that root_clk and main_clk should be considered unrelated (all paths between these clock domains are false).

set_annotated_delay

This command tells Timing Analyzer to consider the delay of the global clock buffer as zero. This is yet another necessity to keep unrelated delays out of the calculation.

Together with the definition of main_clk above, which relates the timed clock to the PLL’s output, the delay of the global clock network in the FPGA fabric is left out of the calculations. As shown below, there’s still a clock delay component that is counted in, but it’s presumably the delay of the clock within the logic element.

As the clock’s delay is left out, it doesn’t matter if the PLL is set to compensate for the global clock delay or not; the same timing is achieved either way. One could, by the way, argue that the PLL’s clock timing compensation is an alternative way to minimize the clock path’s role in the timing calculations. My own attempts to go down that road have however led to nothing else than a lot of wasted time. Note that in order to make sense of the PLL’s timing compensation, the commonplace create_clock definition must be used for main_clk, so the PLL’s own delay is included (it’s compensated for further down the road), and this leads to a total lack of control of what’s timed and what is not.

derive_pll_clocks and derive_clock_uncertainty

derive_pll_clocks is applied even though main_clk is defined explicitly with a create_clock constraint, and the latter overrides the clock generated by derive_pll_clocks. But since the create_clock statement for main_clk is ignored by the synthesizer as well as the fitter (because the relevant pin isn’t found), derive_pll_clocks is necessary during these stages to ensure that the relevant paths are timed. In particular, that the fitter makes sure that register-to-register paths meet timing.

If the clock period given in the create_clock constraint is shorter than the one derived from the PLL (which is recommended for reasons mentioned in this post), there might a situation where timing fails because the fitter didn’t attempt to meet a constraint it was blind to. Or at least theoretically. I’ve never encountered anything like this, partly because it’s quite difficult to fail on a 60 MHz clock.

derive_clock_uncertainty is used, as with any proper set of constraints.

set_max_delay

Finally, the delay constraints themselves. set_max_delay is used rather than set_input_delay and set_output_delay, mainly because set_max_delay expresses the element we want to constrain: A segment between the register and a port. As outlined in this other post of mine, set_input_delay and set_output_delay are tailored to allow copying numbers from the counterpart device’s datasheet directly. However if we want to constrain the internal delay with these, the sampling clock’s period needs to be taken into account. So for the purpose of constraining the internal delay, set_input_delay and set_output_delay’s values must be adjusted if the clock’s frequency changes, and that’s an unnecessary headache.

One could have hoped that there would be a way to constrain the plain combinatoric path between a port and a register. It seems however like there’s no way to do this, but that Timing Analyzer is being a bit too helpful: When any (or both) of the endpoints of a set_max_delay constraint is a register, the clock delay path is taken into consideration. In other words, if the source of the delay path is a register, the clock path delay is added to the constrained path to represent the fact that the data toggle from the source register is delayed by this path. Likewise, if the destination of the constraint is a register, the clock path is added to the timing requirement (relaxes the constraint) to represent that the destination register samples its input later.

This holds true no matter of how the register endpoint is given to the constraint command: Quite obviously, if get_regs was used to select the relevant endpoint, the clock path is included in the math. But it’s less obvious, for example, that if the source endpoint was selected with get_pins on the registers’ output pin (e.g. [ get_pins -hierarchical the_sample_reg|d ]), the clock path is still included. Bottom line: No way to avoid having the clock path in the math. This is the reason for the manipulations with create_clock and set_annotated_delay above.

Examples of the timing obtained with set_max_delay are given below.

set_false_path -hold

These set_false_path constraints disable the timing calculation for the registers’ hold requirement (note the -hold flag). Without these two constraints, Timing Analyzer will mark the relevant I/O ports (partly) unconstrained, even if they have related set_max_delay constraints. This has no practical implication except that the “TimeQuest Timing Analyzer” group in the GUI’s compilation report pane is marked red, indicating there’s a timing problem.

The sole purpose of these set_false_path constraints is hence to tell the tools not to bother about the hold paths, avoiding the said red color in the GUI.

As with any set_false_path constraint, care must be taken not to include any unintended paths.

Hold timing is irrelevant for the purpose of ensuring I/O register packing. Neither does it have any significance when timing against the external device, as its hold timing should be ensured by manual timing calculations. As for timing a loop from the FPGA to the device and back this is unnecessary as well: Failing the receiving register’s hold timing in this case requires that the receiver’s hold time is shorter than the clock-to-output (which involves driving a physical pin and its equivalent capacitor) plus the external device’s response time to the toggling signal. So this is by far unrealistic.

One could think that rather than making a false path, a reasonable set_min_delay constraint would do the job. But no: Any set_min_delay, which in turn activates hold time constraining, leads to an “Input Pin to Input Register Delay” as shown in this other post, but for other reasons and with another behavior. In particular, with the constraint setting of this post, this Input Pin delay is added even if that causes a failure of the set_max_delay constraint.

The underlying reason is to compensate for the clock delay: The tools must ensure that the clock arrives to the input register before the data on its input port toggles. Otherwise, the data sampled for the minimal clock case is different from the case of the maximal clock delay (for which the data toggle is obviously after the clock toggle).

Given the delay in the clock path, this forces the tools to insert a delay before the input register that is at least the clock time delay. When clock delay compensation is enabled at the PLL (and the originating clock is external), the PLL is set to create a negative clock delay, hence eliminating the need for this Input Pin delay.

But it gets worse with a clock generated internally: It’s not completely clear why, but even if the clock path is set to zero with the set_annotate_delay statement as said above, the tools keep adding this delay. Also regardless of whether the PLL is set to compensate for the clock delay. One explanation can be found in set_annotated_delay’s help text saying “This assignment is for timing analysis only, and is not considered during timing-driven compilation”. But this still doesn’t explain why it’s inserted even with the clock path compensation of the PLL enabled. So the conclusion is that the tools weren’t really meant to handle this internally generated clock scheme.

Bottom line: Don’t make any set_min_delay constraints on this path, and surely not set_input_delay -min or set_output_delay -min (the latter two will mess up things even worse. Believe me on that).

Constraints for crossing clock domain

This is somewhat unrelated, but it’s another aspect of how set_max_delay path works.

When crossing clock domains, it’s common to put two registers in series, so that the first register is a metastability guard, and the second samples the signal safely in the destination clock domain.

But since the paths crossing clock domains are not timed by the tools, they may in theory have an arbitrarily high propagation delay. This undermines the whole idea of the metastability guard. So to be extra safe, it makes sense to constrain these paths in order to ensure that the path delay is limited to something sensible.

Unfortunately, there is nothing better than set_max_delay for this purpose, which takes the clock delays into account. As these two clocks are unrelated, this makes no sense at all, but this is what Quartus offers. It would have been much better to constrain just the data path, and maybe creating a special clock and using set_annotated_delay as suggested above would do the trick.

But I’ll suggest the simple and crude method:

set_max_delay -from [ get_clocks *|some_ins|*|tx_clkout] \
    -to [ get_clocks *|some_ins|*|rx_clkout] 4
set_max_delay -from [ get_clocks *|some_ins|*|rx_clkout] \
    -to [ get_clocks *|some_ins|*|tx_clkout] 4

set_false_path -hold -from [ get_clocks *|some_ins|*|tx_clkout] \
    -to [ get_clocks *|some_ins|*|rx_clkout]
set_false_path -hold -from [ get_clocks *|some_ins|*|rx_clkout] \
    -to [ get_clocks *|some_ins|*|tx_clkout]

Choosing the delay as 4 ns as shown above keeps the delays sensibly small on a Cyclone 10, but this is something to verify separately on each design with the Timing Analyzer.

As for the two false path settings: Note that they are only for hold timing. This is sometimes necessary if the tools consider the clocks related, in which case the hold timing might fail because of the different clock delays. Since the clocks are treated as unrelated in the logic design, the hold timing is pointless.

Timing example: Register to pin (output)

+-------------------------------------------------------------+
; Path Summary                                                ;
+---------------------+---------------------------------------+
; Property            ; Value                                 ;
+---------------------+---------------------------------------+
; From Node           ; video_adc:video_adc_ins|pixadc_clk[1] ;
; To Node             ; pixadc_clk[1]                         ;
; Launch Clock        ; main_clk                              ;
; Latch Clock         ; n/a                                   ;
; Max Delay Exception ; 2.700                                 ;
; Data Arrival Time   ; 2.666                                 ;
; Data Required Time  ; 2.700                                 ;
; Slack               ; 0.034                                 ;
+---------------------+---------------------------------------+

+---------------------------------------------------------------------------------------------------------------------------------------------+
; Data Arrival Path                                                                                                                           ;
+---------+---------+----+------+--------+-----------------------+----------------------------------------------------------------------------+
; Total   ; Incr    ; RF ; Type ; Fanout ; Location              ; Element                                                                    ;
+---------+---------+----+------+--------+-----------------------+----------------------------------------------------------------------------+
; 0.000   ; 0.000   ;    ;      ;        ;                       ; launch edge time                                                           ;
; 0.559   ; 0.559   ;    ;      ;        ;                       ; clock path                                                                 ;
;   0.000 ;   0.000 ;    ;      ;        ;                       ; source latency                                                             ;
;   0.000 ;   0.000 ;    ;      ; 13     ; CLKCTRL_G13           ; clkrst_ins|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk ;
;   0.000 ;   0.000 ; RR ; IC   ; 1      ; DDIOOUTCELL_X0_Y10_N4 ; video_adc_ins|pixadc_clk[1]|clk                                            ;
;   0.559 ;   0.559 ; RR ; CELL ; 1      ; DDIOOUTCELL_X0_Y10_N4 ; video_adc:video_adc_ins|pixadc_clk[1]                                      ;
; 2.666   ; 2.107   ;    ;      ;        ;                       ; data path                                                                  ;
;   0.771 ;   0.212 ;    ; uTco ; 1      ; DDIOOUTCELL_X0_Y10_N4 ; video_adc:video_adc_ins|pixadc_clk[1]                                      ;
;   1.268 ;   0.497 ; RR ; CELL ; 1      ; DDIOOUTCELL_X0_Y10_N4 ; video_adc_ins|pixadc_clk[1]|q                                              ;
;   1.268 ;   0.000 ; RR ; IC   ; 2      ; IOOBUF_X0_Y10_N2      ; pixadc_clk[1]~output|i                                                     ;
;   2.666 ;   1.398 ; RR ; CELL ; 1      ; IOOBUF_X0_Y10_N2      ; pixadc_clk[1]~output|o                                                     ;
;   2.666 ;   0.000 ; RR ; CELL ; 0      ; PIN_R2                ; pixadc_clk[1]                                                              ;
+---------+---------+----+------+--------+-----------------------+----------------------------------------------------------------------------+

+-------------------------------------------------------------------------+
; Data Required Path                                                      ;
+---------+---------+----+------+--------+----------+---------------------+
; Total   ; Incr    ; RF ; Type ; Fanout ; Location ; Element             ;
+---------+---------+----+------+--------+----------+---------------------+
; 2.700   ; 2.700   ;    ;      ;        ;          ; latch edge time     ;
; 2.700   ; 0.000   ;    ;      ;        ;          ; clock path          ;
;   2.700 ;   0.000 ; R  ;      ;        ;          ; clock network delay ;
; 2.700   ; 0.000   ; R  ; oExt ; 0      ; PIN_R2   ; pixadc_clk[1]       ;
+---------+---------+----+------+--------+----------+---------------------+

The interconnect delay on the line after location CLKCTRL_G13 is the global clock’s delay, which the set_annotate_delay constraint forces to zero. Without that, it would have read 1.076 ns instead. Together with the create_clock assignment on the output pin, the only part left in the clock path is the 0.559 ns corresponding to the clock’s delay within the register itself (it’s not the clock-to-output, that one follows as uTco).

A regular create_clock declaration would have yielded the following at the beginning of the datapath instead:

+---------+---------+----+------+--------+-----------------------+------------------------------------------------------------------------------+
; Total   ; Incr    ; RF ; Type ; Fanout ; Location              ; Element                                                                      ;
+---------+---------+----+------+--------+-----------------------+------------------------------------------------------------------------------+
; 0.000   ; 0.000   ;    ;      ;        ;                       ; launch edge time                                                             ;
; 2.716   ; 2.716   ;    ;      ;        ;                       ; clock path                                                                   ;
;   0.000 ;   0.000 ;    ;      ;        ;                       ; source latency                                                               ;
;   0.000 ;   0.000 ;    ;      ; 1      ; PLL_3                 ; clkrst_ins|altpll_component|auto_generated|pll1|clk[0]                       ;
;   2.157 ;   2.157 ; RR ; IC   ; 1      ; CLKCTRL_G13           ; clkrst_ins|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
;   2.157 ;   0.000 ; RR ; CELL ; 13     ; CLKCTRL_G13           ; clkrst_ins|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
;   2.157 ;   0.000 ; RR ; IC   ; 1      ; DDIOOUTCELL_X0_Y10_N4 ; video_adc_ins|pixadc_clk[1]|clk                                              ;
;   2.716 ;   0.559 ; RR ; CELL ; 1      ; DDIOOUTCELL_X0_Y10_N4 ; video_adc:video_adc_ins|pixadc_clk[1]

The above relates to a PLL without delay compensation.

Timing example: Pin to register (input)

+-----------------------------------------------------------+
; Path Summary                                              ;
+---------------------+-------------------------------------+
; Property            ; Value                               ;
+---------------------+-------------------------------------+
; From Node           ; pixadc_da[2]                        ;
; To Node             ; video_adc:video_adc_ins|samp_reg[2] ;
; Launch Clock        ; n/a                                 ;
; Latch Clock         ; main_clk                            ;
; Max Delay Exception ; 0.700                               ;
; Data Arrival Time   ; 0.992                               ;
; Data Required Time  ; 1.020                               ;
; Slack               ; 0.028                               ;
+---------------------+-------------------------------------+

+-------------------------------------------------------------------------------------------------+
; Data Arrival Path                                                                               ;
+---------+---------+----+------+--------+------------------+-------------------------------------+
; Total   ; Incr    ; RF ; Type ; Fanout ; Location         ; Element                             ;
+---------+---------+----+------+--------+------------------+-------------------------------------+
; 0.000   ; 0.000   ;    ;      ;        ;                  ; launch edge time                    ;
; 0.000   ; 0.000   ;    ;      ;        ;                  ; clock path                          ;
;   0.000 ;   0.000 ; R  ;      ;        ;                  ; clock network delay                 ;
; 0.000   ; 0.000   ; R  ; iExt ; 1      ; PIN_W2           ; pixadc_da[2]                        ;
; 0.992   ; 0.992   ;    ;      ;        ;                  ; data path                           ;
;   0.000 ;   0.000 ; RR ; IC   ; 1      ; IOIBUF_X0_Y7_N15 ; pixadc_da[2]~input|i                ;
;   0.748 ;   0.748 ; RR ; CELL ; 1      ; IOIBUF_X0_Y7_N15 ; pixadc_da[2]~input|o                ;
;   0.748 ;   0.000 ; RR ; IC   ; 1      ; FF_X0_Y7_N17     ; video_adc_ins|samp_reg[2]|d         ;
;   0.992 ;   0.244 ; RR ; CELL ; 1      ; FF_X0_Y7_N17     ; video_adc:video_adc_ins|samp_reg[2] ;
+---------+---------+----+------+--------+------------------+-------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------+
; Data Required Path                                                                                                                 ;
+---------+---------+----+------+--------+--------------+----------------------------------------------------------------------------+
; Total   ; Incr    ; RF ; Type ; Fanout ; Location     ; Element                                                                    ;
+---------+---------+----+------+--------+--------------+----------------------------------------------------------------------------+
; 0.700   ; 0.700   ;    ;      ;        ;              ; latch edge time                                                            ;
; 1.124   ; 0.424   ;    ;      ;        ;              ; clock path                                                                 ;
;   0.700 ;   0.000 ;    ;      ;        ;              ; source latency                                                             ;
;   0.700 ;   0.000 ;    ;      ; 13     ; CLKCTRL_G13  ; clkrst_ins|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk ;
;   0.700 ;   0.000 ; RR ; IC   ; 1      ; FF_X0_Y7_N17 ; video_adc_ins|samp_reg[2]|clk                                              ;
;   1.124 ;   0.424 ; RR ; CELL ; 1      ; FF_X0_Y7_N17 ; video_adc:video_adc_ins|samp_reg[2]                                        ;
; 1.020   ; -0.104  ;    ; uTsu ; 1      ; FF_X0_Y7_N17 ; video_adc:video_adc_ins|samp_reg[2]                                        ;
+---------+---------+----+------+--------+--------------+----------------------------------------------------------------------------+

First, note the zero time increment marked in green above. It just confirms that no Input Pin delay was inserted by the tools.

Once again, the zero increment in red is the result of the set_annotate_delay constraint. It would have read 1.028 ns otherwise.

And again, a regular create_clock declaration would have yielded the following at the beginning of the datapath instead:

+--------------------------------------------------------------------------------------------------------------------------------------+
; Data Required Path                                                                                                                   ;
+---------+---------+----+------+--------+--------------+------------------------------------------------------------------------------+
; Total   ; Incr    ; RF ; Type ; Fanout ; Location     ; Element                                                                      ;
+---------+---------+----+------+--------+--------------+------------------------------------------------------------------------------+
; 0.700   ; 0.700   ;    ;      ;        ;              ; latch edge time                                                              ;
; 3.194   ; 2.494   ;    ;      ;        ;              ; clock path                                                                   ;
;   0.700 ;   0.000 ;    ;      ;        ;              ; source latency                                                               ;
;   0.700 ;   0.000 ;    ;      ; 1      ; PLL_3        ; clkrst_ins|altpll_component|auto_generated|pll1|clk[0]                       ;
;   2.770 ;   2.070 ; RR ; IC   ; 1      ; CLKCTRL_G13  ; clkrst_ins|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
;   2.770 ;   0.000 ; RR ; CELL ; 13     ; CLKCTRL_G13  ; clkrst_ins|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
;   2.770 ;   0.000 ; RR ; IC   ; 1      ; FF_X0_Y7_N17 ; video_adc_ins|samp_reg[2]|clk                                                ;
;   3.194 ;   0.424 ; RR ; CELL ; 1      ; FF_X0_Y7_N17 ; video_adc:video_adc_ins|samp_reg[2]                                          ;
; 3.090   ; -0.104  ;    ; uTsu ; 1      ; FF_X0_Y7_N17 ; video_adc:video_adc_ins|samp_reg[2]                                          ;
+---------+---------+----+------+--------+--------------+------------------------------------------------------------------------------+

The figures differ from the corresponding figures for the output timing, because increments in the data required path relax the constraint, so the tools pick the minimal delays here.

Loop timing budget

OK, so we have one constraint requiring the data on output ports to be valid 2.7 ns after main_clk. We have another constraint saying that the delay from an input pin to a register is no more than 0.7 ns. The clock period is 16.666 ns. Does it mean that the difference, 16.666 – (2.7 + 0.7) = 13.266 ns is the time allowed for the device to respond?

In other words, if the output signal is a clock that triggers the outputs of the external device, is it enough that the device’s clock-to-output, plus the PCB trace delay, mount up to less than 13.266 ns?

The answer is almost yes. The only thing not taken into account is the skew between the clocks as they arrive to each of the two I/O registers, because the global clock delay was forced to zero. But the skew is typically less than a few hundred picoseconds. All the rest is covered.

Note in particular that in the input timing calculation, the data path (from the pin to the register) isn’t compared with the constrained time (0.7 ns), but rather with the constrained time, plus the register’s internal clock delay, minus the register’s setup time. In other words, these small adjustments result in an accurate answer to if 0.7 ns from the pin to the clock is OK.

And because the delay calculations for the input and output delays begin at exactly the same global clock toggle at the register’s pins, the overall result is valid and accurate, except for the global clock skew, which isn’t taken into account.

Conclusion

It’s quite peculiar that this seemingly simple task of constraining the I/O timing turned out to be as difficult. It’s also unfortunate that this requires some crippling of the regular register-to-register calculations.

What makes this even more unfortunate, is that this constraining is practically necessary to ensure that no input pin delay is inserted by the tools. It’s not just a safety mechanism to set the alarm if the I/O registers slip away into the logic fabric.

One could argue that if timing is important, an external clock should have been used as a direct reference, in which case this whole issue would not have risen. But the point is that even if the design doesn’t squeeze the best possible timing performance from the FPGA, proper constraining is still required. It’s the designers prerogative to use the FPGA in a suboptimal way for ease and laziness, as long as the application’s requirements are met. It’s too bad that the punishment comes from the tools themselves, turning a straightforward task into a saga.

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